Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99060203	1			T1	4		T2	303		T3	162173
all_pins[1]	99060203	1			T1	4		T2	303		T3	162173
all_pins[2]	99060203	1			T1	4		T2	303		T3	162173

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296339422	1			T1	12		T2	895		T3	486059
values[0x1]	841187	1			T2	14		T3	460		T4	12
transitions[0x0=>0x1]	838919	1			T2	14		T3	460		T4	12
transitions[0x1=>0x0]	838942	1			T2	14		T3	460		T4	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98556914	1			T1	4		T2	289		T3	161713
all_pins[0]	values[0x1]	503289	1			T2	14		T3	460		T4	12
all_pins[0]	transitions[0x0=>0x1]	503273	1			T2	14		T3	460		T4	12
all_pins[0]	transitions[0x1=>0x0]	5809	1			T5	58		T7	2		T24	4
all_pins[1]	values[0x0]	99054378	1			T1	4		T2	303		T3	162173
all_pins[1]	values[0x1]	5825	1			T5	58		T7	2		T24	4
all_pins[1]	transitions[0x0=>0x1]	5598	1			T5	58		T7	2		T24	4
all_pins[1]	transitions[0x1=>0x0]	331846	1			T17	81		T48	893		T38	502
all_pins[2]	values[0x0]	98728130	1			T1	4		T2	303		T3	162173
all_pins[2]	values[0x1]	332073	1			T17	81		T48	893		T38	502
all_pins[2]	transitions[0x0=>0x1]	330048	1			T17	81		T48	893		T38	501
all_pins[2]	transitions[0x1=>0x0]	501287	1			T2	14		T3	460		T4	12