Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	671	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5404	1			T5	13		T23	9		T7	2
len_601_800	12458	1			T5	39		T6	1		T23	16
len_401_600	8153	1			T5	23		T6	1		T23	10
len_201_400	16362	1			T5	15		T13	251		T23	6
len_65_200	72848	1			T5	9		T13	680		T80	685
len_min_for_xof_require_squeeze	990	1			T13	10		T80	9		T17	1
len_keccak_block_sizes[72]	728	1			T13	5		T80	9		T107	5
len_keccak_block_sizes[104]	740	1			T13	5		T80	9		T107	5
len_keccak_block_sizes[136]	732	1			T13	5		T80	9		T107	5
len_keccak_block_sizes[144]	291	1			T13	5		T107	5		T37	1
len_keccak_block_sizes[168]	292	1			T13	5		T107	5		T38	1
len_datapath_width	14260	1			T2	3		T4	3		T11	3
len_2_63	211766	1			T2	6		T3	310		T4	6
len_1	62	1			T212	1		T156	2		T31	3