Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::state_read_mask_cg

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
share	2	0	2	100.00	100	1	1	2
state_read_mask	4	0	4	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_mask_share_cross	8	0	8	100.00	100	1	1	0

Summary for Variable share

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for share

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10634403

1

T2

96

T3

3720

T4

96

auto[1]

10634368

1

T2

96

T3

3720

T4

96

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Summary for Variable state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for state_read_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	21033481	1			T2	192		T3	7440		T4	192
triple_byte_access	78476	1			T5	58		T13	620		T80	558
halfword_access	78736	1			T5	62		T13	632		T80	558
byte_access	78078	1			T5	52		T13	620		T80	558

---

Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for state_mask_share_cross

Bins

share	state_read_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	10516758	1			T2	96		T3	3720		T4	96
auto[0]	triple_byte_access	39238	1			T5	29		T13	310		T80	279
auto[0]	halfword_access	39368	1			T5	31		T13	316		T80	279
auto[0]	byte_access	39039	1			T5	26		T13	310		T80	279
auto[1]	word_access	10516723	1			T2	96		T3	3720		T4	96
auto[1]	triple_byte_access	39238	1			T5	29		T13	310		T80	279
auto[1]	halfword_access	39368	1			T5	31		T13	316		T80	279
auto[1]	byte_access	39039	1			T5	26		T13	310		T80	279