Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T147 4 T148 7 T149 4
all_values[1] 272 1 T147 4 T148 7 T149 4
all_values[2] 272 1 T147 4 T148 7 T149 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 417 1 T147 4 T148 8 T149 3
auto[1] 399 1 T147 8 T148 13 T149 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 391 1 T147 5 T148 13 T149 8
auto[1] 425 1 T147 7 T148 8 T149 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 496 1 T147 7 T148 14 T149 9
auto[1] 320 1 T147 5 T148 7 T149 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 70 1 T148 1 T149 1 T183 3
all_values[0] auto[0] auto[0] auto[1] 24 1 T187 2 T188 1 T189 1
all_values[0] auto[0] auto[1] auto[0] 41 1 T147 1 T148 3 T149 3
all_values[0] auto[0] auto[1] auto[1] 30 1 T147 1 T148 1 T190 3
all_values[0] auto[1] auto[0] auto[1] 61 1 T183 2 T191 2 T187 2
all_values[0] auto[1] auto[1] auto[1] 46 1 T147 2 T148 2 T190 1
all_values[1] auto[0] auto[0] auto[0] 82 1 T148 2 T183 4 T191 2
all_values[1] auto[0] auto[1] auto[0] 91 1 T147 2 T148 3 T149 2
all_values[1] auto[1] auto[0] auto[1] 46 1 T148 1 T149 1 T187 1
all_values[1] auto[1] auto[1] auto[1] 53 1 T147 2 T148 1 T149 1
all_values[2] auto[0] auto[0] auto[0] 55 1 T147 2 T148 3 T149 1
all_values[2] auto[0] auto[0] auto[1] 22 1 T147 1 T183 1 T189 3
all_values[2] auto[0] auto[1] auto[0] 52 1 T148 1 T149 1 T191 4
all_values[2] auto[0] auto[1] auto[1] 29 1 T149 1 T183 1 T188 2
all_values[2] auto[1] auto[0] auto[1] 57 1 T147 1 T148 1 T183 2
all_values[2] auto[1] auto[1] auto[1] 57 1 T148 2 T149 1 T183 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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