Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98771162	1			T1	1758		T2	291		T3	163781
all_values[1]	98771162	1			T1	1758		T2	291		T3	163781
all_values[2]	98771162	1			T1	1758		T2	291		T3	163781

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

515854

1

T1

468

T2

118

T3

14

auto[1]

295797632

1

T1

4806

T2

755

T3

491329

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294783372

1

T1

5223

T2

831

T3

489933

auto[1]

1530114

1

T1

51

T2

42

T3

1410

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	180495	1			T1	154		T2	85		T3	3
all_values[0]	auto[0]	auto[1]	2187	1			T1	2		T2	8		T3	4
all_values[0]	auto[1]	auto[0]	98080629	1			T1	1587		T2	192		T3	163308
all_values[0]	auto[1]	auto[1]	507851	1			T1	15		T2	6		T3	466
all_values[1]	auto[0]	auto[0]	172416	1			T1	154		T2	14		T9	15
all_values[1]	auto[0]	auto[1]	1497	1			T1	2		T2	4		T9	2
all_values[1]	auto[1]	auto[0]	98088708	1			T1	1587		T2	263		T3	163311
all_values[1]	auto[1]	auto[1]	508541	1			T1	15		T2	10		T3	470
all_values[2]	auto[0]	auto[0]	157653	1			T1	154		T2	5		T3	3
all_values[2]	auto[0]	auto[1]	1606	1			T1	2		T2	2		T3	4
all_values[2]	auto[1]	auto[0]	98103471	1			T1	1587		T2	272		T3	163308
all_values[2]	auto[1]	auto[1]	508432	1			T1	15		T2	12		T3	466