Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
297764 |
1 |
|
|
T1 |
32 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
397120 |
1 |
|
|
T2 |
16 |
|
T3 |
618 |
|
T12 |
128 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173781 |
1 |
|
|
T1 |
4 |
|
T2 |
6 |
|
T3 |
153 |
lower_val |
172458 |
1 |
|
|
T1 |
21 |
|
T2 |
6 |
|
T3 |
186 |
zero_val |
1874 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
247440 |
1 |
|
|
T1 |
18 |
|
T2 |
10 |
|
T3 |
154 |
lower_val |
248290 |
1 |
|
|
T1 |
14 |
|
T2 |
2 |
|
T3 |
142 |
zero_val |
199154 |
1 |
|
|
T2 |
6 |
|
T3 |
324 |
|
T12 |
68 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
36569 |
1 |
|
|
T1 |
2 |
|
T4 |
60 |
|
T22 |
46 |
higher_val |
higher_val |
auto[1] |
25259 |
1 |
|
|
T2 |
1 |
|
T3 |
32 |
|
T12 |
4 |
higher_val |
lower_val |
auto[0] |
37431 |
1 |
|
|
T1 |
2 |
|
T4 |
51 |
|
T22 |
34 |
higher_val |
lower_val |
auto[1] |
24928 |
1 |
|
|
T2 |
1 |
|
T3 |
31 |
|
T12 |
10 |
higher_val |
zero_val |
auto[0] |
110 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T83 |
1 |
higher_val |
zero_val |
auto[1] |
49484 |
1 |
|
|
T2 |
4 |
|
T3 |
89 |
|
T12 |
20 |
lower_val |
higher_val |
auto[0] |
36767 |
1 |
|
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
54 |
lower_val |
higher_val |
auto[1] |
24536 |
1 |
|
|
T2 |
3 |
|
T3 |
49 |
|
T12 |
7 |
lower_val |
lower_val |
auto[0] |
36837 |
1 |
|
|
T1 |
8 |
|
T12 |
1 |
|
T4 |
46 |
lower_val |
lower_val |
auto[1] |
24584 |
1 |
|
|
T3 |
45 |
|
T12 |
13 |
|
T13 |
42 |
lower_val |
zero_val |
auto[0] |
95 |
1 |
|
|
T73 |
1 |
|
T86 |
1 |
|
T35 |
1 |
lower_val |
zero_val |
auto[1] |
49639 |
1 |
|
|
T2 |
2 |
|
T3 |
92 |
|
T12 |
24 |
zero_val |
higher_val |
auto[0] |
530 |
1 |
|
|
T2 |
1 |
|
T9 |
1 |
|
T4 |
2 |
zero_val |
higher_val |
auto[1] |
153 |
1 |
|
|
T13 |
1 |
|
T4 |
1 |
|
T87 |
1 |
zero_val |
lower_val |
auto[0] |
507 |
1 |
|
|
T1 |
1 |
|
T12 |
1 |
|
T4 |
3 |
zero_val |
lower_val |
auto[1] |
137 |
1 |
|
|
T4 |
1 |
|
T51 |
1 |
|
T87 |
3 |
zero_val |
zero_val |
auto[0] |
296 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T4 |
1 |
zero_val |
zero_val |
auto[1] |
251 |
1 |
|
|
T13 |
1 |
|
T51 |
1 |
|
T87 |
2 |