Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10323	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8659	1			T3	24		T13	19		T4	11
len_5001_7500	13584	1			T3	24		T13	18		T4	44
len_2501_5000	9050	1			T3	24		T13	18		T4	8
len_1025_2500	5253	1			T3	14		T13	11		T4	3
len_769_1024	6555	1			T1	3		T3	2		T12	8
len_513_768	7211	1			T1	2		T3	3		T12	8
len_257_512	21468	1			T1	1		T3	2		T12	6
len_0_256	257773	1			T1	5		T2	9		T3	211
len_keccak_block_sizes[72]	725	1			T3	2		T13	2		T51	2
len_keccak_block_sizes[104]	628	1			T3	2		T13	2		T51	2
len_keccak_block_sizes[136]	521	1			T13	2		T4	1		T51	2
len_keccak_block_sizes[144]	430	1			T12	1		T84	1		T87	3
len_keccak_block_sizes[168]	330	1			T5	1		T87	3		T86	3
len_1	747	1			T3	2		T13	2		T51	2
len_0	1163	1			T3	2		T13	2		T4	5