Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98771162	1			T1	1758		T2	291		T3	163781
all_pins[1]	98771162	1			T1	1758		T2	291		T3	163781
all_pins[2]	98771162	1			T1	1758		T2	291		T3	163781

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295503944	1			T1	5259		T2	866		T3	490877
values[0x1]	809542	1			T1	15		T2	7		T3	466
transitions[0x0=>0x1]	807508	1			T1	15		T2	7		T3	466
transitions[0x1=>0x0]	807527	1			T1	15		T2	7		T3	466

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98263311	1			T1	1743		T2	285		T3	163315
all_pins[0]	values[0x1]	507851	1			T1	15		T2	6		T3	466
all_pins[0]	transitions[0x0=>0x1]	507838	1			T1	15		T2	6		T3	466
all_pins[0]	transitions[0x1=>0x0]	6467	1			T2	1		T4	125		T5	95
all_pins[1]	values[0x0]	98764682	1			T1	1758		T2	290		T3	163781
all_pins[1]	values[0x1]	6480	1			T2	1		T4	125		T5	95
all_pins[1]	transitions[0x0=>0x1]	6233	1			T2	1		T4	101		T5	95
all_pins[1]	transitions[0x1=>0x0]	294964	1			T4	13707		T5	677		T36	1241
all_pins[2]	values[0x0]	98475951	1			T1	1758		T2	291		T3	163781
all_pins[2]	values[0x1]	295211	1			T4	13731		T5	677		T36	1241
all_pins[2]	transitions[0x0=>0x1]	293437	1			T4	13638		T5	677		T36	1241
all_pins[2]	transitions[0x1=>0x0]	506096	1			T1	15		T2	6		T3	466