Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	674	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5516	1			T1	2		T12	6		T4	65
len_601_800	12461	1			T1	3		T12	13		T4	121
len_401_600	8308	1			T1	3		T12	6		T4	83
len_201_400	16481	1			T12	7		T4	38		T5	13
len_65_200	73739	1			T1	2		T12	1		T4	59
len_min_for_xof_require_squeeze	993	1			T4	1		T5	1		T87	9
len_keccak_block_sizes[72]	750	1			T87	9		T86	5		T187	9
len_keccak_block_sizes[104]	754	1			T87	9		T34	1		T86	5
len_keccak_block_sizes[136]	765	1			T84	1		T87	9		T85	1
len_keccak_block_sizes[144]	285	1			T4	1		T86	5		T188	5
len_keccak_block_sizes[168]	280	1			T4	1		T86	5		T188	5
len_datapath_width	13914	1			T2	3		T4	25		T5	2
len_2_63	214405	1			T1	5		T2	6		T3	310
len_1	59	1			T189	1		T57	2		T190	1