Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10754547 |
1 |
|
|
T1 |
1812 |
|
T2 |
96 |
|
T3 |
3720 |
auto[1] |
10754494 |
1 |
|
|
T1 |
1800 |
|
T2 |
96 |
|
T3 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21270823 |
1 |
|
|
T1 |
3592 |
|
T2 |
192 |
|
T3 |
7440 |
triple_byte_access |
79248 |
1 |
|
|
T1 |
10 |
|
T12 |
20 |
|
T4 |
196 |
halfword_access |
79520 |
1 |
|
|
T1 |
2 |
|
T12 |
24 |
|
T4 |
198 |
byte_access |
79450 |
1 |
|
|
T1 |
8 |
|
T9 |
2 |
|
T12 |
14 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10635438 |
1 |
|
|
T1 |
1802 |
|
T2 |
96 |
|
T3 |
3720 |
auto[0] |
triple_byte_access |
39624 |
1 |
|
|
T1 |
5 |
|
T12 |
10 |
|
T4 |
98 |
auto[0] |
halfword_access |
39760 |
1 |
|
|
T1 |
1 |
|
T12 |
12 |
|
T4 |
99 |
auto[0] |
byte_access |
39725 |
1 |
|
|
T1 |
4 |
|
T9 |
1 |
|
T12 |
7 |
auto[1] |
word_access |
10635385 |
1 |
|
|
T1 |
1790 |
|
T2 |
96 |
|
T3 |
3720 |
auto[1] |
triple_byte_access |
39624 |
1 |
|
|
T1 |
5 |
|
T12 |
10 |
|
T4 |
98 |
auto[1] |
halfword_access |
39760 |
1 |
|
|
T1 |
1 |
|
T12 |
12 |
|
T4 |
99 |
auto[1] |
byte_access |
39725 |
1 |
|
|
T1 |
4 |
|
T9 |
1 |
|
T12 |
7 |