Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.95 98.10 92.58 99.89 95.45 95.97 98.89 97.75


Total test records in report: 1238
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T1060 /workspace/coverage/default/22.kmac_test_vectors_shake_256.1521766584 Apr 21 03:44:58 PM PDT 24 Apr 21 04:58:24 PM PDT 24 106333246179 ps
T1061 /workspace/coverage/default/6.kmac_test_vectors_sha3_256.518641467 Apr 21 03:38:12 PM PDT 24 Apr 21 04:13:42 PM PDT 24 76205121296 ps
T1062 /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3478980345 Apr 21 03:50:15 PM PDT 24 Apr 21 04:10:54 PM PDT 24 10686766360 ps
T1063 /workspace/coverage/default/12.kmac_long_msg_and_output.2584549430 Apr 21 03:41:11 PM PDT 24 Apr 21 04:01:20 PM PDT 24 33480677337 ps
T1064 /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1416715376 Apr 21 03:46:59 PM PDT 24 Apr 21 04:24:29 PM PDT 24 248462062418 ps
T1065 /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.320112397 Apr 21 03:42:29 PM PDT 24 Apr 21 03:42:35 PM PDT 24 116633793 ps
T1066 /workspace/coverage/default/23.kmac_sideload.3285118578 Apr 21 03:45:12 PM PDT 24 Apr 21 03:53:14 PM PDT 24 138607107600 ps
T1067 /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1390526749 Apr 21 03:46:20 PM PDT 24 Apr 21 04:26:57 PM PDT 24 100348632344 ps
T1068 /workspace/coverage/default/6.kmac_test_vectors_sha3_384.235778631 Apr 21 03:38:14 PM PDT 24 Apr 21 04:04:34 PM PDT 24 30481302850 ps
T1069 /workspace/coverage/default/22.kmac_sideload.2753375094 Apr 21 03:44:52 PM PDT 24 Apr 21 03:50:03 PM PDT 24 12776981502 ps
T1070 /workspace/coverage/default/35.kmac_test_vectors_shake_128.408142996 Apr 21 03:49:25 PM PDT 24 Apr 21 05:30:38 PM PDT 24 3556165188043 ps
T1071 /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2923911381 Apr 21 03:55:03 PM PDT 24 Apr 21 04:16:33 PM PDT 24 136805961252 ps
T1072 /workspace/coverage/default/28.kmac_smoke.1085080718 Apr 21 03:46:34 PM PDT 24 Apr 21 03:46:52 PM PDT 24 1115246136 ps
T1073 /workspace/coverage/default/35.kmac_test_vectors_sha3_224.798754871 Apr 21 03:49:22 PM PDT 24 Apr 21 04:25:24 PM PDT 24 49317822795 ps
T1074 /workspace/coverage/default/27.kmac_error.910249100 Apr 21 03:46:34 PM PDT 24 Apr 21 03:48:16 PM PDT 24 4616677016 ps
T1075 /workspace/coverage/default/5.kmac_test_vectors_sha3_256.4054195655 Apr 21 03:37:25 PM PDT 24 Apr 21 04:12:05 PM PDT 24 30985219649 ps
T1076 /workspace/coverage/default/48.kmac_test_vectors_shake_256.410746211 Apr 21 03:55:45 PM PDT 24 Apr 21 05:10:29 PM PDT 24 139229641719 ps
T1077 /workspace/coverage/default/41.kmac_long_msg_and_output.308987457 Apr 21 03:51:52 PM PDT 24 Apr 21 03:55:48 PM PDT 24 12742043126 ps
T1078 /workspace/coverage/default/23.kmac_test_vectors_sha3_224.372978283 Apr 21 03:45:10 PM PDT 24 Apr 21 04:21:12 PM PDT 24 101363139732 ps
T1079 /workspace/coverage/default/14.kmac_test_vectors_sha3_512.145937947 Apr 21 03:42:04 PM PDT 24 Apr 21 04:01:25 PM PDT 24 11749499005 ps
T1080 /workspace/coverage/default/41.kmac_burst_write.3520614406 Apr 21 03:51:55 PM PDT 24 Apr 21 04:04:15 PM PDT 24 24124783474 ps
T1081 /workspace/coverage/default/15.kmac_test_vectors_shake_128.4234659822 Apr 21 03:42:27 PM PDT 24 Apr 21 05:20:23 PM PDT 24 355058271433 ps
T1082 /workspace/coverage/default/23.kmac_error.3827740333 Apr 21 03:45:21 PM PDT 24 Apr 21 03:54:05 PM PDT 24 8777850160 ps
T1083 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1550780405 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:46 PM PDT 24 50220790 ps
T185 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2769085927 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:29 PM PDT 24 165367230 ps
T1084 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1079482075 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:44 PM PDT 24 397702782 ps
T146 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2236800445 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:15 PM PDT 24 757544572 ps
T128 /workspace/coverage/cover_reg_top/16.kmac_intr_test.2578927889 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:26 PM PDT 24 40641221 ps
T129 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3108177913 Apr 21 12:48:46 PM PDT 24 Apr 21 12:48:48 PM PDT 24 46231062 ps
T147 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2316590186 Apr 21 12:48:04 PM PDT 24 Apr 21 12:48:06 PM PDT 24 281953166 ps
T89 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2261193146 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:40 PM PDT 24 29350055 ps
T164 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.250519690 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:19 PM PDT 24 1116903353 ps
T125 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.125674166 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:17 PM PDT 24 380506737 ps
T160 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2585527690 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:18 PM PDT 24 56335682 ps
T90 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2416794233 Apr 21 12:48:53 PM PDT 24 Apr 21 12:48:56 PM PDT 24 198320072 ps
T186 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1852281253 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:17 PM PDT 24 24728467 ps
T1085 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2557528369 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:17 PM PDT 24 79246757 ps
T130 /workspace/coverage/cover_reg_top/9.kmac_intr_test.728255909 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:27 PM PDT 24 22519858 ps
T106 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1844576563 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:20 PM PDT 24 120197220 ps
T167 /workspace/coverage/cover_reg_top/42.kmac_intr_test.1421480376 Apr 21 12:48:36 PM PDT 24 Apr 21 12:48:37 PM PDT 24 58846267 ps
T1086 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3497815473 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:25 PM PDT 24 77634732 ps
T148 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.49308797 Apr 21 12:48:05 PM PDT 24 Apr 21 12:48:28 PM PDT 24 3349246982 ps
T168 /workspace/coverage/cover_reg_top/43.kmac_intr_test.2495810380 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:27 PM PDT 24 21232768 ps
T91 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.141374841 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:18 PM PDT 24 132358017 ps
T1087 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.290132332 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:30 PM PDT 24 22308230 ps
T161 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2457071723 Apr 21 12:48:51 PM PDT 24 Apr 21 12:48:52 PM PDT 24 17010229 ps
T1088 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.582147396 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:27 PM PDT 24 399199174 ps
T1089 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3878696548 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 42943793 ps
T171 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1804685533 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:34 PM PDT 24 44377336 ps
T162 /workspace/coverage/cover_reg_top/34.kmac_intr_test.817180661 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:36 PM PDT 24 14865942 ps
T107 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.678881050 Apr 21 12:48:11 PM PDT 24 Apr 21 12:48:13 PM PDT 24 346578615 ps
T149 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.933492032 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:14 PM PDT 24 337436804 ps
T1090 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3220413773 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:19 PM PDT 24 413114866 ps
T1091 /workspace/coverage/cover_reg_top/14.kmac_intr_test.661362949 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:32 PM PDT 24 26338760 ps
T92 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1589757163 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:15 PM PDT 24 159273665 ps
T169 /workspace/coverage/cover_reg_top/22.kmac_intr_test.3952543176 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:47 PM PDT 24 13309266 ps
T1092 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3529628581 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:32 PM PDT 24 72848880 ps
T126 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3386350395 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:18 PM PDT 24 334925360 ps
T93 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.898658212 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:22 PM PDT 24 336977285 ps
T150 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3380292773 Apr 21 12:48:01 PM PDT 24 Apr 21 12:48:03 PM PDT 24 360564356 ps
T94 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3946088016 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:17 PM PDT 24 69296377 ps
T95 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4241964579 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:30 PM PDT 24 82051830 ps
T1093 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1620887734 Apr 21 12:48:00 PM PDT 24 Apr 21 12:48:02 PM PDT 24 67747209 ps
T163 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.765938110 Apr 21 12:48:07 PM PDT 24 Apr 21 12:48:09 PM PDT 24 286871128 ps
T170 /workspace/coverage/cover_reg_top/23.kmac_intr_test.1786798591 Apr 21 12:48:43 PM PDT 24 Apr 21 12:48:44 PM PDT 24 20726597 ps
T1094 /workspace/coverage/cover_reg_top/19.kmac_intr_test.816756311 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:43 PM PDT 24 17625239 ps
T1095 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1111953556 Apr 21 12:48:20 PM PDT 24 Apr 21 12:48:22 PM PDT 24 144955591 ps
T1096 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1248509604 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:18 PM PDT 24 17653067 ps
T1097 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1592502512 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:29 PM PDT 24 77777677 ps
T1098 /workspace/coverage/cover_reg_top/41.kmac_intr_test.3909184049 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:52 PM PDT 24 26417051 ps
T104 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2800106434 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:18 PM PDT 24 124182398 ps
T96 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2746027701 Apr 21 12:48:36 PM PDT 24 Apr 21 12:48:38 PM PDT 24 87012903 ps
T1099 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.64498471 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 26555288 ps
T1100 /workspace/coverage/cover_reg_top/49.kmac_intr_test.1937112442 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:28 PM PDT 24 53208848 ps
T1101 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1653914637 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:26 PM PDT 24 122879953 ps
T127 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.413226218 Apr 21 12:48:07 PM PDT 24 Apr 21 12:48:11 PM PDT 24 352345817 ps
T1102 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2579716835 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:38 PM PDT 24 73323993 ps
T177 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.217715223 Apr 21 12:47:58 PM PDT 24 Apr 21 12:48:02 PM PDT 24 721947446 ps
T136 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2014324520 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:18 PM PDT 24 21461042 ps
T1103 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4079727038 Apr 21 12:48:29 PM PDT 24 Apr 21 12:48:32 PM PDT 24 292850963 ps
T137 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2105404769 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 78433085 ps
T99 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.677519306 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:17 PM PDT 24 952583105 ps
T1104 /workspace/coverage/cover_reg_top/1.kmac_intr_test.361928362 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:19 PM PDT 24 120460574 ps
T1105 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2180741382 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:38 PM PDT 24 45075526 ps
T181 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2959912294 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:38 PM PDT 24 107904688 ps
T1106 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.872743649 Apr 21 12:48:29 PM PDT 24 Apr 21 12:48:32 PM PDT 24 62184820 ps
T1107 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1569021493 Apr 21 12:48:22 PM PDT 24 Apr 21 12:48:23 PM PDT 24 35358995 ps
T1108 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2224875818 Apr 21 12:48:19 PM PDT 24 Apr 21 12:48:23 PM PDT 24 380224881 ps
T1109 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1899878962 Apr 21 12:48:23 PM PDT 24 Apr 21 12:48:25 PM PDT 24 52377888 ps
T1110 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2446661481 Apr 21 12:48:23 PM PDT 24 Apr 21 12:48:25 PM PDT 24 60215027 ps
T178 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1559810809 Apr 21 12:48:20 PM PDT 24 Apr 21 12:48:26 PM PDT 24 262615819 ps
T1111 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4216655826 Apr 21 12:47:57 PM PDT 24 Apr 21 12:47:59 PM PDT 24 21972693 ps
T1112 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2900770077 Apr 21 12:48:47 PM PDT 24 Apr 21 12:48:48 PM PDT 24 15687639 ps
T1113 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3987614066 Apr 21 12:48:32 PM PDT 24 Apr 21 12:48:35 PM PDT 24 59290204 ps
T1114 /workspace/coverage/cover_reg_top/44.kmac_intr_test.3419685200 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:29 PM PDT 24 48190126 ps
T1115 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1869060563 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:18 PM PDT 24 129319535 ps
T1116 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2055729261 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:37 PM PDT 24 115594413 ps
T1117 /workspace/coverage/cover_reg_top/12.kmac_intr_test.281418430 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:26 PM PDT 24 71111026 ps
T1118 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2900425621 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:30 PM PDT 24 15216180 ps
T1119 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1914772445 Apr 21 12:48:42 PM PDT 24 Apr 21 12:48:44 PM PDT 24 22340678 ps
T1120 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.185173225 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:17 PM PDT 24 16710336 ps
T1121 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.4175120164 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:16 PM PDT 24 156648256 ps
T1122 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.652052630 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:18 PM PDT 24 46511736 ps
T1123 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3403752583 Apr 21 12:48:11 PM PDT 24 Apr 21 12:48:12 PM PDT 24 31279737 ps
T1124 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3214129219 Apr 21 12:48:46 PM PDT 24 Apr 21 12:48:48 PM PDT 24 397805594 ps
T1125 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1070960022 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:39 PM PDT 24 73775135 ps
T1126 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2121100965 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:37 PM PDT 24 206776822 ps
T1127 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3475408617 Apr 21 12:48:51 PM PDT 24 Apr 21 12:48:54 PM PDT 24 155479013 ps
T1128 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2828793510 Apr 21 12:48:04 PM PDT 24 Apr 21 12:48:15 PM PDT 24 1174761605 ps
T1129 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2117935060 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:13 PM PDT 24 22734680 ps
T103 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4227588205 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:42 PM PDT 24 109747551 ps
T1130 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.985026392 Apr 21 12:48:22 PM PDT 24 Apr 21 12:48:26 PM PDT 24 1190837608 ps
T97 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3315471557 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:42 PM PDT 24 26212149 ps
T1131 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1769183475 Apr 21 12:48:04 PM PDT 24 Apr 21 12:48:05 PM PDT 24 27743952 ps
T105 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1025105809 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:33 PM PDT 24 72600356 ps
T1132 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1673693749 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:17 PM PDT 24 425775106 ps
T1133 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1443491959 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:14 PM PDT 24 87279080 ps
T1134 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1370963071 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:18 PM PDT 24 235738629 ps
T1135 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3218546416 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:22 PM PDT 24 5347892010 ps
T1136 /workspace/coverage/cover_reg_top/32.kmac_intr_test.2710365689 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:29 PM PDT 24 14349885 ps
T1137 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1852948068 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 35101733 ps
T1138 /workspace/coverage/cover_reg_top/3.kmac_intr_test.3548836769 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 42379587 ps
T1139 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3594514183 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:18 PM PDT 24 188677378 ps
T1140 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1824020571 Apr 21 12:48:29 PM PDT 24 Apr 21 12:48:32 PM PDT 24 91564703 ps
T1141 /workspace/coverage/cover_reg_top/7.kmac_intr_test.176344075 Apr 21 12:48:15 PM PDT 24 Apr 21 12:48:17 PM PDT 24 35972221 ps
T1142 /workspace/coverage/cover_reg_top/8.kmac_intr_test.3856955277 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:20 PM PDT 24 19252486 ps
T183 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1986327452 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:32 PM PDT 24 191874262 ps
T1143 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3403819637 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:37 PM PDT 24 83647067 ps
T1144 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2774224384 Apr 21 12:48:08 PM PDT 24 Apr 21 12:48:09 PM PDT 24 59925991 ps
T1145 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2352798856 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 15038125 ps
T1146 /workspace/coverage/cover_reg_top/4.kmac_intr_test.4087627198 Apr 21 12:48:07 PM PDT 24 Apr 21 12:48:09 PM PDT 24 42032418 ps
T1147 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1725415420 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 156066956 ps
T1148 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1615961258 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:13 PM PDT 24 59404351 ps
T100 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2232430441 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:16 PM PDT 24 48241937 ps
T1149 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4227482351 Apr 21 12:48:02 PM PDT 24 Apr 21 12:48:22 PM PDT 24 4044596812 ps
T1150 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3562374907 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:41 PM PDT 24 47674679 ps
T1151 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.372391414 Apr 21 12:48:37 PM PDT 24 Apr 21 12:48:39 PM PDT 24 18452955 ps
T1152 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3540316164 Apr 21 12:48:23 PM PDT 24 Apr 21 12:48:25 PM PDT 24 105706515 ps
T138 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.564113079 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:17 PM PDT 24 17750248 ps
T1153 /workspace/coverage/cover_reg_top/5.kmac_intr_test.239535160 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 40632019 ps
T1154 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2115327031 Apr 21 12:48:16 PM PDT 24 Apr 21 12:48:20 PM PDT 24 392033117 ps
T1155 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3501176806 Apr 21 12:48:08 PM PDT 24 Apr 21 12:48:09 PM PDT 24 20080368 ps
T1156 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.13451909 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:17 PM PDT 24 50467724 ps
T1157 /workspace/coverage/cover_reg_top/37.kmac_intr_test.224431277 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 13626539 ps
T139 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2135783195 Apr 21 12:48:08 PM PDT 24 Apr 21 12:48:10 PM PDT 24 31815640 ps
T1158 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2102190079 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:25 PM PDT 24 18566775 ps
T1159 /workspace/coverage/cover_reg_top/10.kmac_intr_test.420366133 Apr 21 12:48:34 PM PDT 24 Apr 21 12:48:35 PM PDT 24 21476205 ps
T1160 /workspace/coverage/cover_reg_top/2.kmac_intr_test.666450572 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 48076044 ps
T1161 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1653307280 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:27 PM PDT 24 81322591 ps
T1162 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3761769046 Apr 21 12:48:06 PM PDT 24 Apr 21 12:48:09 PM PDT 24 394049063 ps
T1163 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.279023255 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:40 PM PDT 24 138276728 ps
T1164 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4155564201 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:15 PM PDT 24 41127110 ps
T1165 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4280830906 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:27 PM PDT 24 132789830 ps
T1166 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3082756700 Apr 21 12:48:17 PM PDT 24 Apr 21 12:48:20 PM PDT 24 40685106 ps
T1167 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3049158815 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:29 PM PDT 24 146278005 ps
T1168 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3147240978 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:14 PM PDT 24 15744219 ps
T1169 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.12466547 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:29 PM PDT 24 405145388 ps
T1170 /workspace/coverage/cover_reg_top/6.kmac_intr_test.1999321484 Apr 21 12:48:11 PM PDT 24 Apr 21 12:48:12 PM PDT 24 27164257 ps
T1171 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2336534927 Apr 21 12:48:19 PM PDT 24 Apr 21 12:48:20 PM PDT 24 31979346 ps
T1172 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3285245471 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:20 PM PDT 24 19573873 ps
T1173 /workspace/coverage/cover_reg_top/15.kmac_intr_test.3899908416 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:34 PM PDT 24 40572114 ps
T1174 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1526152391 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:35 PM PDT 24 258348059 ps
T1175 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2790855299 Apr 21 12:48:19 PM PDT 24 Apr 21 12:48:21 PM PDT 24 62276264 ps
T98 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3815211420 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:21 PM PDT 24 37839620 ps
T1176 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3551836170 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:46 PM PDT 24 13565735 ps
T1177 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.192763075 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:37 PM PDT 24 32549004 ps
T1178 /workspace/coverage/cover_reg_top/33.kmac_intr_test.1078146134 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:42 PM PDT 24 32525463 ps
T1179 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3813524270 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:30 PM PDT 24 140774726 ps
T1180 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2910115655 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:14 PM PDT 24 943768374 ps
T176 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3156866332 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:27 PM PDT 24 187829328 ps
T1181 /workspace/coverage/cover_reg_top/38.kmac_intr_test.294863245 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:46 PM PDT 24 13763653 ps
T1182 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1564025404 Apr 21 12:48:27 PM PDT 24 Apr 21 12:48:29 PM PDT 24 42539755 ps
T1183 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2394810604 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:29 PM PDT 24 561351970 ps
T1184 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2520227049 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:12 PM PDT 24 21136292 ps
T1185 /workspace/coverage/cover_reg_top/46.kmac_intr_test.1607428215 Apr 21 12:48:33 PM PDT 24 Apr 21 12:48:34 PM PDT 24 12915109 ps
T173 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1998285059 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:16 PM PDT 24 432863289 ps
T1186 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1359780790 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:18 PM PDT 24 46253932 ps
T1187 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3204296690 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:29 PM PDT 24 78200854 ps
T1188 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2265194118 Apr 21 12:48:45 PM PDT 24 Apr 21 12:48:47 PM PDT 24 99017425 ps
T1189 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1042416516 Apr 21 12:48:29 PM PDT 24 Apr 21 12:48:30 PM PDT 24 20936596 ps
T1190 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3009930979 Apr 21 12:48:35 PM PDT 24 Apr 21 12:48:37 PM PDT 24 93811044 ps
T1191 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3470508443 Apr 21 12:48:05 PM PDT 24 Apr 21 12:48:07 PM PDT 24 25463455 ps
T1192 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2864622785 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:14 PM PDT 24 25802650 ps
T101 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.655241785 Apr 21 12:47:56 PM PDT 24 Apr 21 12:47:59 PM PDT 24 24126683 ps
T1193 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1581357 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:29 PM PDT 24 40421367 ps
T1194 /workspace/coverage/cover_reg_top/0.kmac_intr_test.297112163 Apr 21 12:47:59 PM PDT 24 Apr 21 12:48:00 PM PDT 24 22849794 ps
T180 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2722786260 Apr 21 12:48:23 PM PDT 24 Apr 21 12:48:27 PM PDT 24 163630039 ps
T174 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1212320963 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:17 PM PDT 24 204636368 ps
T1195 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3063445426 Apr 21 12:48:19 PM PDT 24 Apr 21 12:48:22 PM PDT 24 109381712 ps
T1196 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.219500278 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:28 PM PDT 24 185036632 ps
T182 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4237241489 Apr 21 12:48:20 PM PDT 24 Apr 21 12:48:22 PM PDT 24 106138504 ps
T1197 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3610621062 Apr 21 12:48:40 PM PDT 24 Apr 21 12:48:42 PM PDT 24 24156415 ps
T175 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3396459392 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:30 PM PDT 24 392334447 ps
T1198 /workspace/coverage/cover_reg_top/13.kmac_intr_test.2020323475 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:25 PM PDT 24 14653612 ps
T1199 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2051391856 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:19 PM PDT 24 72050515 ps
T1200 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.78436262 Apr 21 12:48:39 PM PDT 24 Apr 21 12:48:40 PM PDT 24 84338464 ps
T1201 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1537754130 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:28 PM PDT 24 173036983 ps
T1202 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.495519395 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 25263592 ps
T1203 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2803455596 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:13 PM PDT 24 411878431 ps
T1204 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2639428475 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:40 PM PDT 24 12608785 ps
T1205 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3899416419 Apr 21 12:48:30 PM PDT 24 Apr 21 12:48:33 PM PDT 24 414734229 ps
T1206 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1838027799 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:19 PM PDT 24 310733139 ps
T1207 /workspace/coverage/cover_reg_top/11.kmac_intr_test.1343257628 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:26 PM PDT 24 40190630 ps
T1208 /workspace/coverage/cover_reg_top/18.kmac_intr_test.568231202 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:33 PM PDT 24 19059586 ps
T1209 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2769911959 Apr 21 12:48:26 PM PDT 24 Apr 21 12:48:29 PM PDT 24 160072229 ps
T1210 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2983748466 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:13 PM PDT 24 86401664 ps
T102 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2488229432 Apr 21 12:48:41 PM PDT 24 Apr 21 12:48:42 PM PDT 24 172019968 ps
T1211 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.212440074 Apr 21 12:48:21 PM PDT 24 Apr 21 12:48:22 PM PDT 24 143849947 ps
T1212 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4253150692 Apr 21 12:48:38 PM PDT 24 Apr 21 12:48:39 PM PDT 24 64732057 ps
T1213 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3202427110 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:39 PM PDT 24 579100852 ps
T1214 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1392973018 Apr 21 12:48:43 PM PDT 24 Apr 21 12:48:46 PM PDT 24 126277408 ps
T1215 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2348705729 Apr 21 12:48:49 PM PDT 24 Apr 21 12:48:52 PM PDT 24 44368539 ps
T1216 /workspace/coverage/cover_reg_top/24.kmac_intr_test.4021378147 Apr 21 12:48:44 PM PDT 24 Apr 21 12:48:45 PM PDT 24 30813977 ps
T1217 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2365371313 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:32 PM PDT 24 15291975 ps
T1218 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3961379183 Apr 21 12:48:31 PM PDT 24 Apr 21 12:48:35 PM PDT 24 517942238 ps
T1219 /workspace/coverage/cover_reg_top/21.kmac_intr_test.663146373 Apr 21 12:48:39 PM PDT 24 Apr 21 12:48:40 PM PDT 24 17648030 ps
T179 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1979105988 Apr 21 12:48:30 PM PDT 24 Apr 21 12:48:35 PM PDT 24 273195266 ps
T1220 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3762779413 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:16 PM PDT 24 90522580 ps
T1221 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.786331466 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:32 PM PDT 24 298165849 ps
T1222 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3418382663 Apr 21 12:48:30 PM PDT 24 Apr 21 12:48:32 PM PDT 24 27679707 ps
T1223 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.182417061 Apr 21 12:48:18 PM PDT 24 Apr 21 12:48:19 PM PDT 24 38499760 ps
T1224 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1214733792 Apr 21 12:48:22 PM PDT 24 Apr 21 12:48:25 PM PDT 24 801101397 ps
T1225 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.908801510 Apr 21 12:48:28 PM PDT 24 Apr 21 12:48:31 PM PDT 24 305795954 ps
T1226 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2724426040 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:25 PM PDT 24 398942001 ps
T184 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3304351756 Apr 21 12:48:39 PM PDT 24 Apr 21 12:48:44 PM PDT 24 181167245 ps
T1227 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1052407338 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:12 PM PDT 24 40476044 ps
T1228 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1659480952 Apr 21 12:48:20 PM PDT 24 Apr 21 12:48:23 PM PDT 24 38095312 ps
T1229 /workspace/coverage/cover_reg_top/47.kmac_intr_test.2787860538 Apr 21 12:48:24 PM PDT 24 Apr 21 12:48:26 PM PDT 24 39194915 ps
T1230 /workspace/coverage/cover_reg_top/36.kmac_intr_test.4014403721 Apr 21 12:48:25 PM PDT 24 Apr 21 12:48:27 PM PDT 24 47533155 ps
T140 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4070368583 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:15 PM PDT 24 15568346 ps
T1231 /workspace/coverage/cover_reg_top/17.kmac_intr_test.3266842553 Apr 21 12:48:39 PM PDT 24 Apr 21 12:48:40 PM PDT 24 14056525 ps
T1232 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3692648949 Apr 21 12:48:07 PM PDT 24 Apr 21 12:48:26 PM PDT 24 8017659405 ps
T1233 /workspace/coverage/cover_reg_top/48.kmac_intr_test.2300005461 Apr 21 12:48:34 PM PDT 24 Apr 21 12:48:36 PM PDT 24 16880529 ps
T1234 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.642285139 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:12 PM PDT 24 22655149 ps
T1235 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3121084975 Apr 21 12:48:34 PM PDT 24 Apr 21 12:48:37 PM PDT 24 75034352 ps
T1236 /workspace/coverage/cover_reg_top/29.kmac_intr_test.4292535395 Apr 21 12:48:29 PM PDT 24 Apr 21 12:48:31 PM PDT 24 30566741 ps
T1237 /workspace/coverage/cover_reg_top/30.kmac_intr_test.2744682032 Apr 21 12:48:36 PM PDT 24 Apr 21 12:48:37 PM PDT 24 39086412 ps
T1238 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2452321711 Apr 21 12:48:42 PM PDT 24 Apr 21 12:48:44 PM PDT 24 271138097 ps

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.706943466
Short name T4
Test name
Test status
Simulation time 141022986827 ps
CPU time 2094.92 seconds
Started Apr 21 03:33:32 PM PDT 24
Finished Apr 21 04:08:28 PM PDT 24
Peak memory 440000 kb
Host smart-743066bf-6ea4-4a09-b00d-c98bf93aeac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706943466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.706943466 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.141374841
Short name T91
Test name
Test status
Simulation time 132358017 ps
CPU time 2.8 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 220588 kb
Host smart-18a82f9a-ecf6-44e1-8af3-cf1fda90356f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141374841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_
shadow_reg_errors_with_csr_rw.141374841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.3509963040
Short name T18
Test name
Test status
Simulation time 103253391623 ps
CPU time 112.27 seconds
Started Apr 21 03:37:00 PM PDT 24
Finished Apr 21 03:38:53 PM PDT 24
Peak memory 247992 kb
Host smart-68f59d4e-07d1-432c-9c61-835d2e4bd129
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509963040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.3509963040 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.2540143025
Short name T45
Test name
Test status
Simulation time 90499222 ps
CPU time 1.52 seconds
Started Apr 21 03:55:53 PM PDT 24
Finished Apr 21 03:55:55 PM PDT 24
Peak memory 218408 kb
Host smart-c4416625-ba3c-487d-9f0c-ee1582e4f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540143025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.2540143025 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_error.3763230506
Short name T5
Test name
Test status
Simulation time 4653917821 ps
CPU time 404.94 seconds
Started Apr 21 03:41:19 PM PDT 24
Finished Apr 21 03:48:04 PM PDT 24
Peak memory 259336 kb
Host smart-1b35671e-74b7-455f-a058-c898d50e4455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763230506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.3763230506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.833285304
Short name T50
Test name
Test status
Simulation time 50339776 ps
CPU time 1.74 seconds
Started Apr 21 03:45:04 PM PDT 24
Finished Apr 21 03:45:06 PM PDT 24
Peak memory 218400 kb
Host smart-796b6adc-de7d-445b-b544-fee00a949f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833285304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.833285304 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_key_error.455824174
Short name T17
Test name
Test status
Simulation time 788556646 ps
CPU time 5.33 seconds
Started Apr 21 03:47:16 PM PDT 24
Finished Apr 21 03:47:22 PM PDT 24
Peak memory 218472 kb
Host smart-2f8feea2-4310-4ced-a8c5-724809dc9e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455824174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.455824174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.1922381350
Short name T297
Test name
Test status
Simulation time 3529070375 ps
CPU time 47.27 seconds
Started Apr 21 03:34:37 PM PDT 24
Finished Apr 21 03:35:24 PM PDT 24
Peak memory 220144 kb
Host smart-588ffbb7-99a7-4d89-9f7e-1e49e10d9bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922381350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1922381350 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2379674114
Short name T55
Test name
Test status
Simulation time 31927291 ps
CPU time 1.21 seconds
Started Apr 21 03:42:34 PM PDT 24
Finished Apr 21 03:42:35 PM PDT 24
Peak memory 218480 kb
Host smart-4b4ea75e-921b-48df-b8d7-381e7cbee292
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379674114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2379674114 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1177318738
Short name T1
Test name
Test status
Simulation time 1043192368 ps
CPU time 34.59 seconds
Started Apr 21 03:51:19 PM PDT 24
Finished Apr 21 03:51:54 PM PDT 24
Peak memory 236068 kb
Host smart-c00cd367-5347-4b17-9910-87539374af42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177318738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1177318738 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.661362949
Short name T1091
Test name
Test status
Simulation time 26338760 ps
CPU time 0.8 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 216316 kb
Host smart-3c0d129a-8b8c-426c-8f7c-179d0664e5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661362949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.661362949 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1157047269
Short name T43
Test name
Test status
Simulation time 30924342 ps
CPU time 1.42 seconds
Started Apr 21 03:41:52 PM PDT 24
Finished Apr 21 03:41:53 PM PDT 24
Peak memory 218416 kb
Host smart-767d7abe-e707-4aeb-a932-407e30b6bd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157047269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1157047269 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.125674166
Short name T125
Test name
Test status
Simulation time 380506737 ps
CPU time 4.1 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216600 kb
Host smart-c29d5f2c-a461-4f76-aa84-4636664803a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125674166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.125674
166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.1589757163
Short name T92
Test name
Test status
Simulation time 159273665 ps
CPU time 1.34 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 216372 kb
Host smart-4df460f4-1b9e-4ce5-8404-8c7e02ecd003
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589757163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.1589757163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.2299464013
Short name T63
Test name
Test status
Simulation time 150027204 ps
CPU time 1.35 seconds
Started Apr 21 03:34:29 PM PDT 24
Finished Apr 21 03:34:31 PM PDT 24
Peak memory 222060 kb
Host smart-12f6b444-11cd-4d4f-bc0a-2881f2c49e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2299464013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2299464013 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2685401176
Short name T87
Test name
Test status
Simulation time 797003659942 ps
CPU time 5830.27 seconds
Started Apr 21 03:47:04 PM PDT 24
Finished Apr 21 05:24:15 PM PDT 24
Peak memory 645800 kb
Host smart-13780b32-7c04-4399-974d-5e4bcca4c702
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2685401176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2685401176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1204641903
Short name T21
Test name
Test status
Simulation time 121999195 ps
CPU time 1.44 seconds
Started Apr 21 03:38:58 PM PDT 24
Finished Apr 21 03:39:00 PM PDT 24
Peak memory 218380 kb
Host smart-37cdbeca-4dd0-44e6-bc86-7d6b1c1fb0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204641903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1204641903 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.4070368583
Short name T140
Test name
Test status
Simulation time 15568346 ps
CPU time 1.17 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 216648 kb
Host smart-a7889bb9-78c4-4e3b-ad0b-97dc253004a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070368583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.4070368583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2230223251
Short name T637
Test name
Test status
Simulation time 42910309 ps
CPU time 1.29 seconds
Started Apr 21 03:40:38 PM PDT 24
Finished Apr 21 03:40:40 PM PDT 24
Peak memory 218392 kb
Host smart-a60ed37c-1450-4d00-801a-dbc36f4f7dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230223251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2230223251 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3664108738
Short name T68
Test name
Test status
Simulation time 49031881 ps
CPU time 1.48 seconds
Started Apr 21 03:42:33 PM PDT 24
Finished Apr 21 03:42:35 PM PDT 24
Peak memory 218400 kb
Host smart-e2d7bffb-4509-48b1-9da3-5a163edad1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664108738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3664108738 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.270379270
Short name T47
Test name
Test status
Simulation time 2123965197 ps
CPU time 25.45 seconds
Started Apr 21 03:50:35 PM PDT 24
Finished Apr 21 03:51:00 PM PDT 24
Peak memory 234864 kb
Host smart-0609341a-77ef-443b-bd5b-c3aa72ce54c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270379270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.270379270 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.1229392251
Short name T42
Test name
Test status
Simulation time 76091100 ps
CPU time 1.41 seconds
Started Apr 21 03:54:48 PM PDT 24
Finished Apr 21 03:54:50 PM PDT 24
Peak memory 223896 kb
Host smart-71d58e4f-c129-4811-9ba0-f4d4c819248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229392251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1229392251 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_alert_test.2970127306
Short name T237
Test name
Test status
Simulation time 14668350 ps
CPU time 0.85 seconds
Started Apr 21 03:44:26 PM PDT 24
Finished Apr 21 03:44:27 PM PDT 24
Peak memory 218356 kb
Host smart-b80b39ee-339a-4bfb-992f-9f3d7b445cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970127306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.2970127306 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.1937112442
Short name T1100
Test name
Test status
Simulation time 53208848 ps
CPU time 0.85 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 216412 kb
Host smart-5a90c735-162a-4f1c-886f-192e3d5be71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937112442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.1937112442 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2746027701
Short name T96
Test name
Test status
Simulation time 87012903 ps
CPU time 2.02 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 216892 kb
Host smart-e34131a5-9082-4129-b1c6-a6f929381dfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746027701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2746027701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.1979105988
Short name T179
Test name
Test status
Simulation time 273195266 ps
CPU time 4.81 seconds
Started Apr 21 12:48:30 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 216588 kb
Host smart-3d1e3ac6-7501-4aed-baef-37e8a2cf725e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979105988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.1979
105988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.4016181441
Short name T32
Test name
Test status
Simulation time 13044555289 ps
CPU time 371.12 seconds
Started Apr 21 03:42:27 PM PDT 24
Finished Apr 21 03:48:39 PM PDT 24
Peak memory 251504 kb
Host smart-67c01d27-f627-4a82-a3d6-12f2f0c3a18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016181441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.4016181441 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1168357665
Short name T88
Test name
Test status
Simulation time 13351324883 ps
CPU time 47.66 seconds
Started Apr 21 03:36:18 PM PDT 24
Finished Apr 21 03:37:06 PM PDT 24
Peak memory 256300 kb
Host smart-54fba6e7-27d5-4d9c-b4d0-18ce6a1eb4ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168357665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1168357665 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.4092556946
Short name T530
Test name
Test status
Simulation time 24260931083 ps
CPU time 274.82 seconds
Started Apr 21 03:33:00 PM PDT 24
Finished Apr 21 03:37:35 PM PDT 24
Peak memory 243924 kb
Host smart-34d4fae4-d4e2-4358-99c0-ca0af53c79a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092556946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4092556946 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.4241964579
Short name T95
Test name
Test status
Simulation time 82051830 ps
CPU time 1.18 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 217860 kb
Host smart-65b7c396-66e4-4590-891b-f43a847e7d65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241964579 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg
_errors.4241964579 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.kmac_stress_all.2975867702
Short name T57
Test name
Test status
Simulation time 16473055916 ps
CPU time 1243.07 seconds
Started Apr 21 03:54:46 PM PDT 24
Finished Apr 21 04:15:29 PM PDT 24
Peak memory 333408 kb
Host smart-00918cbf-8628-4ead-830a-37936830c89f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2975867702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.2975867702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.1559810809
Short name T178
Test name
Test status
Simulation time 262615819 ps
CPU time 5.13 seconds
Started Apr 21 12:48:20 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216680 kb
Host smart-3746dfb1-372e-4225-af80-21a9bfcf477d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559810809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.1559
810809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1986327452
Short name T183
Test name
Test status
Simulation time 191874262 ps
CPU time 4.7 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 216608 kb
Host smart-00cfbc6f-3ad2-4fb0-bf43-30535ca660d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986327452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1986
327452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_error.3438097557
Short name T7
Test name
Test status
Simulation time 3498462358 ps
CPU time 273.39 seconds
Started Apr 21 03:33:17 PM PDT 24
Finished Apr 21 03:37:51 PM PDT 24
Peak memory 256476 kb
Host smart-a87ab881-55da-46fb-8dfe-03fab83476cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438097557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3438097557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.891841327
Short name T936
Test name
Test status
Simulation time 1141553456 ps
CPU time 4.07 seconds
Started Apr 21 03:33:08 PM PDT 24
Finished Apr 21 03:33:12 PM PDT 24
Peak memory 218456 kb
Host smart-bdd0b286-c0bf-441f-944a-f05efff9623f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891841327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.891841327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.552558517
Short name T77
Test name
Test status
Simulation time 65186315832 ps
CPU time 578.79 seconds
Started Apr 21 03:50:08 PM PDT 24
Finished Apr 21 03:59:47 PM PDT 24
Peak memory 269096 kb
Host smart-278d4b3b-20e2-4d4c-b917-9b5e136dd94b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552558517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.552558517 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2724426040
Short name T1226
Test name
Test status
Simulation time 398942001 ps
CPU time 9.92 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216564 kb
Host smart-125254c3-c7b3-44c5-9a86-6b6406c3acd7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724426040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2724426
040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2394810604
Short name T1183
Test name
Test status
Simulation time 561351970 ps
CPU time 15.79 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216472 kb
Host smart-d5ac8d94-3df1-458b-8dbe-30b805478959
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394810604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2394810
604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3540316164
Short name T1152
Test name
Test status
Simulation time 105706515 ps
CPU time 1.12 seconds
Started Apr 21 12:48:23 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216540 kb
Host smart-c5aa570d-3594-4647-8495-da311a3650c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540316164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3540316
164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2316590186
Short name T147
Test name
Test status
Simulation time 281953166 ps
CPU time 1.66 seconds
Started Apr 21 12:48:04 PM PDT 24
Finished Apr 21 12:48:06 PM PDT 24
Peak memory 219556 kb
Host smart-5938b31c-f8d0-4016-8726-eec89e9687fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316590186 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2316590186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.2864622785
Short name T1192
Test name
Test status
Simulation time 25802650 ps
CPU time 0.94 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 216368 kb
Host smart-2014253a-7fbe-4b81-ac24-5daa8cd1873c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864622785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.2864622785 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.297112163
Short name T1194
Test name
Test status
Simulation time 22849794 ps
CPU time 0.86 seconds
Started Apr 21 12:47:59 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 216268 kb
Host smart-eb628c3b-99cd-4f25-9833-a41d98b0a199
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297112163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.297112163 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.182417061
Short name T1223
Test name
Test status
Simulation time 38499760 ps
CPU time 0.81 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216400 kb
Host smart-09676481-48ab-4e49-a168-a9d8335d9c95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182417061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.182417061 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3470508443
Short name T1191
Test name
Test status
Simulation time 25463455 ps
CPU time 1.4 seconds
Started Apr 21 12:48:05 PM PDT 24
Finished Apr 21 12:48:07 PM PDT 24
Peak memory 216564 kb
Host smart-1bd07c0f-a51e-4c44-a98b-a2034b2a99f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470508443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3470508443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.655241785
Short name T101
Test name
Test status
Simulation time 24126683 ps
CPU time 1.05 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 216712 kb
Host smart-18e0248e-7ab2-4d4f-abf1-549f24135895
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655241785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_e
rrors.655241785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.2910115655
Short name T1180
Test name
Test status
Simulation time 943768374 ps
CPU time 3.21 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 220140 kb
Host smart-5540c9d1-ecac-4d17-8992-bf31880c650c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910115655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac
_shadow_reg_errors_with_csr_rw.2910115655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.1615961258
Short name T1148
Test name
Test status
Simulation time 59404351 ps
CPU time 1.91 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 216564 kb
Host smart-2e0916c8-efc6-4da7-88d0-28789be86011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615961258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1615961258 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.217715223
Short name T177
Test name
Test status
Simulation time 721947446 ps
CPU time 2.75 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:48:02 PM PDT 24
Peak memory 216544 kb
Host smart-04198ad5-016c-49a8-8fef-bbbf2ac590f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217715223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.217715
223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.933492032
Short name T149
Test name
Test status
Simulation time 337436804 ps
CPU time 5.21 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 216728 kb
Host smart-123efb9d-e32f-4c00-830c-19dea4d170be
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933492032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.93349203
2 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.49308797
Short name T148
Test name
Test status
Simulation time 3349246982 ps
CPU time 22.95 seconds
Started Apr 21 12:48:05 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 216608 kb
Host smart-014f109b-b544-4ae3-b098-058d01e86a1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49308797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.49308797
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.3380292773
Short name T150
Test name
Test status
Simulation time 360564356 ps
CPU time 0.99 seconds
Started Apr 21 12:48:01 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 216372 kb
Host smart-f42194a0-ca10-4f3c-89aa-4d4aebbc09c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380292773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.3380292
773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2803455596
Short name T1203
Test name
Test status
Simulation time 411878431 ps
CPU time 2.5 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 222676 kb
Host smart-c4859829-6c1d-4676-b766-8f46495259f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803455596 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2803455596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.1725415420
Short name T1147
Test name
Test status
Simulation time 156066956 ps
CPU time 1.17 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 216476 kb
Host smart-d8199f41-8d22-42e3-bd02-f6e476576ee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725415420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.1725415420 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.361928362
Short name T1104
Test name
Test status
Simulation time 120460574 ps
CPU time 0.79 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216316 kb
Host smart-45f23631-2eaa-4c0d-afd2-f29c0a8d1ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361928362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.361928362 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.2105404769
Short name T137
Test name
Test status
Simulation time 78433085 ps
CPU time 1.55 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 216536 kb
Host smart-093da144-b329-4177-b3e7-fa91320c9d88
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105404769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.2105404769 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3501176806
Short name T1155
Test name
Test status
Simulation time 20080368 ps
CPU time 0.77 seconds
Started Apr 21 12:48:08 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 216288 kb
Host smart-f2840306-b943-4ea3-a1f4-314499a833e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501176806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3501176806
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1052407338
Short name T1227
Test name
Test status
Simulation time 40476044 ps
CPU time 2.23 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 216600 kb
Host smart-3d9b181b-9614-422c-8f73-ca6a47631f88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052407338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.1052407338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4216655826
Short name T1111
Test name
Test status
Simulation time 21972693 ps
CPU time 1.1 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 216840 kb
Host smart-ce1ae593-2826-4667-9ea5-83d5ec7618cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216655826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.4216655826 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.1769183475
Short name T1131
Test name
Test status
Simulation time 27743952 ps
CPU time 1.46 seconds
Started Apr 21 12:48:04 PM PDT 24
Finished Apr 21 12:48:05 PM PDT 24
Peak memory 216756 kb
Host smart-285d199b-ceae-49b0-b081-f8797c4c8e60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769183475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.1769183475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3220413773
Short name T1090
Test name
Test status
Simulation time 413114866 ps
CPU time 2.7 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216660 kb
Host smart-7219604d-e5f1-4234-a9f3-36f1489a90dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220413773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3220413773 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3761769046
Short name T1162
Test name
Test status
Simulation time 394049063 ps
CPU time 2.97 seconds
Started Apr 21 12:48:06 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 216564 kb
Host smart-209ec6d4-9f9f-4f86-9e3a-9a15b18cd506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761769046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.37617
69046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.908801510
Short name T1225
Test name
Test status
Simulation time 305795954 ps
CPU time 2.52 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:31 PM PDT 24
Peak memory 221820 kb
Host smart-fadfe367-d6ba-4bb1-aa2e-dbc3c7e32e3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908801510 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.908801510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1248509604
Short name T1096
Test name
Test status
Simulation time 17653067 ps
CPU time 1.09 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216540 kb
Host smart-41d8e9c9-00f6-4e48-bb9c-413345e14b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248509604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1248509604 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.420366133
Short name T1159
Test name
Test status
Simulation time 21476205 ps
CPU time 0.81 seconds
Started Apr 21 12:48:34 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 216352 kb
Host smart-34742d88-20e2-4a16-a048-b9bec778cfdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420366133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.420366133 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2579716835
Short name T1102
Test name
Test status
Simulation time 73323993 ps
CPU time 2.23 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 215612 kb
Host smart-5d3d42d9-0e7b-4f25-9677-ebd733e7cbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579716835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.2579716835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3315471557
Short name T97
Test name
Test status
Simulation time 26212149 ps
CPU time 1.07 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 216652 kb
Host smart-5d5140bd-33e0-45d1-964e-a9e03b908b43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315471557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3315471557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.3815211420
Short name T98
Test name
Test status
Simulation time 37839620 ps
CPU time 1.87 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:21 PM PDT 24
Peak memory 219272 kb
Host smart-67568394-7a17-415e-a636-1c78b20aa8c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815211420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.3815211420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3063445426
Short name T1195
Test name
Test status
Simulation time 109381712 ps
CPU time 2.78 seconds
Started Apr 21 12:48:19 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 216624 kb
Host smart-876dbedf-dcf2-407a-a0da-ed49d41a8e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063445426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3063445426 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2722786260
Short name T180
Test name
Test status
Simulation time 163630039 ps
CPU time 2.96 seconds
Started Apr 21 12:48:23 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216628 kb
Host smart-425a5263-c4d4-400f-a4e8-1ccd0602ead6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722786260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2722
786260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.3529628581
Short name T1092
Test name
Test status
Simulation time 72848880 ps
CPU time 2.67 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 221980 kb
Host smart-6f15b5a7-de56-4eb7-bf5e-e491a49e7d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529628581 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.3529628581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.2365371313
Short name T1217
Test name
Test status
Simulation time 15291975 ps
CPU time 0.9 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 216352 kb
Host smart-425d6e75-292b-4684-af2c-90777a2acc7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365371313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2365371313 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1343257628
Short name T1207
Test name
Test status
Simulation time 40190630 ps
CPU time 0.79 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216284 kb
Host smart-5d521f00-3e68-4bce-a222-228fc2088628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343257628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1343257628 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1550780405
Short name T1083
Test name
Test status
Simulation time 50220790 ps
CPU time 1.43 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 216552 kb
Host smart-8f0a7e2d-83ba-4834-891c-691aef5156f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550780405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1550780405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2051391856
Short name T1199
Test name
Test status
Simulation time 72050515 ps
CPU time 0.94 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216448 kb
Host smart-4bb9345d-7eec-4cf0-94dc-71000ddbe657
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051391856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2051391856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.4280830906
Short name T1165
Test name
Test status
Simulation time 132789830 ps
CPU time 1.87 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 220320 kb
Host smart-379a006c-f879-46b3-93a1-e3a594c83efd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280830906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.4280830906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.3987614066
Short name T1113
Test name
Test status
Simulation time 59290204 ps
CPU time 1.96 seconds
Started Apr 21 12:48:32 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 216636 kb
Host smart-7838dbb9-0aea-49eb-8f1a-e4070ee6b72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987614066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.3987614066 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.1537754130
Short name T1201
Test name
Test status
Simulation time 173036983 ps
CPU time 1.61 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 218672 kb
Host smart-f033b7ab-4a8e-4e8e-9928-06a767ac1ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537754130 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.1537754130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2769085927
Short name T185
Test name
Test status
Simulation time 165367230 ps
CPU time 1.13 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216460 kb
Host smart-edb1b820-7b11-4d44-a95d-55f3c6aabc7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769085927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2769085927 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.281418430
Short name T1117
Test name
Test status
Simulation time 71111026 ps
CPU time 0.85 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216396 kb
Host smart-d129a580-1483-43b1-94c5-d15bd1c0961c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281418430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.281418430 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.1659480952
Short name T1228
Test name
Test status
Simulation time 38095312 ps
CPU time 2.14 seconds
Started Apr 21 12:48:20 PM PDT 24
Finished Apr 21 12:48:23 PM PDT 24
Peak memory 216616 kb
Host smart-d05c515d-2c75-46b5-aa35-1e291fc62a00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659480952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.1659480952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.4079727038
Short name T1103
Test name
Test status
Simulation time 292850963 ps
CPU time 2.05 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 220256 kb
Host smart-1d8fbcaf-ff12-496a-a126-52d905cbe60f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079727038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.4079727038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.985026392
Short name T1130
Test name
Test status
Simulation time 1190837608 ps
CPU time 3.76 seconds
Started Apr 21 12:48:22 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216676 kb
Host smart-0fa0adfe-36d8-41ce-a4e6-683e2aaf04b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985026392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.985026392 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2224875818
Short name T1108
Test name
Test status
Simulation time 380224881 ps
CPU time 3.03 seconds
Started Apr 21 12:48:19 PM PDT 24
Finished Apr 21 12:48:23 PM PDT 24
Peak memory 216544 kb
Host smart-06edebf3-02c5-47cc-9abd-5c8525aca153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224875818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2224
875818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.3418382663
Short name T1222
Test name
Test status
Simulation time 27679707 ps
CPU time 1.56 seconds
Started Apr 21 12:48:30 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 218440 kb
Host smart-e658345a-0540-45e0-8f14-c8f48779396c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418382663 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.3418382663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.1569021493
Short name T1107
Test name
Test status
Simulation time 35358995 ps
CPU time 1.23 seconds
Started Apr 21 12:48:22 PM PDT 24
Finished Apr 21 12:48:23 PM PDT 24
Peak memory 216544 kb
Host smart-cf52c676-e5b5-4b85-8b68-53e54282fe34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569021493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.1569021493 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.2020323475
Short name T1198
Test name
Test status
Simulation time 14653612 ps
CPU time 0.78 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216316 kb
Host smart-a51774ea-5f1e-4ae2-add7-c84e13f7668e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020323475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.2020323475 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.2055729261
Short name T1116
Test name
Test status
Simulation time 115594413 ps
CPU time 1.67 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216628 kb
Host smart-dfcfcbe5-a338-4ce5-921d-47aa40ca1ab5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055729261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.2055729261 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.212440074
Short name T1211
Test name
Test status
Simulation time 143849947 ps
CPU time 1.1 seconds
Started Apr 21 12:48:21 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 216952 kb
Host smart-9f09ce2d-78da-427e-9932-c86ce2b76a78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212440074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_
errors.212440074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.898658212
Short name T93
Test name
Test status
Simulation time 336977285 ps
CPU time 3.1 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 219976 kb
Host smart-a52d66b2-a4e8-4d9f-9c9b-a42d075c9233
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898658212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac
_shadow_reg_errors_with_csr_rw.898658212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.290132332
Short name T1087
Test name
Test status
Simulation time 22308230 ps
CPU time 1.47 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 216692 kb
Host smart-e3ed9f6b-be5b-4a4b-b4c6-8269eb8f1d05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290132332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.290132332 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3961379183
Short name T1218
Test name
Test status
Simulation time 517942238 ps
CPU time 3.21 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 216548 kb
Host smart-41f8adcb-ff9a-4134-a64f-d7bea7388c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961379183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3961
379183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1653914637
Short name T1101
Test name
Test status
Simulation time 122879953 ps
CPU time 1.78 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 217836 kb
Host smart-7097dacb-a457-45c7-a891-ec386e1867c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653914637 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1653914637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2102190079
Short name T1158
Test name
Test status
Simulation time 18566775 ps
CPU time 1.03 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216368 kb
Host smart-3927fe5e-8873-422f-be9f-2a8d5aae5df4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102190079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2102190079 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1824020571
Short name T1140
Test name
Test status
Simulation time 91564703 ps
CPU time 2.4 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 216488 kb
Host smart-24bff346-7acf-49bc-8e51-412a2e2e19a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824020571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1824020571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2261193146
Short name T89
Test name
Test status
Simulation time 29350055 ps
CPU time 1.31 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 217924 kb
Host smart-842b5f79-4d0e-49fe-b77e-00f8deb608c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261193146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2261193146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.4227588205
Short name T103
Test name
Test status
Simulation time 109747551 ps
CPU time 2.93 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 220636 kb
Host smart-207d8f1b-aceb-428a-9c25-aed43c7347a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227588205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.4227588205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3562374907
Short name T1150
Test name
Test status
Simulation time 47674679 ps
CPU time 2.54 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:41 PM PDT 24
Peak memory 216596 kb
Host smart-66846c84-38f5-4346-8baa-e41dc59267d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562374907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3562374907 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.872743649
Short name T1106
Test name
Test status
Simulation time 62184820 ps
CPU time 2.15 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 221608 kb
Host smart-b2f677a5-af27-4662-91d9-0b248a2ecfba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872743649 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.872743649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.1070960022
Short name T1125
Test name
Test status
Simulation time 73775135 ps
CPU time 1.05 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 216416 kb
Host smart-7455ce61-1376-4c10-9e14-e9ce8ef97d75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070960022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.1070960022 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3899908416
Short name T1173
Test name
Test status
Simulation time 40572114 ps
CPU time 0.85 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:34 PM PDT 24
Peak memory 216320 kb
Host smart-8f8908f4-2b88-4b58-8c56-e6a22dea5337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899908416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3899908416 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3899416419
Short name T1205
Test name
Test status
Simulation time 414734229 ps
CPU time 2.72 seconds
Started Apr 21 12:48:30 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 216548 kb
Host smart-487bc77e-ee68-464f-b341-658a0aa7cf8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899416419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.3899416419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.582147396
Short name T1088
Test name
Test status
Simulation time 399199174 ps
CPU time 1 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216612 kb
Host smart-7f0c69f6-559f-41b4-9ad1-e9b921095446
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582147396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_
errors.582147396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2121100965
Short name T1126
Test name
Test status
Simulation time 206776822 ps
CPU time 1.65 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216524 kb
Host smart-a026e688-4052-4ef1-9f1d-f32618fec730
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121100965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2121100965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.3813524270
Short name T1179
Test name
Test status
Simulation time 140774726 ps
CPU time 3.86 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 216700 kb
Host smart-2de6fc4a-0262-43cc-983a-11aa8d9bad44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813524270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3813524270 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.3396459392
Short name T175
Test name
Test status
Simulation time 392334447 ps
CPU time 5.14 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 216608 kb
Host smart-0f8572b6-ba90-4bdb-a4ca-5b1059c5ae23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396459392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.3396
459392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2180741382
Short name T1105
Test name
Test status
Simulation time 45075526 ps
CPU time 1.63 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 217600 kb
Host smart-6d15f6ad-109c-4644-87af-c2f168648a87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180741382 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2180741382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.78436262
Short name T1200
Test name
Test status
Simulation time 84338464 ps
CPU time 0.98 seconds
Started Apr 21 12:48:39 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 216316 kb
Host smart-a4698711-5092-42f9-af16-64abeaab1774
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78436262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.78436262 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2578927889
Short name T128
Test name
Test status
Simulation time 40641221 ps
CPU time 0.79 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216360 kb
Host smart-2ef6f147-a6f4-4805-a218-5926d1c39066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578927889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2578927889 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3121084975
Short name T1235
Test name
Test status
Simulation time 75034352 ps
CPU time 2.18 seconds
Started Apr 21 12:48:34 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216596 kb
Host smart-77446c9b-b637-4310-862e-73aaa5e60557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121084975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3121084975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.4253150692
Short name T1212
Test name
Test status
Simulation time 64732057 ps
CPU time 1.07 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 216700 kb
Host smart-bb0ed855-1013-4ab3-b136-e05a8595fff1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253150692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.4253150692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1392973018
Short name T1214
Test name
Test status
Simulation time 126277408 ps
CPU time 1.75 seconds
Started Apr 21 12:48:43 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 219296 kb
Host smart-7ba4a9f5-bf83-4525-858a-accee10febd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392973018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1392973018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.3475408617
Short name T1127
Test name
Test status
Simulation time 155479013 ps
CPU time 1.99 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:54 PM PDT 24
Peak memory 216644 kb
Host smart-8deb618e-f094-4e64-9039-f786945f0a46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475408617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3475408617 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.786331466
Short name T1221
Test name
Test status
Simulation time 298165849 ps
CPU time 5.24 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:32 PM PDT 24
Peak memory 216560 kb
Host smart-fd948eb5-e7e1-433f-b76c-e8feee9733fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786331466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.78633
1466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.279023255
Short name T1163
Test name
Test status
Simulation time 138276728 ps
CPU time 2.08 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 222128 kb
Host smart-745bbdba-2840-4bee-9712-5d41ef5ddc72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279023255 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.279023255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.372391414
Short name T1151
Test name
Test status
Simulation time 18452955 ps
CPU time 1.12 seconds
Started Apr 21 12:48:37 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 216540 kb
Host smart-88435892-86c8-40bc-94b9-89f33d04423a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372391414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.372391414 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.3266842553
Short name T1231
Test name
Test status
Simulation time 14056525 ps
CPU time 0.78 seconds
Started Apr 21 12:48:39 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 216348 kb
Host smart-29fbdef4-4b1b-443f-b6e2-1194253202d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266842553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.3266842553 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2452321711
Short name T1238
Test name
Test status
Simulation time 271138097 ps
CPU time 1.75 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 216568 kb
Host smart-ed7ea97d-2a49-4e70-9e96-bd6146370dac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452321711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.2452321711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.2488229432
Short name T102
Test name
Test status
Simulation time 172019968 ps
CPU time 1.14 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 216880 kb
Host smart-5049d032-0e23-4229-85dd-a9fbdaddb70a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488229432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.2488229432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.1079482075
Short name T1084
Test name
Test status
Simulation time 397702782 ps
CPU time 1.56 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 216596 kb
Host smart-fdd08d1a-7427-41a9-95af-7b7977d78886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079482075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1079482075 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.2959912294
Short name T181
Test name
Test status
Simulation time 107904688 ps
CPU time 2.41 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:38 PM PDT 24
Peak memory 216560 kb
Host smart-ce7c77c9-4712-4a70-a782-2e6553e5dbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959912294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.2959
912294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.3214129219
Short name T1124
Test name
Test status
Simulation time 397805594 ps
CPU time 1.67 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 218180 kb
Host smart-d90b0d2a-4066-42cf-a54b-a5d0748e8a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214129219 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.3214129219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1914772445
Short name T1119
Test name
Test status
Simulation time 22340678 ps
CPU time 0.94 seconds
Started Apr 21 12:48:42 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 216320 kb
Host smart-35e58faa-5df4-4ab1-8b76-a8d58925343d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914772445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1914772445 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.568231202
Short name T1208
Test name
Test status
Simulation time 19059586 ps
CPU time 0.83 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 216248 kb
Host smart-57120dc6-2113-4715-a805-3ababaaa5850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568231202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.568231202 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.1581357
Short name T1193
Test name
Test status
Simulation time 40421367 ps
CPU time 2.49 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216588 kb
Host smart-fea3bf02-62b1-4e3f-bf45-ad5b2d15812e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_csr_o
utstanding.1581357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.1564025404
Short name T1182
Test name
Test status
Simulation time 42539755 ps
CPU time 1.17 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216456 kb
Host smart-ab015c64-4df6-48ef-9233-9f202af39a77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564025404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.1564025404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.2416794233
Short name T90
Test name
Test status
Simulation time 198320072 ps
CPU time 2.67 seconds
Started Apr 21 12:48:53 PM PDT 24
Finished Apr 21 12:48:56 PM PDT 24
Peak memory 218880 kb
Host smart-2560c9ec-52c0-4dd2-91d1-82c05cfc55b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416794233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.2416794233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.3204296690
Short name T1187
Test name
Test status
Simulation time 78200854 ps
CPU time 2.59 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216700 kb
Host smart-098fe4ce-a3ec-4599-8eda-dca5cea0f98f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204296690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.3204296690 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3304351756
Short name T184
Test name
Test status
Simulation time 181167245 ps
CPU time 4.14 seconds
Started Apr 21 12:48:39 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 216560 kb
Host smart-6a1494d8-2f50-4223-b1c6-522853dd4ada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304351756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3304
351756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.3403819637
Short name T1143
Test name
Test status
Simulation time 83647067 ps
CPU time 1.7 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 217724 kb
Host smart-d1063f07-6413-425e-8eda-49dec7b00c31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403819637 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.3403819637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.2265194118
Short name T1188
Test name
Test status
Simulation time 99017425 ps
CPU time 1.2 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 216540 kb
Host smart-8101820b-50c3-4b38-82a7-69357d72e216
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265194118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.2265194118 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.816756311
Short name T1094
Test name
Test status
Simulation time 17625239 ps
CPU time 0.8 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:43 PM PDT 24
Peak memory 216208 kb
Host smart-f171f8b6-631e-43c3-b3de-eab968d2944d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816756311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.816756311 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.219500278
Short name T1196
Test name
Test status
Simulation time 185036632 ps
CPU time 2.69 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:28 PM PDT 24
Peak memory 216588 kb
Host smart-12795982-4680-419f-93b3-7325bac62907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219500278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.219500278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.192763075
Short name T1177
Test name
Test status
Simulation time 32549004 ps
CPU time 1.03 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216748 kb
Host smart-f0e87e00-c128-4caa-9338-0a2771dc735c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192763075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_
errors.192763075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1526152391
Short name T1174
Test name
Test status
Simulation time 258348059 ps
CPU time 1.63 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:35 PM PDT 24
Peak memory 219100 kb
Host smart-87122f05-a7bf-4d3f-8d92-b6b58464e81a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526152391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.1526152391 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2348705729
Short name T1215
Test name
Test status
Simulation time 44368539 ps
CPU time 2.72 seconds
Started Apr 21 12:48:49 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 216636 kb
Host smart-485916a0-2bb4-4b78-bcd9-f5f8e86e059f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348705729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2348705729 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2828793510
Short name T1128
Test name
Test status
Simulation time 1174761605 ps
CPU time 10.08 seconds
Started Apr 21 12:48:04 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 216732 kb
Host smart-798f28b1-1f7b-4023-86da-603ea2fde0fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828793510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2828793
510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.4227482351
Short name T1149
Test name
Test status
Simulation time 4044596812 ps
CPU time 19.12 seconds
Started Apr 21 12:48:02 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 216576 kb
Host smart-a61d2d04-f57e-4de0-b1ac-811af4836451
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227482351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.4227482
351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.642285139
Short name T1234
Test name
Test status
Simulation time 22655149 ps
CPU time 0.98 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 216360 kb
Host smart-26593bf0-fffb-40ed-b3c3-da2e75814b99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642285139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.64228513
9 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.3762779413
Short name T1220
Test name
Test status
Simulation time 90522580 ps
CPU time 1.74 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 217944 kb
Host smart-c6afc163-29f1-4a56-b5b0-8d969bdee91e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762779413 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3762779413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1620887734
Short name T1093
Test name
Test status
Simulation time 67747209 ps
CPU time 0.97 seconds
Started Apr 21 12:48:00 PM PDT 24
Finished Apr 21 12:48:02 PM PDT 24
Peak memory 216328 kb
Host smart-09be00eb-ad0f-499e-9333-ba76e90f6e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620887734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1620887734 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.666450572
Short name T1160
Test name
Test status
Simulation time 48076044 ps
CPU time 0.81 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216312 kb
Host smart-140b477b-278a-492c-ab53-17d95df64bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666450572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.666450572 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.564113079
Short name T138
Test name
Test status
Simulation time 17750248 ps
CPU time 1.37 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216604 kb
Host smart-c55f0ca6-84d5-4375-9968-12faa7103062
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564113079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.564113079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.3285245471
Short name T1172
Test name
Test status
Simulation time 19573873 ps
CPU time 0.78 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 216348 kb
Host smart-d130f4e9-3544-4e9d-a8e6-2372d1f4f4b0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285245471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.3285245471
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2236800445
Short name T146
Test name
Test status
Simulation time 757544572 ps
CPU time 2.69 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 216592 kb
Host smart-5819915f-d430-4153-a990-bc5992affecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236800445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2236800445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.3946088016
Short name T94
Test name
Test status
Simulation time 69296377 ps
CPU time 1.51 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 217984 kb
Host smart-c397bb50-2c25-4cfb-a57b-fde8e43ed71f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946088016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.3946088016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.2800106434
Short name T104
Test name
Test status
Simulation time 124182398 ps
CPU time 2.83 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 220312 kb
Host smart-1c9f0a5d-47f8-4d4b-9ec4-230de19e6a01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800106434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.2800106434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1370963071
Short name T1134
Test name
Test status
Simulation time 235738629 ps
CPU time 3.12 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216620 kb
Host smart-e6d5024e-7b40-430e-8d58-f8f2da0ba8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370963071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1370963071 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3386350395
Short name T126
Test name
Test status
Simulation time 334925360 ps
CPU time 2.66 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216640 kb
Host smart-126eec93-5f71-4be2-a7cd-6833ef207146
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386350395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.33863
50395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3551836170
Short name T1176
Test name
Test status
Simulation time 13565735 ps
CPU time 0.78 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 216284 kb
Host smart-82d609b4-70aa-413e-a0c9-16d8fcb01561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551836170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3551836170 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.663146373
Short name T1219
Test name
Test status
Simulation time 17648030 ps
CPU time 0.8 seconds
Started Apr 21 12:48:39 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 216348 kb
Host smart-625f9e69-32f9-4df0-9080-af5f624e432f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663146373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.663146373 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.3952543176
Short name T169
Test name
Test status
Simulation time 13309266 ps
CPU time 0.82 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:47 PM PDT 24
Peak memory 216352 kb
Host smart-8faae744-7ee5-4deb-b844-73605b979967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952543176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3952543176 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.1786798591
Short name T170
Test name
Test status
Simulation time 20726597 ps
CPU time 0.83 seconds
Started Apr 21 12:48:43 PM PDT 24
Finished Apr 21 12:48:44 PM PDT 24
Peak memory 216272 kb
Host smart-e93eb83c-8f28-4d00-88a4-12ddf57c8e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786798591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1786798591 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.4021378147
Short name T1216
Test name
Test status
Simulation time 30813977 ps
CPU time 0.76 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 216356 kb
Host smart-002256b1-aac1-46a5-b8f4-90ba23765811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021378147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.4021378147 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2900770077
Short name T1112
Test name
Test status
Simulation time 15687639 ps
CPU time 0.81 seconds
Started Apr 21 12:48:47 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 216360 kb
Host smart-65b11bc3-1465-41b0-897e-23421a64dd57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900770077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2900770077 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2352798856
Short name T1145
Test name
Test status
Simulation time 15038125 ps
CPU time 0.79 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 216288 kb
Host smart-cd1da39a-770d-4ad4-bdea-bcd044023b36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352798856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2352798856 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2900425621
Short name T1118
Test name
Test status
Simulation time 15216180 ps
CPU time 0.86 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 216368 kb
Host smart-904e1628-872b-42a7-8134-bf8682a94d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900425621 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2900425621 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1804685533
Short name T171
Test name
Test status
Simulation time 44377336 ps
CPU time 0.76 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:34 PM PDT 24
Peak memory 216212 kb
Host smart-eeee6951-720d-42ed-aca6-66ba73b47e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804685533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1804685533 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.4292535395
Short name T1236
Test name
Test status
Simulation time 30566741 ps
CPU time 0.76 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:31 PM PDT 24
Peak memory 216348 kb
Host smart-30028804-6420-4a52-8f5d-bafec5f98d20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292535395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.4292535395 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3218546416
Short name T1135
Test name
Test status
Simulation time 5347892010 ps
CPU time 11.07 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 216536 kb
Host smart-1ee150a6-a364-4fb9-a0fe-78386b5cefc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218546416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3218546
416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.3692648949
Short name T1232
Test name
Test status
Simulation time 8017659405 ps
CPU time 18.87 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216608 kb
Host smart-3236ea31-beb0-4c83-b973-5735555bb60b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692648949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.3692648
949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1852948068
Short name T1137
Test name
Test status
Simulation time 35101733 ps
CPU time 1.11 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 216496 kb
Host smart-32796427-afa1-420b-8e40-51bd6d54ec57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852948068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1852948
068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.765938110
Short name T163
Test name
Test status
Simulation time 286871128 ps
CPU time 1.68 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 217868 kb
Host smart-1b315fa9-50c6-43b3-961e-aa77fc329066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765938110 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.765938110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.2520227049
Short name T1184
Test name
Test status
Simulation time 21136292 ps
CPU time 0.98 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 216408 kb
Host smart-9742312c-f24d-49e0-a6c0-d23da27cd63c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520227049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.2520227049 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.3548836769
Short name T1138
Test name
Test status
Simulation time 42379587 ps
CPU time 0.82 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 216280 kb
Host smart-f38c3bdd-aa07-409d-92cc-65c8031c7dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548836769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.3548836769 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2014324520
Short name T136
Test name
Test status
Simulation time 21461042 ps
CPU time 1.08 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216612 kb
Host smart-d60ee871-fb4b-440e-8363-3c0df2ac3c56
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014324520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2014324520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.495519395
Short name T1202
Test name
Test status
Simulation time 25263592 ps
CPU time 0.76 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216284 kb
Host smart-d32b08fe-7088-418c-88cb-fa1b00d27c4f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495519395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.495519395 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1214733792
Short name T1224
Test name
Test status
Simulation time 801101397 ps
CPU time 1.81 seconds
Started Apr 21 12:48:22 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216600 kb
Host smart-1fd33074-84ff-45e6-a123-7a29ae4a4af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214733792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1214733792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.2117935060
Short name T1129
Test name
Test status
Simulation time 22734680 ps
CPU time 0.99 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 216300 kb
Host smart-6604db1e-83f2-4b74-b76d-41ff1d9cdab1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117935060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.2117935060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.2983748466
Short name T1210
Test name
Test status
Simulation time 86401664 ps
CPU time 2.4 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 220596 kb
Host smart-ed6972a3-ad62-44a4-8a8b-2546311624ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983748466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.2983748466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.2115327031
Short name T1154
Test name
Test status
Simulation time 392033117 ps
CPU time 2.9 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 216636 kb
Host smart-18de872b-7771-4598-add2-a8192355a11d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115327031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.2115327031 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1212320963
Short name T174
Test name
Test status
Simulation time 204636368 ps
CPU time 3.92 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216624 kb
Host smart-f13f7b11-450a-4788-9858-ba4d7dbab4a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212320963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.12123
20963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.2744682032
Short name T1237
Test name
Test status
Simulation time 39086412 ps
CPU time 0.79 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216280 kb
Host smart-3702c8bf-fcd2-4f93-b290-c11564e5d399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744682032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.2744682032 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1042416516
Short name T1189
Test name
Test status
Simulation time 20936596 ps
CPU time 0.77 seconds
Started Apr 21 12:48:29 PM PDT 24
Finished Apr 21 12:48:30 PM PDT 24
Peak memory 216352 kb
Host smart-2077ca67-2abe-4e45-af69-b2cf0bc62d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042416516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1042416516 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.2710365689
Short name T1136
Test name
Test status
Simulation time 14349885 ps
CPU time 0.78 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216348 kb
Host smart-2f359d9c-0c72-4be8-b7ce-8a16466d7813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710365689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2710365689 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.1078146134
Short name T1178
Test name
Test status
Simulation time 32525463 ps
CPU time 0.8 seconds
Started Apr 21 12:48:41 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 216268 kb
Host smart-8dd4a70a-375f-46f9-889b-f1a7b5784a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078146134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1078146134 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.817180661
Short name T162
Test name
Test status
Simulation time 14865942 ps
CPU time 0.82 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:36 PM PDT 24
Peak memory 216236 kb
Host smart-46fb4463-0fb0-43ce-8d61-1e223e71e19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817180661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.817180661 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3610621062
Short name T1197
Test name
Test status
Simulation time 24156415 ps
CPU time 0.76 seconds
Started Apr 21 12:48:40 PM PDT 24
Finished Apr 21 12:48:42 PM PDT 24
Peak memory 216336 kb
Host smart-92b341c1-eedd-4f38-abc1-4f081a3ac777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610621062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3610621062 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.4014403721
Short name T1230
Test name
Test status
Simulation time 47533155 ps
CPU time 0.78 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216316 kb
Host smart-11d81082-ab74-4337-bf7b-de9545634d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014403721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.4014403721 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.224431277
Short name T1157
Test name
Test status
Simulation time 13626539 ps
CPU time 0.85 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:45 PM PDT 24
Peak memory 216340 kb
Host smart-16b685bc-acf1-4260-b75b-25e5a7478119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224431277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.224431277 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.294863245
Short name T1181
Test name
Test status
Simulation time 13763653 ps
CPU time 0.8 seconds
Started Apr 21 12:48:44 PM PDT 24
Finished Apr 21 12:48:46 PM PDT 24
Peak memory 216312 kb
Host smart-2e4c30c0-3ea9-43f0-94a3-f40a613f111b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294863245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.294863245 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3108177913
Short name T129
Test name
Test status
Simulation time 46231062 ps
CPU time 0.78 seconds
Started Apr 21 12:48:46 PM PDT 24
Finished Apr 21 12:48:48 PM PDT 24
Peak memory 216356 kb
Host smart-bc78b47f-bcfc-4982-89ea-25c7bb6b933e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108177913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3108177913 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1838027799
Short name T1206
Test name
Test status
Simulation time 310733139 ps
CPU time 4.52 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216480 kb
Host smart-5cc3c01c-6fa2-424a-8e05-3c066913ce42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838027799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1838027
799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.3202427110
Short name T1213
Test name
Test status
Simulation time 579100852 ps
CPU time 7.96 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:39 PM PDT 24
Peak memory 216536 kb
Host smart-cef3aeb2-c3c6-44c6-b498-e12aa82d6d5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202427110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.3202427
110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.3878696548
Short name T1089
Test name
Test status
Simulation time 42943793 ps
CPU time 0.95 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216340 kb
Host smart-597857a3-5dc1-4ce1-a8e0-bb7df1fb07a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878696548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.3878696
548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.1592502512
Short name T1097
Test name
Test status
Simulation time 77777677 ps
CPU time 2.35 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 222536 kb
Host smart-92da79f9-b2ca-4376-a739-042de9f36bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592502512 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.1592502512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.4155564201
Short name T1164
Test name
Test status
Simulation time 41127110 ps
CPU time 1.02 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 216296 kb
Host smart-a83367fa-c00a-4441-8ef4-dadf76561802
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155564201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.4155564201 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.4087627198
Short name T1146
Test name
Test status
Simulation time 42032418 ps
CPU time 0.8 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 216248 kb
Host smart-9e3c3f7a-6a01-4cfa-a2fd-5849211de590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087627198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.4087627198 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2135783195
Short name T139
Test name
Test status
Simulation time 31815640 ps
CPU time 1.2 seconds
Started Apr 21 12:48:08 PM PDT 24
Finished Apr 21 12:48:10 PM PDT 24
Peak memory 216504 kb
Host smart-509233e2-a329-4ea7-b264-fafd63349967
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135783195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2135783195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.3403752583
Short name T1123
Test name
Test status
Simulation time 31279737 ps
CPU time 0.77 seconds
Started Apr 21 12:48:11 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 216272 kb
Host smart-14bbc050-41a3-4bf9-a414-4dbb328889d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403752583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3403752583
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.3497815473
Short name T1086
Test name
Test status
Simulation time 77634732 ps
CPU time 1.42 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216592 kb
Host smart-c70bf440-286e-421f-8bda-dac9e40c1789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497815473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.3497815473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2774224384
Short name T1144
Test name
Test status
Simulation time 59925991 ps
CPU time 0.94 seconds
Started Apr 21 12:48:08 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 216492 kb
Host smart-8fb9145d-b631-4ead-a5cc-e4bf2b9604f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774224384 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.2774224384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.250519690
Short name T164
Test name
Test status
Simulation time 1116903353 ps
CPU time 3.29 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 216660 kb
Host smart-952003ee-65b4-4307-9060-5855ffced6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250519690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.250519690 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.413226218
Short name T127
Test name
Test status
Simulation time 352345817 ps
CPU time 3.87 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 216660 kb
Host smart-271f74b6-dc2c-4b63-8c29-85ede082d07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413226218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.413226
218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2639428475
Short name T1204
Test name
Test status
Simulation time 12608785 ps
CPU time 0.77 seconds
Started Apr 21 12:48:38 PM PDT 24
Finished Apr 21 12:48:40 PM PDT 24
Peak memory 216372 kb
Host smart-0951cfd6-b0de-4b40-a1cc-43a51fdc2f9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639428475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2639428475 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.3909184049
Short name T1098
Test name
Test status
Simulation time 26417051 ps
CPU time 0.81 seconds
Started Apr 21 12:48:45 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 216276 kb
Host smart-69d038a9-ee82-4c60-86dd-26b84b916f9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909184049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.3909184049 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.1421480376
Short name T167
Test name
Test status
Simulation time 58846267 ps
CPU time 0.81 seconds
Started Apr 21 12:48:36 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 216288 kb
Host smart-644cf752-266f-4693-ba60-340010b96f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421480376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.1421480376 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.2495810380
Short name T168
Test name
Test status
Simulation time 21232768 ps
CPU time 0.78 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216352 kb
Host smart-903a3215-5e50-4ef1-b71f-71cd8f83e76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495810380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.2495810380 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.3419685200
Short name T1114
Test name
Test status
Simulation time 48190126 ps
CPU time 0.78 seconds
Started Apr 21 12:48:28 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216380 kb
Host smart-44475a9a-9dd3-46eb-9d9d-8342cbe363f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419685200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.3419685200 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2457071723
Short name T161
Test name
Test status
Simulation time 17010229 ps
CPU time 0.8 seconds
Started Apr 21 12:48:51 PM PDT 24
Finished Apr 21 12:48:52 PM PDT 24
Peak memory 216276 kb
Host smart-d8bc7888-b3a3-4099-86c0-1dd855fddb41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457071723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2457071723 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.1607428215
Short name T1185
Test name
Test status
Simulation time 12915109 ps
CPU time 0.83 seconds
Started Apr 21 12:48:33 PM PDT 24
Finished Apr 21 12:48:34 PM PDT 24
Peak memory 216280 kb
Host smart-4708b236-8dd5-4886-b1b3-087382f4ee65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607428215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.1607428215 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.2787860538
Short name T1229
Test name
Test status
Simulation time 39194915 ps
CPU time 0.75 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:26 PM PDT 24
Peak memory 216384 kb
Host smart-77757b7d-2d9c-4d60-9c2d-2675885e984d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787860538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.2787860538 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.2300005461
Short name T1233
Test name
Test status
Simulation time 16880529 ps
CPU time 0.8 seconds
Started Apr 21 12:48:34 PM PDT 24
Finished Apr 21 12:48:36 PM PDT 24
Peak memory 216360 kb
Host smart-0ae4fdd2-f0aa-4fc4-a7d4-96836aa0f20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300005461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2300005461 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.1852281253
Short name T186
Test name
Test status
Simulation time 24728467 ps
CPU time 1.48 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 220048 kb
Host smart-ddbb5a42-b759-45dd-86f8-5375818afaa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852281253 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.1852281253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.3147240978
Short name T1168
Test name
Test status
Simulation time 15744219 ps
CPU time 0.93 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 215744 kb
Host smart-fcae8a60-a0e5-46fa-8391-730d093666c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147240978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3147240978 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.239535160
Short name T1153
Test name
Test status
Simulation time 40632019 ps
CPU time 0.76 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216372 kb
Host smart-d47e680a-cb17-48aa-8215-d584c0a13d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239535160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.239535160 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.4175120164
Short name T1121
Test name
Test status
Simulation time 156648256 ps
CPU time 2.18 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216332 kb
Host smart-9cba1c66-94b4-4106-9071-53de049613e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175120164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.4175120164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.678881050
Short name T107
Test name
Test status
Simulation time 346578615 ps
CPU time 1.46 seconds
Started Apr 21 12:48:11 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 217092 kb
Host smart-959850fb-b395-4ea5-8ffc-0d02c714b9b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678881050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_e
rrors.678881050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.1025105809
Short name T105
Test name
Test status
Simulation time 72600356 ps
CPU time 1.86 seconds
Started Apr 21 12:48:31 PM PDT 24
Finished Apr 21 12:48:33 PM PDT 24
Peak memory 216952 kb
Host smart-e07ce4df-a160-47e0-9d43-739e66a09486
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025105809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.1025105809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.1359780790
Short name T1186
Test name
Test status
Simulation time 46253932 ps
CPU time 2.74 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216632 kb
Host smart-82190c9e-87cd-4159-97c1-1541fb36a862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359780790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.1359780790 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1673693749
Short name T1132
Test name
Test status
Simulation time 425775106 ps
CPU time 2.79 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216212 kb
Host smart-7e4fae6c-156c-41b8-8f3e-e601674bf7de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673693749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.16736
93749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.1111953556
Short name T1095
Test name
Test status
Simulation time 144955591 ps
CPU time 1.59 seconds
Started Apr 21 12:48:20 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 217668 kb
Host smart-4cd2d7b3-4030-4b5d-a5bf-8362433b65fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111953556 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.1111953556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.64498471
Short name T1099
Test name
Test status
Simulation time 26555288 ps
CPU time 1.14 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216564 kb
Host smart-501cbbeb-70dd-460a-be61-89e753d3a187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64498471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.64498471 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.1999321484
Short name T1170
Test name
Test status
Simulation time 27164257 ps
CPU time 0.81 seconds
Started Apr 21 12:48:11 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 216332 kb
Host smart-75a894c6-1f86-4b31-b08b-dbc7279afd75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999321484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.1999321484 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1869060563
Short name T1115
Test name
Test status
Simulation time 129319535 ps
CPU time 2.07 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216528 kb
Host smart-e0cbd54e-c5e5-4838-bbb2-a5d556baac31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869060563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1869060563 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1844576563
Short name T106
Test name
Test status
Simulation time 120197220 ps
CPU time 1.93 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 216668 kb
Host smart-4b1f85ae-4f30-4a94-b9c7-2d71d84653fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844576563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1844576563 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.652052630
Short name T1122
Test name
Test status
Simulation time 46511736 ps
CPU time 2.79 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216656 kb
Host smart-f97d5c9f-d5c3-48d3-9030-591947eb29e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652052630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.652052630 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3082756700
Short name T1166
Test name
Test status
Simulation time 40685106 ps
CPU time 1.52 seconds
Started Apr 21 12:48:17 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 218028 kb
Host smart-276f8d17-d443-4239-9d08-471e9cd9ab48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082756700 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3082756700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.185173225
Short name T1120
Test name
Test status
Simulation time 16710336 ps
CPU time 1.07 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216468 kb
Host smart-413d7ee6-2e4a-406f-9894-0c403f9ff215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185173225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.185173225 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.176344075
Short name T1141
Test name
Test status
Simulation time 35972221 ps
CPU time 0.79 seconds
Started Apr 21 12:48:15 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216352 kb
Host smart-8c731fce-34c7-4657-9f47-11a2c6dd0d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176344075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.176344075 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2446661481
Short name T1110
Test name
Test status
Simulation time 60215027 ps
CPU time 1.58 seconds
Started Apr 21 12:48:23 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 216592 kb
Host smart-cbf65b5b-ca3e-4233-a7d5-15a33420d3af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446661481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2446661481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1443491959
Short name T1133
Test name
Test status
Simulation time 87279080 ps
CPU time 1.15 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 216868 kb
Host smart-a81d8c59-e445-42e8-a8de-5dcff70d1a1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443491959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1443491959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3009930979
Short name T1190
Test name
Test status
Simulation time 93811044 ps
CPU time 1.61 seconds
Started Apr 21 12:48:35 PM PDT 24
Finished Apr 21 12:48:37 PM PDT 24
Peak memory 215548 kb
Host smart-db83dd98-b807-4542-8a1a-9851853c7e4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009930979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3009930979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2557528369
Short name T1085
Test name
Test status
Simulation time 79246757 ps
CPU time 2.64 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216552 kb
Host smart-53ea8eb3-a0a2-45e0-939a-a909290fc1c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557528369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2557528369 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.1998285059
Short name T173
Test name
Test status
Simulation time 432863289 ps
CPU time 2.47 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 216604 kb
Host smart-26a3ff4f-f8cf-4a33-a15e-96a697b74511
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998285059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.19982
85059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1899878962
Short name T1109
Test name
Test status
Simulation time 52377888 ps
CPU time 1.75 seconds
Started Apr 21 12:48:23 PM PDT 24
Finished Apr 21 12:48:25 PM PDT 24
Peak memory 221128 kb
Host smart-2dd4f7a5-2096-48ee-9446-3e6b76b0babd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899878962 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1899878962 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.2336534927
Short name T1171
Test name
Test status
Simulation time 31979346 ps
CPU time 1.21 seconds
Started Apr 21 12:48:19 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 216428 kb
Host smart-f9705083-70d7-4f5f-8f3e-b10ad9e73581
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336534927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.2336534927 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.3856955277
Short name T1142
Test name
Test status
Simulation time 19252486 ps
CPU time 0.78 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 216376 kb
Host smart-df69208a-919a-4b8b-9f08-f818e59d369e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856955277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.3856955277 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3594514183
Short name T1139
Test name
Test status
Simulation time 188677378 ps
CPU time 1.56 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216528 kb
Host smart-9abd9fa6-57fb-4b50-aa60-0e406a245007
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594514183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.3594514183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2232430441
Short name T100
Test name
Test status
Simulation time 48241937 ps
CPU time 1.36 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 217952 kb
Host smart-98b44296-0146-4328-b70b-f6c10133f2e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232430441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.2232430441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.13451909
Short name T1156
Test name
Test status
Simulation time 50467724 ps
CPU time 1.63 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 216584 kb
Host smart-3bccc0b9-2103-47ad-bf34-b7fea9287bb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13451909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_s
hadow_reg_errors_with_csr_rw.13451909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.2769911959
Short name T1209
Test name
Test status
Simulation time 160072229 ps
CPU time 2.18 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216640 kb
Host smart-d3eff34d-71e3-4c8a-80dc-1c1403fc7980
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769911959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.2769911959 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3156866332
Short name T176
Test name
Test status
Simulation time 187829328 ps
CPU time 2.33 seconds
Started Apr 21 12:48:24 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216604 kb
Host smart-9dd6c888-4e94-4409-8dd6-60b0e1faee6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156866332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.31568
66332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.3049158815
Short name T1167
Test name
Test status
Simulation time 146278005 ps
CPU time 1.82 seconds
Started Apr 21 12:48:27 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 220684 kb
Host smart-1df5bd12-8e4a-498f-a37b-e3d384b4ff86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049158815 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.3049158815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2585527690
Short name T160
Test name
Test status
Simulation time 56335682 ps
CPU time 1.2 seconds
Started Apr 21 12:48:16 PM PDT 24
Finished Apr 21 12:48:18 PM PDT 24
Peak memory 216516 kb
Host smart-785730c1-cc4d-49ff-947a-7c881438f5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585527690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2585527690 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.728255909
Short name T130
Test name
Test status
Simulation time 22519858 ps
CPU time 0.78 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216328 kb
Host smart-f98f1c00-5709-49d8-abd7-805eb137f226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728255909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.728255909 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.2790855299
Short name T1175
Test name
Test status
Simulation time 62276264 ps
CPU time 1.63 seconds
Started Apr 21 12:48:19 PM PDT 24
Finished Apr 21 12:48:21 PM PDT 24
Peak memory 216604 kb
Host smart-1f8235a3-3fef-4d3a-b528-2d9da2523135
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790855299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.2790855299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1653307280
Short name T1161
Test name
Test status
Simulation time 81322591 ps
CPU time 1.18 seconds
Started Apr 21 12:48:25 PM PDT 24
Finished Apr 21 12:48:27 PM PDT 24
Peak memory 216860 kb
Host smart-aa2aa20e-af7d-4976-a17e-7b7c56a5429b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653307280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1653307280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.677519306
Short name T99
Test name
Test status
Simulation time 952583105 ps
CPU time 2.75 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:17 PM PDT 24
Peak memory 220296 kb
Host smart-f4959f2b-5711-431d-b1f2-daf2b2778b6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677519306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_
shadow_reg_errors_with_csr_rw.677519306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.12466547
Short name T1169
Test name
Test status
Simulation time 405145388 ps
CPU time 2.13 seconds
Started Apr 21 12:48:26 PM PDT 24
Finished Apr 21 12:48:29 PM PDT 24
Peak memory 216708 kb
Host smart-117a05d9-932b-4753-939d-6bc9bf7f3578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12466547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.12466547 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.4237241489
Short name T182
Test name
Test status
Simulation time 106138504 ps
CPU time 2.32 seconds
Started Apr 21 12:48:20 PM PDT 24
Finished Apr 21 12:48:22 PM PDT 24
Peak memory 216664 kb
Host smart-8394b406-5da1-46a7-811e-285b5774944d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237241489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.42372
41489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.2831672978
Short name T604
Test name
Test status
Simulation time 29102733 ps
CPU time 0.79 seconds
Started Apr 21 03:33:34 PM PDT 24
Finished Apr 21 03:33:35 PM PDT 24
Peak memory 218340 kb
Host smart-fb67a511-2de5-4142-8154-68d5fe38ac86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831672978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.2831672978 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.3493570342
Short name T725
Test name
Test status
Simulation time 7314182211 ps
CPU time 173.33 seconds
Started Apr 21 03:33:05 PM PDT 24
Finished Apr 21 03:35:59 PM PDT 24
Peak memory 240156 kb
Host smart-6e0bf0c1-01de-4aa4-bc31-0187897f88ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493570342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3493570342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.789908830
Short name T228
Test name
Test status
Simulation time 11517271501 ps
CPU time 301.82 seconds
Started Apr 21 03:33:15 PM PDT 24
Finished Apr 21 03:38:18 PM PDT 24
Peak memory 249072 kb
Host smart-489a0412-099f-4049-83e1-c27dec4cb3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789908830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.789908830 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1338837532
Short name T587
Test name
Test status
Simulation time 9919646289 ps
CPU time 238.35 seconds
Started Apr 21 03:32:47 PM PDT 24
Finished Apr 21 03:36:46 PM PDT 24
Peak memory 229752 kb
Host smart-0a7e422c-082f-4ac0-bd86-de3ffe1eeb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338837532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1338837532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.16167699
Short name T1035
Test name
Test status
Simulation time 400271349 ps
CPU time 2.77 seconds
Started Apr 21 03:33:10 PM PDT 24
Finished Apr 21 03:33:13 PM PDT 24
Peak memory 226508 kb
Host smart-7a4509cd-4829-4aba-ac78-7a7a1c56290f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=16167699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.16167699 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.2319973942
Short name T909
Test name
Test status
Simulation time 356912678 ps
CPU time 1.19 seconds
Started Apr 21 03:33:10 PM PDT 24
Finished Apr 21 03:33:12 PM PDT 24
Peak memory 220696 kb
Host smart-7a0e13b3-bd65-4759-a8b7-930b16757361
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2319973942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2319973942 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.3123523707
Short name T22
Test name
Test status
Simulation time 5741862146 ps
CPU time 53.45 seconds
Started Apr 21 03:33:20 PM PDT 24
Finished Apr 21 03:34:14 PM PDT 24
Peak memory 220324 kb
Host smart-50148dd3-7364-4bf8-a75c-271b523c955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123523707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3123523707 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2702459959
Short name T46
Test name
Test status
Simulation time 117496798 ps
CPU time 1.53 seconds
Started Apr 21 03:33:25 PM PDT 24
Finished Apr 21 03:33:27 PM PDT 24
Peak memory 219368 kb
Host smart-88df1b92-3f2a-4f38-abdf-4f898a9c183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702459959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2702459959 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.1199756414
Short name T1040
Test name
Test status
Simulation time 105711991040 ps
CPU time 1307.98 seconds
Started Apr 21 03:32:47 PM PDT 24
Finished Apr 21 03:54:36 PM PDT 24
Peak memory 325860 kb
Host smart-fb66950f-96cd-4b4a-8181-6483831bb907
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199756414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.1199756414 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.198130900
Short name T890
Test name
Test status
Simulation time 64362887682 ps
CPU time 385.95 seconds
Started Apr 21 03:33:05 PM PDT 24
Finished Apr 21 03:39:32 PM PDT 24
Peak memory 251636 kb
Host smart-94252d23-87c6-4024-bd0d-ce7aa506d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198130900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.198130900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.2824166584
Short name T19
Test name
Test status
Simulation time 18661464743 ps
CPU time 88.76 seconds
Started Apr 21 03:33:35 PM PDT 24
Finished Apr 21 03:35:04 PM PDT 24
Peak memory 270536 kb
Host smart-3c197a30-565c-4d5f-b3b9-e662c9dfe94c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824166584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.2824166584 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.3489375664
Short name T644
Test name
Test status
Simulation time 14571551531 ps
CPU time 334.8 seconds
Started Apr 21 03:32:44 PM PDT 24
Finished Apr 21 03:38:19 PM PDT 24
Peak memory 247812 kb
Host smart-4dc3ea42-d497-409b-90fc-dc7cebf5082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489375664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3489375664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2041305354
Short name T540
Test name
Test status
Simulation time 10350704965 ps
CPU time 59.8 seconds
Started Apr 21 03:32:41 PM PDT 24
Finished Apr 21 03:33:41 PM PDT 24
Peak memory 226612 kb
Host smart-cdc17136-dfc3-49cf-86b1-eb5be584bfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041305354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2041305354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.3267045432
Short name T790
Test name
Test status
Simulation time 88459643427 ps
CPU time 1552.1 seconds
Started Apr 21 03:34:45 PM PDT 24
Finished Apr 21 04:00:39 PM PDT 24
Peak memory 377372 kb
Host smart-9e5ef578-c123-46fd-8446-eba60178e5ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3267045432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.3267045432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2591092884
Short name T558
Test name
Test status
Simulation time 980497000 ps
CPU time 6.15 seconds
Started Apr 21 03:32:58 PM PDT 24
Finished Apr 21 03:33:04 PM PDT 24
Peak memory 218552 kb
Host smart-d64d2aed-ffec-4593-8eba-5e1a7470484b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591092884 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2591092884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.2223270198
Short name T324
Test name
Test status
Simulation time 778799678 ps
CPU time 6.54 seconds
Started Apr 21 03:33:16 PM PDT 24
Finished Apr 21 03:33:23 PM PDT 24
Peak memory 226648 kb
Host smart-df1eaf48-dbce-45c2-af78-4cd44b1f6e3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223270198 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.2223270198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.2934134104
Short name T466
Test name
Test status
Simulation time 85667368971 ps
CPU time 2370.27 seconds
Started Apr 21 03:32:46 PM PDT 24
Finished Apr 21 04:12:16 PM PDT 24
Peak memory 383124 kb
Host smart-e5c01228-7e41-4500-9bb9-8259ec101c56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2934134104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2934134104 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.1972800828
Short name T799
Test name
Test status
Simulation time 105458273767 ps
CPU time 2180.98 seconds
Started Apr 21 03:32:47 PM PDT 24
Finished Apr 21 04:09:08 PM PDT 24
Peak memory 383160 kb
Host smart-9227c816-ab8f-4621-baee-2fcd81ff9933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1972800828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1972800828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.533179971
Short name T259
Test name
Test status
Simulation time 65133094391 ps
CPU time 1695.36 seconds
Started Apr 21 03:32:55 PM PDT 24
Finished Apr 21 04:01:11 PM PDT 24
Peak memory 341872 kb
Host smart-c1f4ee41-4acb-4662-b84a-be69aa34e0c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=533179971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.533179971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.426618832
Short name T406
Test name
Test status
Simulation time 21467763391 ps
CPU time 1224.43 seconds
Started Apr 21 03:32:58 PM PDT 24
Finished Apr 21 03:53:22 PM PDT 24
Peak memory 304004 kb
Host smart-a268a1e4-fcca-4344-8964-9a4b12e98743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=426618832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.426618832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.1198029495
Short name T208
Test name
Test status
Simulation time 270899509994 ps
CPU time 4762.3 seconds
Started Apr 21 03:33:11 PM PDT 24
Finished Apr 21 04:52:35 PM PDT 24
Peak memory 647312 kb
Host smart-71bdb5d2-c594-46e1-970a-0d6dfcb19a1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1198029495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1198029495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.4258413818
Short name T505
Test name
Test status
Simulation time 315861786214 ps
CPU time 5073.7 seconds
Started Apr 21 03:33:09 PM PDT 24
Finished Apr 21 04:57:44 PM PDT 24
Peak memory 564136 kb
Host smart-f4cb66fd-b281-4321-a7c9-72c8e11193ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4258413818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.4258413818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.948110119
Short name T652
Test name
Test status
Simulation time 15573041 ps
CPU time 0.86 seconds
Started Apr 21 03:34:46 PM PDT 24
Finished Apr 21 03:34:47 PM PDT 24
Peak memory 218344 kb
Host smart-4ebf9f81-ad70-47a1-ba89-7bce6971e83c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948110119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.948110119 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.3209171187
Short name T818
Test name
Test status
Simulation time 19401302589 ps
CPU time 313.19 seconds
Started Apr 21 03:33:58 PM PDT 24
Finished Apr 21 03:39:11 PM PDT 24
Peak memory 248000 kb
Host smart-e1a35431-4db4-4c94-af01-0d80ebbd7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209171187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3209171187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1039173276
Short name T964
Test name
Test status
Simulation time 10185911979 ps
CPU time 47.47 seconds
Started Apr 21 03:34:02 PM PDT 24
Finished Apr 21 03:34:50 PM PDT 24
Peak memory 226888 kb
Host smart-5ce97091-7031-49c9-b6a2-a393e5aca005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039173276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1039173276 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1814849352
Short name T835
Test name
Test status
Simulation time 24837260010 ps
CPU time 1124.92 seconds
Started Apr 21 03:33:38 PM PDT 24
Finished Apr 21 03:52:23 PM PDT 24
Peak memory 243116 kb
Host smart-22864e28-6483-4362-bb86-51b71f343208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814849352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1814849352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.2949464905
Short name T962
Test name
Test status
Simulation time 224299077 ps
CPU time 1.27 seconds
Started Apr 21 03:34:42 PM PDT 24
Finished Apr 21 03:34:43 PM PDT 24
Peak memory 218380 kb
Host smart-93d50f88-3100-4ba6-8dc5-046b871598c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949464905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2949464905 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.1611416509
Short name T834
Test name
Test status
Simulation time 1922109484 ps
CPU time 74.21 seconds
Started Apr 21 03:34:12 PM PDT 24
Finished Apr 21 03:35:27 PM PDT 24
Peak memory 240284 kb
Host smart-6286456f-1565-453b-89c0-f8b435bb51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611416509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.1611416509 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.3215298007
Short name T343
Test name
Test status
Simulation time 4036445285 ps
CPU time 288.16 seconds
Started Apr 21 03:34:15 PM PDT 24
Finished Apr 21 03:39:03 PM PDT 24
Peak memory 258332 kb
Host smart-15e8931d-260c-4486-85cb-aafa6d2ba0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215298007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3215298007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.3051962551
Short name T426
Test name
Test status
Simulation time 865015153 ps
CPU time 5.03 seconds
Started Apr 21 03:34:22 PM PDT 24
Finished Apr 21 03:34:27 PM PDT 24
Peak memory 218392 kb
Host smart-67962651-189c-4dd6-9ce9-05f66270523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051962551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.3051962551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.2533276771
Short name T1045
Test name
Test status
Simulation time 101830362 ps
CPU time 1.35 seconds
Started Apr 21 03:34:37 PM PDT 24
Finished Apr 21 03:34:39 PM PDT 24
Peak memory 218428 kb
Host smart-8a7ec575-85b4-44bf-a630-b4ae7915dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533276771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2533276771 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.4063397365
Short name T973
Test name
Test status
Simulation time 43059493245 ps
CPU time 639.19 seconds
Started Apr 21 03:33:43 PM PDT 24
Finished Apr 21 03:44:23 PM PDT 24
Peak memory 270324 kb
Host smart-f61f316c-7cb8-4aa7-a4b5-df86f95ba809
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063397365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.4063397365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.1156371259
Short name T960
Test name
Test status
Simulation time 24922951889 ps
CPU time 405.11 seconds
Started Apr 21 03:34:10 PM PDT 24
Finished Apr 21 03:40:55 PM PDT 24
Peak memory 252652 kb
Host smart-e93750d7-d2e7-41b7-b326-1c23236f0c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156371259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.1156371259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.1740266571
Short name T116
Test name
Test status
Simulation time 13501267545 ps
CPU time 85.9 seconds
Started Apr 21 03:34:46 PM PDT 24
Finished Apr 21 03:36:12 PM PDT 24
Peak memory 274288 kb
Host smart-65d219fd-3a14-4e37-a6e6-5b8c70587479
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740266571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.1740266571 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.3691031581
Short name T942
Test name
Test status
Simulation time 36494394109 ps
CPU time 373.76 seconds
Started Apr 21 03:33:40 PM PDT 24
Finished Apr 21 03:39:54 PM PDT 24
Peak memory 244668 kb
Host smart-d888af06-cac1-4646-b801-12d29ea9ac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691031581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.3691031581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2108297501
Short name T408
Test name
Test status
Simulation time 7753382221 ps
CPU time 75.07 seconds
Started Apr 21 03:33:40 PM PDT 24
Finished Apr 21 03:34:56 PM PDT 24
Peak memory 226680 kb
Host smart-4dfcf60a-cb2f-4cf7-9be3-afd6e63abce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108297501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2108297501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2479562771
Short name T435
Test name
Test status
Simulation time 30714032557 ps
CPU time 372.01 seconds
Started Apr 21 03:34:37 PM PDT 24
Finished Apr 21 03:40:49 PM PDT 24
Peak memory 239988 kb
Host smart-154c7271-435c-4a3d-b295-ced9992027da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2479562771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2479562771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.3761235112
Short name T1004
Test name
Test status
Simulation time 798097269 ps
CPU time 7.16 seconds
Started Apr 21 03:33:58 PM PDT 24
Finished Apr 21 03:34:05 PM PDT 24
Peak memory 226576 kb
Host smart-33beb627-1b3b-4cee-a46e-d06970780538
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761235112 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.3761235112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2681747485
Short name T983
Test name
Test status
Simulation time 3365218150 ps
CPU time 6.46 seconds
Started Apr 21 03:33:56 PM PDT 24
Finished Apr 21 03:34:03 PM PDT 24
Peak memory 226696 kb
Host smart-ac4a8f16-f9c4-44c5-9f9e-905b49d2d374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681747485 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2681747485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.960813644
Short name T356
Test name
Test status
Simulation time 135721073864 ps
CPU time 2542.09 seconds
Started Apr 21 03:33:40 PM PDT 24
Finished Apr 21 04:16:03 PM PDT 24
Peak memory 396072 kb
Host smart-60de9fa7-f2f0-485c-b79f-e6964628605f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=960813644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.960813644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.43652469
Short name T708
Test name
Test status
Simulation time 99392367503 ps
CPU time 2095.8 seconds
Started Apr 21 03:33:41 PM PDT 24
Finished Apr 21 04:08:38 PM PDT 24
Peak memory 379168 kb
Host smart-7d2a5044-2f70-4737-9fa4-e12de4b77bc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=43652469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.43652469 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.3468987378
Short name T808
Test name
Test status
Simulation time 311911454919 ps
CPU time 1988.41 seconds
Started Apr 21 03:34:15 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 333780 kb
Host smart-5bdee0c4-dafd-4d8e-9435-427eeeb3da2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3468987378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.3468987378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1830139865
Short name T207
Test name
Test status
Simulation time 20810027551 ps
CPU time 1305.05 seconds
Started Apr 21 03:33:44 PM PDT 24
Finished Apr 21 03:55:30 PM PDT 24
Peak memory 298932 kb
Host smart-33f4e822-5e8b-4bb6-9249-8ec8bbd9c480
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830139865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1830139865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1972877005
Short name T852
Test name
Test status
Simulation time 179336524003 ps
CPU time 5783.42 seconds
Started Apr 21 03:33:45 PM PDT 24
Finished Apr 21 05:10:09 PM PDT 24
Peak memory 642748 kb
Host smart-f46b2da3-bcc8-49b9-bb85-275d99a3d7cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1972877005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1972877005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3305509839
Short name T941
Test name
Test status
Simulation time 183849844482 ps
CPU time 4984.97 seconds
Started Apr 21 03:33:55 PM PDT 24
Finished Apr 21 04:57:01 PM PDT 24
Peak memory 582860 kb
Host smart-df990125-120a-446c-8b73-c0b2cf2867ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3305509839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3305509839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3261631633
Short name T536
Test name
Test status
Simulation time 79311080 ps
CPU time 0.78 seconds
Started Apr 21 03:40:41 PM PDT 24
Finished Apr 21 03:40:42 PM PDT 24
Peak memory 218324 kb
Host smart-d3ea2b5c-7bc4-450d-b1c5-a887939c67c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261631633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3261631633 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.3716574039
Short name T755
Test name
Test status
Simulation time 2342272107 ps
CPU time 51.88 seconds
Started Apr 21 03:40:35 PM PDT 24
Finished Apr 21 03:41:27 PM PDT 24
Peak memory 227348 kb
Host smart-d3e644f4-b65d-4db1-aade-809755f27b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716574039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3716574039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.87937067
Short name T584
Test name
Test status
Simulation time 19643140539 ps
CPU time 893.99 seconds
Started Apr 21 03:40:27 PM PDT 24
Finished Apr 21 03:55:21 PM PDT 24
Peak memory 236260 kb
Host smart-7ee8cd7d-f9f2-416d-b52c-630e167d3fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87937067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.87937067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.2871118013
Short name T1019
Test name
Test status
Simulation time 227827968 ps
CPU time 2.99 seconds
Started Apr 21 03:40:44 PM PDT 24
Finished Apr 21 03:40:47 PM PDT 24
Peak memory 221312 kb
Host smart-b93d853b-47bd-449d-b364-961807611e66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2871118013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2871118013 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.2949414132
Short name T707
Test name
Test status
Simulation time 27389925 ps
CPU time 0.88 seconds
Started Apr 21 03:40:38 PM PDT 24
Finished Apr 21 03:40:39 PM PDT 24
Peak memory 220440 kb
Host smart-1aa34418-0982-4648-9b28-c2159763eda3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949414132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2949414132 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.3631463656
Short name T567
Test name
Test status
Simulation time 22201673299 ps
CPU time 121.95 seconds
Started Apr 21 03:40:35 PM PDT 24
Finished Apr 21 03:42:38 PM PDT 24
Peak memory 234020 kb
Host smart-9a0f43f8-0ce2-451d-af97-a6a85b81bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631463656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.3631463656 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.3873099454
Short name T303
Test name
Test status
Simulation time 56406145026 ps
CPU time 415.81 seconds
Started Apr 21 03:40:36 PM PDT 24
Finished Apr 21 03:47:32 PM PDT 24
Peak memory 259400 kb
Host smart-575a6751-611d-46d7-9cf2-1a3d97af2d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873099454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.3873099454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.774900235
Short name T944
Test name
Test status
Simulation time 1464225104 ps
CPU time 2.73 seconds
Started Apr 21 03:40:35 PM PDT 24
Finished Apr 21 03:40:38 PM PDT 24
Peak memory 218488 kb
Host smart-e9cd1d83-df7a-4f9d-905d-199a02286255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774900235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.774900235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.3175324087
Short name T663
Test name
Test status
Simulation time 123766287588 ps
CPU time 2527.35 seconds
Started Apr 21 03:40:21 PM PDT 24
Finished Apr 21 04:22:29 PM PDT 24
Peak memory 427768 kb
Host smart-451aa44a-0c49-400b-b79f-d6e42750e111
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175324087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.3175324087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.1388900260
Short name T722
Test name
Test status
Simulation time 93789282082 ps
CPU time 324.22 seconds
Started Apr 21 03:40:26 PM PDT 24
Finished Apr 21 03:45:50 PM PDT 24
Peak memory 247548 kb
Host smart-7ed9eddb-2dbd-4d85-b09c-f87de1fd1384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388900260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.1388900260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.2180461822
Short name T741
Test name
Test status
Simulation time 1785383124 ps
CPU time 70.43 seconds
Started Apr 21 03:40:19 PM PDT 24
Finished Apr 21 03:41:29 PM PDT 24
Peak memory 226612 kb
Host smart-d9c7ca51-ed3e-41c5-bddd-8e8a21e86180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180461822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.2180461822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.244215052
Short name T308
Test name
Test status
Simulation time 3634612603 ps
CPU time 51.72 seconds
Started Apr 21 03:40:40 PM PDT 24
Finished Apr 21 03:41:31 PM PDT 24
Peak memory 229384 kb
Host smart-93ed7e01-090f-44f2-b774-685ad2b7479c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=244215052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.244215052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_stress_all_with_rand_reset.392792065
Short name T76
Test name
Test status
Simulation time 18843906693 ps
CPU time 1486.34 seconds
Started Apr 21 03:40:41 PM PDT 24
Finished Apr 21 04:05:27 PM PDT 24
Peak memory 335208 kb
Host smart-6da0668a-d7c7-4e79-8567-a7cf76733451
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392792065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all_with_rand_reset.392792065 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.1621603886
Short name T810
Test name
Test status
Simulation time 1330522357 ps
CPU time 6.32 seconds
Started Apr 21 03:40:34 PM PDT 24
Finished Apr 21 03:40:40 PM PDT 24
Peak memory 226616 kb
Host smart-06fc0821-d789-42f5-b961-563f4d390ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621603886 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.1621603886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.366260695
Short name T837
Test name
Test status
Simulation time 254276045 ps
CPU time 6.46 seconds
Started Apr 21 03:40:34 PM PDT 24
Finished Apr 21 03:40:41 PM PDT 24
Peak memory 226612 kb
Host smart-438f6e3f-b508-492b-a048-d3c2734e2812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366260695 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.kmac_test_vectors_kmac_xof.366260695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.1327823458
Short name T886
Test name
Test status
Simulation time 197798610916 ps
CPU time 2460.68 seconds
Started Apr 21 03:40:29 PM PDT 24
Finished Apr 21 04:21:30 PM PDT 24
Peak memory 382412 kb
Host smart-27ef8cda-0cda-44b5-ae60-2303e65859a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1327823458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.1327823458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.1450139748
Short name T606
Test name
Test status
Simulation time 23291360518 ps
CPU time 1948.48 seconds
Started Apr 21 03:40:32 PM PDT 24
Finished Apr 21 04:13:01 PM PDT 24
Peak memory 382516 kb
Host smart-337acf29-0f39-4847-b981-1b5dc9bd27b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1450139748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1450139748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2798355507
Short name T379
Test name
Test status
Simulation time 142943971869 ps
CPU time 1700.04 seconds
Started Apr 21 03:40:31 PM PDT 24
Finished Apr 21 04:08:52 PM PDT 24
Peak memory 333292 kb
Host smart-0bae6304-66be-4b5d-bd13-8ac92dc60eb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2798355507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2798355507 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1654879587
Short name T779
Test name
Test status
Simulation time 24346426079 ps
CPU time 1045.99 seconds
Started Apr 21 03:40:34 PM PDT 24
Finished Apr 21 03:58:01 PM PDT 24
Peak memory 299108 kb
Host smart-e751a96b-874e-4e90-85ec-668cd8ae5ac3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1654879587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1654879587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.554746509
Short name T348
Test name
Test status
Simulation time 537982349111 ps
CPU time 5456.03 seconds
Started Apr 21 03:40:33 PM PDT 24
Finished Apr 21 05:11:30 PM PDT 24
Peak memory 646164 kb
Host smart-6a652fb9-e3d5-44a1-9bd4-b832fb379151
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=554746509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.554746509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.2589723138
Short name T245
Test name
Test status
Simulation time 247201623144 ps
CPU time 5172.91 seconds
Started Apr 21 03:40:32 PM PDT 24
Finished Apr 21 05:06:45 PM PDT 24
Peak memory 564048 kb
Host smart-9e326929-cbe6-4898-9795-becd591198de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2589723138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2589723138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.2467776676
Short name T316
Test name
Test status
Simulation time 19277104 ps
CPU time 0.89 seconds
Started Apr 21 03:41:02 PM PDT 24
Finished Apr 21 03:41:03 PM PDT 24
Peak memory 218348 kb
Host smart-c7f362b9-1476-4b08-8bd9-6451d180e971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467776676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2467776676 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.2004194074
Short name T820
Test name
Test status
Simulation time 9342437110 ps
CPU time 148.95 seconds
Started Apr 21 03:40:52 PM PDT 24
Finished Apr 21 03:43:21 PM PDT 24
Peak memory 236764 kb
Host smart-9efd415e-618a-4db0-87bf-3bb4e3304ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004194074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2004194074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.2922527386
Short name T320
Test name
Test status
Simulation time 5171701241 ps
CPU time 577.27 seconds
Started Apr 21 03:40:47 PM PDT 24
Finished Apr 21 03:50:24 PM PDT 24
Peak memory 233580 kb
Host smart-5ddb9d4a-8e75-48c0-a237-c64f797ce905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922527386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2922527386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.4264235669
Short name T770
Test name
Test status
Simulation time 1508714149 ps
CPU time 35.06 seconds
Started Apr 21 03:40:53 PM PDT 24
Finished Apr 21 03:41:28 PM PDT 24
Peak memory 234300 kb
Host smart-11a09e29-9c8d-4984-8c20-313c9a04a0ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4264235669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.4264235669 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2747501403
Short name T690
Test name
Test status
Simulation time 41681623 ps
CPU time 1.35 seconds
Started Apr 21 03:40:54 PM PDT 24
Finished Apr 21 03:40:55 PM PDT 24
Peak memory 221916 kb
Host smart-8378b225-bb9c-4443-ba82-5609ea3002f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747501403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2747501403 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.691365197
Short name T60
Test name
Test status
Simulation time 11752093170 ps
CPU time 83.14 seconds
Started Apr 21 03:40:50 PM PDT 24
Finished Apr 21 03:42:13 PM PDT 24
Peak memory 231088 kb
Host smart-c4583ed2-8245-4cfe-8019-df8c7be45706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691365197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.691365197 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1501391044
Short name T272
Test name
Test status
Simulation time 1903688881 ps
CPU time 85.56 seconds
Started Apr 21 03:40:54 PM PDT 24
Finished Apr 21 03:42:20 PM PDT 24
Peak memory 243004 kb
Host smart-5e31cce9-1927-405f-bb93-f27667c1698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501391044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1501391044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.3391256421
Short name T830
Test name
Test status
Simulation time 590789793 ps
CPU time 2.2 seconds
Started Apr 21 03:40:52 PM PDT 24
Finished Apr 21 03:40:55 PM PDT 24
Peak memory 218460 kb
Host smart-6ed51f94-364a-49e7-aa81-52898ff1e435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391256421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3391256421 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.3045095271
Short name T559
Test name
Test status
Simulation time 80140088 ps
CPU time 1.21 seconds
Started Apr 21 03:40:58 PM PDT 24
Finished Apr 21 03:40:59 PM PDT 24
Peak memory 218428 kb
Host smart-a4cb8b9e-d276-4e35-986b-89d3c45056ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045095271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3045095271 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1790077984
Short name T205
Test name
Test status
Simulation time 268199515545 ps
CPU time 1733.4 seconds
Started Apr 21 03:40:44 PM PDT 24
Finished Apr 21 04:09:38 PM PDT 24
Peak memory 345140 kb
Host smart-147cd366-48cb-4700-a4a9-71f095c81c2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790077984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1790077984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2132150426
Short name T1036
Test name
Test status
Simulation time 7106445752 ps
CPU time 227 seconds
Started Apr 21 03:40:44 PM PDT 24
Finished Apr 21 03:44:31 PM PDT 24
Peak memory 243076 kb
Host smart-c2039476-7c4c-443d-b4da-a37bf7084abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132150426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2132150426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.2892049383
Short name T202
Test name
Test status
Simulation time 1604522591 ps
CPU time 9.52 seconds
Started Apr 21 03:40:41 PM PDT 24
Finished Apr 21 03:40:51 PM PDT 24
Peak memory 223664 kb
Host smart-7a32d6d4-f948-4f4f-a7bd-28d2c719c984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892049383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.2892049383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3817804727
Short name T636
Test name
Test status
Simulation time 91246788529 ps
CPU time 549.95 seconds
Started Apr 21 03:41:01 PM PDT 24
Finished Apr 21 03:50:11 PM PDT 24
Peak memory 297772 kb
Host smart-96d2e5e9-a1f7-453a-a72d-91af157868d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3817804727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3817804727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.1675491025
Short name T948
Test name
Test status
Simulation time 372106978 ps
CPU time 6.23 seconds
Started Apr 21 03:40:51 PM PDT 24
Finished Apr 21 03:40:58 PM PDT 24
Peak memory 218564 kb
Host smart-5bcf2be6-c9ae-484e-a6cf-e82e9ed6f90e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675491025 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.1675491025 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2685704032
Short name T502
Test name
Test status
Simulation time 247774188 ps
CPU time 6.26 seconds
Started Apr 21 03:40:51 PM PDT 24
Finished Apr 21 03:40:57 PM PDT 24
Peak memory 219512 kb
Host smart-a72da9c2-383d-4522-8198-9d31a81e43c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685704032 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2685704032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.1159526572
Short name T580
Test name
Test status
Simulation time 22064713738 ps
CPU time 2128.49 seconds
Started Apr 21 03:40:45 PM PDT 24
Finished Apr 21 04:16:13 PM PDT 24
Peak memory 403176 kb
Host smart-108cf9db-f512-4f0e-830c-de849b1126ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1159526572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.1159526572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.3963451539
Short name T200
Test name
Test status
Simulation time 19043562440 ps
CPU time 1847.62 seconds
Started Apr 21 03:40:45 PM PDT 24
Finished Apr 21 04:11:33 PM PDT 24
Peak memory 383024 kb
Host smart-82ae6de4-a0a9-4e7c-bb84-5bd62010f496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3963451539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.3963451539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.3622127781
Short name T863
Test name
Test status
Simulation time 51020152058 ps
CPU time 1795.85 seconds
Started Apr 21 03:40:47 PM PDT 24
Finished Apr 21 04:10:44 PM PDT 24
Peak memory 343824 kb
Host smart-6292bcb4-c3d9-48ac-bb14-8e239634e3d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3622127781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3622127781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3055027175
Short name T862
Test name
Test status
Simulation time 27908093160 ps
CPU time 1380.3 seconds
Started Apr 21 03:40:48 PM PDT 24
Finished Apr 21 04:03:49 PM PDT 24
Peak memory 298240 kb
Host smart-38d0e9c8-0f28-48b6-9eaf-4a45c1944981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3055027175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3055027175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.1912350742
Short name T437
Test name
Test status
Simulation time 1873916042858 ps
CPU time 6101.16 seconds
Started Apr 21 03:40:50 PM PDT 24
Finished Apr 21 05:22:33 PM PDT 24
Peak memory 654964 kb
Host smart-de49d84b-897f-4539-9a6c-29755fc23510
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1912350742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.1912350742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.697003061
Short name T333
Test name
Test status
Simulation time 788040439738 ps
CPU time 5088.93 seconds
Started Apr 21 03:40:57 PM PDT 24
Finished Apr 21 05:05:47 PM PDT 24
Peak memory 564444 kb
Host smart-05ba7bab-bcb5-4b77-8ac5-4031121a0aa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=697003061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.697003061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.3389128961
Short name T991
Test name
Test status
Simulation time 49431484 ps
CPU time 0.88 seconds
Started Apr 21 03:41:26 PM PDT 24
Finished Apr 21 03:41:27 PM PDT 24
Peak memory 218292 kb
Host smart-f77a6aca-9c3d-418a-b958-6fe225f8d97e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389128961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.3389128961 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.4063650817
Short name T213
Test name
Test status
Simulation time 26990173537 ps
CPU time 263.98 seconds
Started Apr 21 03:41:19 PM PDT 24
Finished Apr 21 03:45:43 PM PDT 24
Peak memory 244540 kb
Host smart-3ee73098-5bd0-4b8e-8581-cf8b6314871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063650817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.4063650817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2158580788
Short name T1001
Test name
Test status
Simulation time 19232140229 ps
CPU time 891.81 seconds
Started Apr 21 03:41:10 PM PDT 24
Finished Apr 21 03:56:02 PM PDT 24
Peak memory 243056 kb
Host smart-548ba390-ce3f-4561-aecb-9db4f7cd3176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158580788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2158580788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.1228840732
Short name T961
Test name
Test status
Simulation time 26240395 ps
CPU time 1.03 seconds
Started Apr 21 03:41:19 PM PDT 24
Finished Apr 21 03:41:20 PM PDT 24
Peak memory 218328 kb
Host smart-c68722c0-4db5-4464-b586-e4c58bd22e72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1228840732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.1228840732 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.2788965353
Short name T953
Test name
Test status
Simulation time 73827347 ps
CPU time 1.08 seconds
Started Apr 21 03:41:26 PM PDT 24
Finished Apr 21 03:41:27 PM PDT 24
Peak memory 221972 kb
Host smart-c31c08a6-509d-4dd0-8367-7c2fa8eefeff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788965353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.2788965353 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.707586716
Short name T229
Test name
Test status
Simulation time 23476765777 ps
CPU time 285.22 seconds
Started Apr 21 03:41:21 PM PDT 24
Finished Apr 21 03:46:06 PM PDT 24
Peak memory 246492 kb
Host smart-0c2cadaf-7cd9-4025-876c-195dcfff7822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707586716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.707586716 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_key_error.3350890789
Short name T465
Test name
Test status
Simulation time 3765673513 ps
CPU time 5.76 seconds
Started Apr 21 03:41:19 PM PDT 24
Finished Apr 21 03:41:25 PM PDT 24
Peak memory 218556 kb
Host smart-303964b5-f472-42ed-b371-9add932c5046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350890789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.3350890789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.4135236458
Short name T866
Test name
Test status
Simulation time 2409507833 ps
CPU time 30.24 seconds
Started Apr 21 03:41:20 PM PDT 24
Finished Apr 21 03:41:51 PM PDT 24
Peak memory 227464 kb
Host smart-9d61e695-aa57-47c9-90d3-ddf90f2831c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135236458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.4135236458 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.2584549430
Short name T1063
Test name
Test status
Simulation time 33480677337 ps
CPU time 1208.7 seconds
Started Apr 21 03:41:11 PM PDT 24
Finished Apr 21 04:01:20 PM PDT 24
Peak memory 315052 kb
Host smart-ddb168d7-268b-45b9-b7a3-4603d512e03c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584549430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.2584549430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.2054257030
Short name T479
Test name
Test status
Simulation time 5862727973 ps
CPU time 78.31 seconds
Started Apr 21 03:41:10 PM PDT 24
Finished Apr 21 03:42:29 PM PDT 24
Peak memory 227084 kb
Host smart-3abcc23c-83a0-4f86-8e07-22397acde9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054257030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2054257030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.3622531761
Short name T657
Test name
Test status
Simulation time 14851305749 ps
CPU time 78.78 seconds
Started Apr 21 03:41:10 PM PDT 24
Finished Apr 21 03:42:29 PM PDT 24
Peak memory 219584 kb
Host smart-088de870-c9cd-4ca2-879e-1bd3d863a871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622531761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3622531761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.1631699296
Short name T522
Test name
Test status
Simulation time 67579868102 ps
CPU time 118.35 seconds
Started Apr 21 03:41:23 PM PDT 24
Finished Apr 21 03:43:21 PM PDT 24
Peak memory 243096 kb
Host smart-7ee28140-60df-4c24-9091-e88827521f37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1631699296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.1631699296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1823768210
Short name T610
Test name
Test status
Simulation time 479641837 ps
CPU time 6.44 seconds
Started Apr 21 03:41:15 PM PDT 24
Finished Apr 21 03:41:22 PM PDT 24
Peak memory 226644 kb
Host smart-5f538b66-5f41-4bb9-a4b2-97e7d4ec34d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823768210 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1823768210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.3045112695
Short name T419
Test name
Test status
Simulation time 947659757 ps
CPU time 7.07 seconds
Started Apr 21 03:41:21 PM PDT 24
Finished Apr 21 03:41:29 PM PDT 24
Peak memory 218568 kb
Host smart-5c7e1d80-c54f-4049-b990-3fe6efbe8f7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045112695 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.3045112695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.2700495729
Short name T322
Test name
Test status
Simulation time 360145808765 ps
CPU time 2661.65 seconds
Started Apr 21 03:41:10 PM PDT 24
Finished Apr 21 04:25:32 PM PDT 24
Peak memory 397828 kb
Host smart-790d9037-4981-4d0e-bc03-1cfc7c7dc864
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2700495729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.2700495729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.1301176309
Short name T1012
Test name
Test status
Simulation time 22995081165 ps
CPU time 2020.49 seconds
Started Apr 21 03:41:11 PM PDT 24
Finished Apr 21 04:14:52 PM PDT 24
Peak memory 392152 kb
Host smart-0cbc5be5-cfe7-4cca-a514-8002f39b912f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1301176309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.1301176309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.1601304371
Short name T642
Test name
Test status
Simulation time 15957125662 ps
CPU time 1513.77 seconds
Started Apr 21 03:41:11 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 344000 kb
Host smart-bbeaad68-0188-4a03-bfe4-c69343475081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1601304371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.1601304371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.3087677189
Short name T429
Test name
Test status
Simulation time 197187415918 ps
CPU time 1402.19 seconds
Started Apr 21 03:41:10 PM PDT 24
Finished Apr 21 04:04:33 PM PDT 24
Peak memory 300920 kb
Host smart-8ed84c09-7192-4ec8-97fa-89f6acde189d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3087677189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3087677189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.136147455
Short name T187
Test name
Test status
Simulation time 2311060766348 ps
CPU time 6731.17 seconds
Started Apr 21 03:41:14 PM PDT 24
Finished Apr 21 05:33:26 PM PDT 24
Peak memory 635072 kb
Host smart-d4a574e8-4d0b-40b9-9dc2-4228cbd04d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=136147455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.136147455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.2293573684
Short name T451
Test name
Test status
Simulation time 3660572814550 ps
CPU time 5593.81 seconds
Started Apr 21 03:41:21 PM PDT 24
Finished Apr 21 05:14:36 PM PDT 24
Peak memory 576916 kb
Host smart-4df38752-b760-4001-b71e-ab5e6e9e2ad5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2293573684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.2293573684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.732320673
Short name T1038
Test name
Test status
Simulation time 28782982 ps
CPU time 0.85 seconds
Started Apr 21 03:42:01 PM PDT 24
Finished Apr 21 03:42:02 PM PDT 24
Peak memory 218280 kb
Host smart-8bb9c7f5-ead3-4001-a4ef-131ef1f87e4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732320673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.732320673 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.1821750327
Short name T239
Test name
Test status
Simulation time 2340679515 ps
CPU time 64.46 seconds
Started Apr 21 03:41:39 PM PDT 24
Finished Apr 21 03:42:43 PM PDT 24
Peak memory 228064 kb
Host smart-41d44b71-7fcc-417b-9f58-15cf208649b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821750327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.1821750327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.4079673462
Short name T350
Test name
Test status
Simulation time 4195587799 ps
CPU time 241.31 seconds
Started Apr 21 03:41:30 PM PDT 24
Finished Apr 21 03:45:32 PM PDT 24
Peak memory 227844 kb
Host smart-d2bd60f0-4c3e-422c-badf-4e4bcaf39307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079673462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.4079673462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2953670970
Short name T780
Test name
Test status
Simulation time 11144521182 ps
CPU time 37.58 seconds
Started Apr 21 03:41:43 PM PDT 24
Finished Apr 21 03:42:21 PM PDT 24
Peak memory 227752 kb
Host smart-4eea8955-d33b-47fc-aa8d-c6a94019b5b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953670970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2953670970 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.2747299992
Short name T196
Test name
Test status
Simulation time 6624269893 ps
CPU time 41.88 seconds
Started Apr 21 03:41:52 PM PDT 24
Finished Apr 21 03:42:34 PM PDT 24
Peak memory 226784 kb
Host smart-18a8ee07-11fa-4c3f-922e-2282843cc9b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747299992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2747299992 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.1263499152
Short name T273
Test name
Test status
Simulation time 10048769659 ps
CPU time 140.73 seconds
Started Apr 21 03:41:41 PM PDT 24
Finished Apr 21 03:44:02 PM PDT 24
Peak memory 237184 kb
Host smart-ba9e6acf-a2f4-46b2-a962-1945a627b257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263499152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1263499152 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2794071791
Short name T36
Test name
Test status
Simulation time 44720753786 ps
CPU time 320.15 seconds
Started Apr 21 03:41:40 PM PDT 24
Finished Apr 21 03:47:00 PM PDT 24
Peak memory 254952 kb
Host smart-080232da-0fde-48ea-bdfe-5686a275465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794071791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2794071791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.1517570714
Short name T1050
Test name
Test status
Simulation time 748062846 ps
CPU time 2.75 seconds
Started Apr 21 03:41:41 PM PDT 24
Finished Apr 21 03:41:44 PM PDT 24
Peak memory 218408 kb
Host smart-4560329b-215b-49c4-a3ea-701495a8e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517570714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.1517570714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.938345958
Short name T908
Test name
Test status
Simulation time 52278965810 ps
CPU time 532.8 seconds
Started Apr 21 03:41:30 PM PDT 24
Finished Apr 21 03:50:23 PM PDT 24
Peak memory 262360 kb
Host smart-4fe47bb2-3344-4d5f-a0e3-1f40bbb5de9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938345958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.938345958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.1797030013
Short name T824
Test name
Test status
Simulation time 14386525888 ps
CPU time 496.05 seconds
Started Apr 21 03:41:29 PM PDT 24
Finished Apr 21 03:49:45 PM PDT 24
Peak memory 255144 kb
Host smart-040271f0-8121-4f99-b2d1-465a3a024cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797030013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1797030013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.3489932663
Short name T249
Test name
Test status
Simulation time 495240287 ps
CPU time 7.45 seconds
Started Apr 21 03:41:25 PM PDT 24
Finished Apr 21 03:41:33 PM PDT 24
Peak memory 222720 kb
Host smart-32c7b380-ce8a-4d55-96d3-98eba82c4d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489932663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3489932663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.1162389784
Short name T134
Test name
Test status
Simulation time 1346189477524 ps
CPU time 5311.6 seconds
Started Apr 21 03:41:53 PM PDT 24
Finished Apr 21 05:10:25 PM PDT 24
Peak memory 511752 kb
Host smart-8ef8f0f1-16b6-49e3-8d83-11a29a9e7562
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162389784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.1162389784 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.1148923180
Short name T797
Test name
Test status
Simulation time 951991342 ps
CPU time 6.21 seconds
Started Apr 21 03:41:35 PM PDT 24
Finished Apr 21 03:41:41 PM PDT 24
Peak memory 226580 kb
Host smart-0ae9f0d5-26fb-4560-b91a-c6b66987dbac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148923180 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.1148923180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2687655138
Short name T397
Test name
Test status
Simulation time 447027140 ps
CPU time 5.94 seconds
Started Apr 21 03:41:40 PM PDT 24
Finished Apr 21 03:41:46 PM PDT 24
Peak memory 226836 kb
Host smart-c663fb5c-e6af-406f-92d1-f1385d485d8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687655138 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2687655138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.3020223573
Short name T355
Test name
Test status
Simulation time 21127982177 ps
CPU time 1935.53 seconds
Started Apr 21 03:41:31 PM PDT 24
Finished Apr 21 04:13:47 PM PDT 24
Peak memory 396896 kb
Host smart-e08e66b1-8c03-4525-8144-b817ec9a04b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3020223573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.3020223573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1337666197
Short name T515
Test name
Test status
Simulation time 62699938364 ps
CPU time 1789.22 seconds
Started Apr 21 03:41:31 PM PDT 24
Finished Apr 21 04:11:21 PM PDT 24
Peak memory 381424 kb
Host smart-7dbef74f-065d-46b2-a86c-b44a07339a88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1337666197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1337666197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.1082114791
Short name T286
Test name
Test status
Simulation time 50058570506 ps
CPU time 1482.07 seconds
Started Apr 21 03:41:31 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 337516 kb
Host smart-768eb3f6-c376-400b-928f-28667a8a7620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1082114791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.1082114791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.446673682
Short name T370
Test name
Test status
Simulation time 350093407369 ps
CPU time 1426.24 seconds
Started Apr 21 03:41:32 PM PDT 24
Finished Apr 21 04:05:18 PM PDT 24
Peak memory 300576 kb
Host smart-c2ceab6f-c11a-4f1d-9975-367cee28746a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=446673682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.446673682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.297408820
Short name T992
Test name
Test status
Simulation time 358735601934 ps
CPU time 6105.02 seconds
Started Apr 21 03:41:33 PM PDT 24
Finished Apr 21 05:23:19 PM PDT 24
Peak memory 678140 kb
Host smart-c2b8db57-7b5d-40f5-8fc1-b60df36f4387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=297408820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.297408820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.417309504
Short name T959
Test name
Test status
Simulation time 150093088810 ps
CPU time 4791.38 seconds
Started Apr 21 03:41:36 PM PDT 24
Finished Apr 21 05:01:29 PM PDT 24
Peak memory 561640 kb
Host smart-90dd9430-989c-4e10-bd79-951300f5eb85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=417309504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.417309504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.3703091493
Short name T482
Test name
Test status
Simulation time 63743193 ps
CPU time 0.88 seconds
Started Apr 21 03:42:14 PM PDT 24
Finished Apr 21 03:42:15 PM PDT 24
Peak memory 218308 kb
Host smart-b0a48dcb-9bc8-4157-8c26-b392cbb9bee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703091493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3703091493 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.1450211520
Short name T939
Test name
Test status
Simulation time 4169855513 ps
CPU time 79.89 seconds
Started Apr 21 03:42:07 PM PDT 24
Finished Apr 21 03:43:27 PM PDT 24
Peak memory 231904 kb
Host smart-f2e78e81-3db5-4834-adf2-8096f759ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450211520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1450211520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2889647871
Short name T1027
Test name
Test status
Simulation time 17862723581 ps
CPU time 457.17 seconds
Started Apr 21 03:41:59 PM PDT 24
Finished Apr 21 03:49:37 PM PDT 24
Peak memory 230888 kb
Host smart-eaf93e8c-de35-4354-9225-d01026c844d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889647871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2889647871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3440886585
Short name T1031
Test name
Test status
Simulation time 3677963750 ps
CPU time 33.83 seconds
Started Apr 21 03:42:09 PM PDT 24
Finished Apr 21 03:42:43 PM PDT 24
Peak memory 228680 kb
Host smart-adec11ab-8842-4744-945e-70941aa09eda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3440886585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3440886585 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.4291802898
Short name T64
Test name
Test status
Simulation time 25262091 ps
CPU time 1.01 seconds
Started Apr 21 03:42:09 PM PDT 24
Finished Apr 21 03:42:10 PM PDT 24
Peak memory 221568 kb
Host smart-60227ff1-bebb-49e2-8050-509e03db0c30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4291802898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.4291802898 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.2010531104
Short name T981
Test name
Test status
Simulation time 3889978079 ps
CPU time 139.34 seconds
Started Apr 21 03:42:06 PM PDT 24
Finished Apr 21 03:44:25 PM PDT 24
Peak memory 235736 kb
Host smart-f50ae6b8-2f54-45b6-ab04-3b4b8dad4710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010531104 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2010531104 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.1815768957
Short name T682
Test name
Test status
Simulation time 22254256619 ps
CPU time 164.76 seconds
Started Apr 21 03:42:07 PM PDT 24
Finished Apr 21 03:44:52 PM PDT 24
Peak memory 243080 kb
Host smart-49a7981e-8272-4853-873a-8c17349db4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815768957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.1815768957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.780534021
Short name T263
Test name
Test status
Simulation time 1031076150 ps
CPU time 5.07 seconds
Started Apr 21 03:42:06 PM PDT 24
Finished Apr 21 03:42:11 PM PDT 24
Peak memory 218460 kb
Host smart-7818f8c0-f891-4374-aa82-8f4d2fdaa48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780534021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.780534021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1702560835
Short name T38
Test name
Test status
Simulation time 140141525 ps
CPU time 1.31 seconds
Started Apr 21 03:42:10 PM PDT 24
Finished Apr 21 03:42:12 PM PDT 24
Peak memory 218440 kb
Host smart-d96a627d-e757-4110-a5b9-53065383ee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702560835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1702560835 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.718017240
Short name T363
Test name
Test status
Simulation time 128272336434 ps
CPU time 3287.41 seconds
Started Apr 21 03:41:57 PM PDT 24
Finished Apr 21 04:36:45 PM PDT 24
Peak memory 507960 kb
Host smart-9935f56f-0749-4f04-b633-30006fb50e02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718017240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_an
d_output.718017240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.4084884555
Short name T459
Test name
Test status
Simulation time 4131842284 ps
CPU time 329.93 seconds
Started Apr 21 03:41:58 PM PDT 24
Finished Apr 21 03:47:28 PM PDT 24
Peak memory 247432 kb
Host smart-6f72c008-a9fa-4c77-ae20-2502bf5be2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084884555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.4084884555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.1065430246
Short name T577
Test name
Test status
Simulation time 2684965144 ps
CPU time 23.71 seconds
Started Apr 21 03:41:58 PM PDT 24
Finished Apr 21 03:42:22 PM PDT 24
Peak memory 226704 kb
Host smart-25b4fd1f-3a35-498f-98cb-6c0d12664d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065430246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.1065430246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.21188976
Short name T902
Test name
Test status
Simulation time 109389239967 ps
CPU time 1030.3 seconds
Started Apr 21 03:42:10 PM PDT 24
Finished Apr 21 03:59:21 PM PDT 24
Peak memory 341420 kb
Host smart-53a88530-4dcb-407c-9716-4d942a9231d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=21188976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.21188976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.3305077495
Short name T368
Test name
Test status
Simulation time 214951917 ps
CPU time 6.16 seconds
Started Apr 21 03:42:02 PM PDT 24
Finished Apr 21 03:42:09 PM PDT 24
Peak memory 218584 kb
Host smart-f125bec3-028d-4eb3-af40-5519a305acd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305077495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.3305077495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.565777185
Short name T238
Test name
Test status
Simulation time 801191497 ps
CPU time 6.77 seconds
Started Apr 21 03:42:05 PM PDT 24
Finished Apr 21 03:42:12 PM PDT 24
Peak memory 226612 kb
Host smart-90871990-f190-46a2-b485-b703eebafd37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565777185 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.565777185 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.2258242675
Short name T367
Test name
Test status
Simulation time 65192977135 ps
CPU time 2238.73 seconds
Started Apr 21 03:42:05 PM PDT 24
Finished Apr 21 04:19:24 PM PDT 24
Peak memory 391940 kb
Host smart-d23b7b0d-f5c0-454c-a540-8d28a5e17fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2258242675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.2258242675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.2797024952
Short name T881
Test name
Test status
Simulation time 155017875139 ps
CPU time 1992.59 seconds
Started Apr 21 03:42:03 PM PDT 24
Finished Apr 21 04:15:17 PM PDT 24
Peak memory 376968 kb
Host smart-a021dddb-d1ab-4beb-b504-cb3bb35870ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2797024952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2797024952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.2484741244
Short name T917
Test name
Test status
Simulation time 75374961519 ps
CPU time 1805.3 seconds
Started Apr 21 03:42:02 PM PDT 24
Finished Apr 21 04:12:08 PM PDT 24
Peak memory 342224 kb
Host smart-07f11cf9-0428-4d83-b632-09a46bfc4408
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2484741244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.2484741244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.145937947
Short name T1079
Test name
Test status
Simulation time 11749499005 ps
CPU time 1160.32 seconds
Started Apr 21 03:42:04 PM PDT 24
Finished Apr 21 04:01:25 PM PDT 24
Peak memory 302620 kb
Host smart-7f49e839-9a7f-463c-b4bd-e5a68f1d766d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=145937947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.145937947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.259349273
Short name T378
Test name
Test status
Simulation time 181591152717 ps
CPU time 5463.5 seconds
Started Apr 21 03:42:04 PM PDT 24
Finished Apr 21 05:13:08 PM PDT 24
Peak memory 660228 kb
Host smart-677ad262-ca4d-4e7c-a695-74daef8b8cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=259349273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.259349273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.1422412228
Short name T697
Test name
Test status
Simulation time 239925505723 ps
CPU time 4530.17 seconds
Started Apr 21 03:42:04 PM PDT 24
Finished Apr 21 04:57:35 PM PDT 24
Peak memory 559900 kb
Host smart-07a8e263-2205-40c2-9e6a-6b16fe9c4460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1422412228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1422412228 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.2666018317
Short name T485
Test name
Test status
Simulation time 59596620 ps
CPU time 0.89 seconds
Started Apr 21 03:42:36 PM PDT 24
Finished Apr 21 03:42:37 PM PDT 24
Peak memory 218296 kb
Host smart-fbce83cd-e6b9-46a5-abd1-978f705582e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666018317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.2666018317 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.3267985018
Short name T759
Test name
Test status
Simulation time 3542843362 ps
CPU time 208.41 seconds
Started Apr 21 03:42:27 PM PDT 24
Finished Apr 21 03:45:56 PM PDT 24
Peak memory 242788 kb
Host smart-98abbc02-2811-4c88-a9b5-eb849c7c3c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267985018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.3267985018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.1786259297
Short name T574
Test name
Test status
Simulation time 22327753056 ps
CPU time 970.15 seconds
Started Apr 21 03:42:18 PM PDT 24
Finished Apr 21 03:58:28 PM PDT 24
Peak memory 236388 kb
Host smart-688b200f-b9f6-4648-8aa7-b52b01bb01b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786259297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.1786259297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.1138470550
Short name T840
Test name
Test status
Simulation time 41835177 ps
CPU time 1.2 seconds
Started Apr 21 03:42:38 PM PDT 24
Finished Apr 21 03:42:39 PM PDT 24
Peak memory 221844 kb
Host smart-59d27ce8-3546-4ef4-a502-a1b7e7ae58c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138470550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1138470550 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_error.3313156588
Short name T867
Test name
Test status
Simulation time 177780720480 ps
CPU time 489.33 seconds
Started Apr 21 03:42:29 PM PDT 24
Finished Apr 21 03:50:39 PM PDT 24
Peak memory 260400 kb
Host smart-7d566cd5-c26d-4ab2-a1fe-15732b2e3777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313156588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.3313156588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.2199072866
Short name T563
Test name
Test status
Simulation time 750533916 ps
CPU time 4.67 seconds
Started Apr 21 03:42:33 PM PDT 24
Finished Apr 21 03:42:37 PM PDT 24
Peak memory 218424 kb
Host smart-bcb2032a-998c-4f73-9be5-e2f5fe45d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199072866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2199072866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.318251008
Short name T666
Test name
Test status
Simulation time 420130740997 ps
CPU time 2847.21 seconds
Started Apr 21 03:42:18 PM PDT 24
Finished Apr 21 04:29:46 PM PDT 24
Peak memory 426756 kb
Host smart-26196d47-a9ac-441e-a543-71730cab3a91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318251008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an
d_output.318251008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.2897245467
Short name T670
Test name
Test status
Simulation time 5313296112 ps
CPU time 496.07 seconds
Started Apr 21 03:42:17 PM PDT 24
Finished Apr 21 03:50:33 PM PDT 24
Peak memory 253432 kb
Host smart-8f8c6972-0d4f-4ca1-a5ac-23d288a1398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897245467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.2897245467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1581400823
Short name T124
Test name
Test status
Simulation time 22670412378 ps
CPU time 76.77 seconds
Started Apr 21 03:42:15 PM PDT 24
Finished Apr 21 03:43:32 PM PDT 24
Peak memory 226632 kb
Host smart-a1a27aad-4d8a-4df6-b93e-3693bbebf61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581400823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1581400823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.939291756
Short name T1017
Test name
Test status
Simulation time 9083712978 ps
CPU time 726 seconds
Started Apr 21 03:42:33 PM PDT 24
Finished Apr 21 03:54:40 PM PDT 24
Peak memory 302068 kb
Host smart-ac1a7a4d-6702-4cf5-830c-d9aa5add7dcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=939291756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.939291756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1426370394
Short name T969
Test name
Test status
Simulation time 201789793 ps
CPU time 6.71 seconds
Started Apr 21 03:42:26 PM PDT 24
Finished Apr 21 03:42:33 PM PDT 24
Peak memory 226600 kb
Host smart-5345c295-28ca-424b-acdf-b10fbe56a3cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426370394 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1426370394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.320112397
Short name T1065
Test name
Test status
Simulation time 116633793 ps
CPU time 6.17 seconds
Started Apr 21 03:42:29 PM PDT 24
Finished Apr 21 03:42:35 PM PDT 24
Peak memory 219500 kb
Host smart-0522eb3c-315e-4375-9707-81dcfaa2df5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320112397 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.kmac_test_vectors_kmac_xof.320112397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.4077611200
Short name T281
Test name
Test status
Simulation time 381089254312 ps
CPU time 2558.3 seconds
Started Apr 21 03:42:15 PM PDT 24
Finished Apr 21 04:24:54 PM PDT 24
Peak memory 389972 kb
Host smart-c9eb5ec1-dd7b-4872-b7bf-020147580302
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4077611200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.4077611200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.2449929907
Short name T215
Test name
Test status
Simulation time 19713623780 ps
CPU time 1846.1 seconds
Started Apr 21 03:42:16 PM PDT 24
Finished Apr 21 04:13:03 PM PDT 24
Peak memory 395408 kb
Host smart-8c22e892-5ee8-4860-89c6-798b7456ca67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2449929907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.2449929907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.1439576713
Short name T304
Test name
Test status
Simulation time 16656818563 ps
CPU time 1659.57 seconds
Started Apr 21 03:42:19 PM PDT 24
Finished Apr 21 04:09:59 PM PDT 24
Peak memory 339220 kb
Host smart-f662bf65-66a6-4396-b71d-0db401662af8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1439576713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.1439576713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.1385988107
Short name T819
Test name
Test status
Simulation time 22965188438 ps
CPU time 1229.07 seconds
Started Apr 21 03:42:28 PM PDT 24
Finished Apr 21 04:02:57 PM PDT 24
Peak memory 302828 kb
Host smart-dbbb16b3-b97a-45df-8714-b7b269ab023b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1385988107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.1385988107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.4234659822
Short name T1081
Test name
Test status
Simulation time 355058271433 ps
CPU time 5875.57 seconds
Started Apr 21 03:42:27 PM PDT 24
Finished Apr 21 05:20:23 PM PDT 24
Peak memory 634192 kb
Host smart-5741217e-deff-44e1-8a60-882be662c49b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4234659822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.4234659822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.2868884005
Short name T86
Test name
Test status
Simulation time 323066022570 ps
CPU time 4705.53 seconds
Started Apr 21 03:42:25 PM PDT 24
Finished Apr 21 05:00:51 PM PDT 24
Peak memory 576852 kb
Host smart-07198877-3764-4ffd-b4e1-f848aa969dfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2868884005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.2868884005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.283442546
Short name T860
Test name
Test status
Simulation time 219763656 ps
CPU time 0.91 seconds
Started Apr 21 03:43:07 PM PDT 24
Finished Apr 21 03:43:08 PM PDT 24
Peak memory 218344 kb
Host smart-aa459b43-8183-4465-a86d-02cf062fe1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283442546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.283442546 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.612400885
Short name T12
Test name
Test status
Simulation time 19386441866 ps
CPU time 117.11 seconds
Started Apr 21 03:42:55 PM PDT 24
Finished Apr 21 03:44:52 PM PDT 24
Peak memory 233832 kb
Host smart-8ca52b88-dc70-4525-984f-8c9cb0ec514d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612400885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.612400885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.688090091
Short name T142
Test name
Test status
Simulation time 26231464656 ps
CPU time 764.04 seconds
Started Apr 21 03:42:43 PM PDT 24
Finished Apr 21 03:55:27 PM PDT 24
Peak memory 242564 kb
Host smart-8f7cb921-68f1-489b-9689-8a9e878fcb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688090091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.688090091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.693157573
Short name T331
Test name
Test status
Simulation time 1284029895 ps
CPU time 39.95 seconds
Started Apr 21 03:43:02 PM PDT 24
Finished Apr 21 03:43:42 PM PDT 24
Peak memory 226876 kb
Host smart-a9e6883e-9ab0-4656-90ad-5e6fd44bcedf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693157573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.693157573 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3321473587
Short name T844
Test name
Test status
Simulation time 512361836 ps
CPU time 12.46 seconds
Started Apr 21 03:43:02 PM PDT 24
Finished Apr 21 03:43:15 PM PDT 24
Peak memory 226460 kb
Host smart-dffc7505-ec0f-48b7-9b48-348b3de4dda3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3321473587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3321473587 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.2830696154
Short name T677
Test name
Test status
Simulation time 35148399475 ps
CPU time 247.16 seconds
Started Apr 21 03:42:58 PM PDT 24
Finished Apr 21 03:47:05 PM PDT 24
Peak memory 246084 kb
Host smart-1578f549-8185-4257-a936-d1d614b78f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830696154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.2830696154 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.4187045613
Short name T154
Test name
Test status
Simulation time 22295501332 ps
CPU time 226.64 seconds
Started Apr 21 03:43:06 PM PDT 24
Finished Apr 21 03:46:53 PM PDT 24
Peak memory 259072 kb
Host smart-c6935d21-6b40-4b22-a227-9761f0949f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187045613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.4187045613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_key_error.3341925544
Short name T380
Test name
Test status
Simulation time 953640518 ps
CPU time 5.74 seconds
Started Apr 21 03:43:01 PM PDT 24
Finished Apr 21 03:43:07 PM PDT 24
Peak memory 218468 kb
Host smart-46bc6725-05bb-4cee-a549-8f0a0a03a06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341925544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3341925544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.1960262423
Short name T499
Test name
Test status
Simulation time 100203319 ps
CPU time 1.4 seconds
Started Apr 21 03:43:02 PM PDT 24
Finished Apr 21 03:43:03 PM PDT 24
Peak memory 219392 kb
Host smart-a0f97c7c-f939-465e-b8db-eec15ab5f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960262423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.1960262423 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.194308249
Short name T738
Test name
Test status
Simulation time 29302924373 ps
CPU time 1407.96 seconds
Started Apr 21 03:42:39 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 332124 kb
Host smart-f079906f-5c07-450b-87e0-5bbe5ddff2c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194308249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_an
d_output.194308249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.160064764
Short name T684
Test name
Test status
Simulation time 3130912130 ps
CPU time 30.72 seconds
Started Apr 21 03:42:42 PM PDT 24
Finished Apr 21 03:43:13 PM PDT 24
Peak memory 226732 kb
Host smart-bc711741-b476-4601-89d9-42bb3a659c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160064764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.160064764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.2795272892
Short name T832
Test name
Test status
Simulation time 9868208561 ps
CPU time 55.3 seconds
Started Apr 21 03:42:37 PM PDT 24
Finished Apr 21 03:43:33 PM PDT 24
Peak memory 226652 kb
Host smart-0473d9b8-de9b-4f55-af72-f1892881e11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795272892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.2795272892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.2174459587
Short name T486
Test name
Test status
Simulation time 7606478002 ps
CPU time 94.8 seconds
Started Apr 21 03:43:06 PM PDT 24
Finished Apr 21 03:44:41 PM PDT 24
Peak memory 243128 kb
Host smart-7329052c-d1ce-42cd-88e6-3d92c92deff4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2174459587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.2174459587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.429471903
Short name T926
Test name
Test status
Simulation time 1049409171 ps
CPU time 6.52 seconds
Started Apr 21 03:42:52 PM PDT 24
Finished Apr 21 03:42:59 PM PDT 24
Peak memory 226600 kb
Host smart-61d00421-69c8-4b52-a930-7f7c93e7c3f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429471903 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.kmac_test_vectors_kmac.429471903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.48055921
Short name T537
Test name
Test status
Simulation time 373418345 ps
CPU time 5.77 seconds
Started Apr 21 03:42:52 PM PDT 24
Finished Apr 21 03:42:58 PM PDT 24
Peak memory 218636 kb
Host smart-428e236a-02ec-49d3-8d7b-0b058f5607bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48055921 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.kmac_test_vectors_kmac_xof.48055921 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.1606216326
Short name T255
Test name
Test status
Simulation time 91319525765 ps
CPU time 2082.07 seconds
Started Apr 21 03:42:43 PM PDT 24
Finished Apr 21 04:17:25 PM PDT 24
Peak memory 409588 kb
Host smart-39e9f127-692f-4d17-9fb3-30cfe9ef18a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1606216326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.1606216326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.3824509534
Short name T481
Test name
Test status
Simulation time 18739392124 ps
CPU time 2106.32 seconds
Started Apr 21 03:42:47 PM PDT 24
Finished Apr 21 04:17:54 PM PDT 24
Peak memory 377948 kb
Host smart-241722f8-fb13-4282-9515-95be00d9f0e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3824509534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.3824509534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.325160791
Short name T639
Test name
Test status
Simulation time 75721404496 ps
CPU time 1969.45 seconds
Started Apr 21 03:42:48 PM PDT 24
Finished Apr 21 04:15:38 PM PDT 24
Peak memory 343068 kb
Host smart-e048714a-62a1-41f8-8ce1-4d06af46586e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=325160791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.325160791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.4167973120
Short name T342
Test name
Test status
Simulation time 34925863952 ps
CPU time 1237.64 seconds
Started Apr 21 03:42:47 PM PDT 24
Finished Apr 21 04:03:25 PM PDT 24
Peak memory 298396 kb
Host smart-5e8d008d-c09e-47e0-8875-f8a83af97f5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4167973120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.4167973120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.536580032
Short name T906
Test name
Test status
Simulation time 735567295094 ps
CPU time 5214.61 seconds
Started Apr 21 03:42:46 PM PDT 24
Finished Apr 21 05:09:42 PM PDT 24
Peak memory 655984 kb
Host smart-40bc23b9-bf26-4a5b-9d6c-dea06f27f461
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=536580032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.536580032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.2210529548
Short name T211
Test name
Test status
Simulation time 108501890262 ps
CPU time 4263.88 seconds
Started Apr 21 03:42:50 PM PDT 24
Finished Apr 21 04:53:55 PM PDT 24
Peak memory 559232 kb
Host smart-6048d0f5-d112-4eb4-8033-6214f5589533
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2210529548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.2210529548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.3076497083
Short name T314
Test name
Test status
Simulation time 16330104 ps
CPU time 0.89 seconds
Started Apr 21 03:43:27 PM PDT 24
Finished Apr 21 03:43:28 PM PDT 24
Peak memory 220368 kb
Host smart-fccedcd8-64ff-4ed8-8d4d-61fe858db957
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076497083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.3076497083 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2266304622
Short name T395
Test name
Test status
Simulation time 1886850362 ps
CPU time 14.19 seconds
Started Apr 21 03:43:13 PM PDT 24
Finished Apr 21 03:43:27 PM PDT 24
Peak memory 218552 kb
Host smart-ac2cfffc-5003-4c7e-94f3-7feb7e3736ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266304622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2266304622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.132849113
Short name T676
Test name
Test status
Simulation time 60835081855 ps
CPU time 570.31 seconds
Started Apr 21 03:43:09 PM PDT 24
Finished Apr 21 03:52:39 PM PDT 24
Peak memory 233172 kb
Host smart-1cc790d3-4532-4d91-be63-b9c3a452fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132849113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.132849113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.4270865615
Short name T873
Test name
Test status
Simulation time 47015724 ps
CPU time 3.21 seconds
Started Apr 21 03:43:22 PM PDT 24
Finished Apr 21 03:43:26 PM PDT 24
Peak memory 223432 kb
Host smart-2a5036b0-d5cf-4dea-91b3-158e24e23c63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4270865615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.4270865615 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3696405341
Short name T475
Test name
Test status
Simulation time 126416411 ps
CPU time 1.2 seconds
Started Apr 21 03:43:24 PM PDT 24
Finished Apr 21 03:43:25 PM PDT 24
Peak memory 222160 kb
Host smart-31cdb1ac-893d-4801-bdae-09dfefe5fb0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3696405341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3696405341 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.4186913936
Short name T1024
Test name
Test status
Simulation time 2583638956 ps
CPU time 114.09 seconds
Started Apr 21 03:43:17 PM PDT 24
Finished Apr 21 03:45:11 PM PDT 24
Peak memory 234104 kb
Host smart-8762faf8-842d-453b-bd18-edf23ee90e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186913936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.4186913936 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.1887947672
Short name T37
Test name
Test status
Simulation time 9675910946 ps
CPU time 231.35 seconds
Started Apr 21 03:43:15 PM PDT 24
Finished Apr 21 03:47:07 PM PDT 24
Peak memory 252140 kb
Host smart-f422a939-3113-4242-9da3-5c410a75383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887947672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1887947672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.964524073
Short name T265
Test name
Test status
Simulation time 1212084437 ps
CPU time 6.74 seconds
Started Apr 21 03:43:19 PM PDT 24
Finished Apr 21 03:43:26 PM PDT 24
Peak memory 218460 kb
Host smart-824b95cf-69a6-436c-8233-df0a34895556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964524073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.964524073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.1447670805
Short name T868
Test name
Test status
Simulation time 51446382 ps
CPU time 1.54 seconds
Started Apr 21 03:43:25 PM PDT 24
Finished Apr 21 03:43:26 PM PDT 24
Peak memory 218432 kb
Host smart-24ba41d3-f255-4ed9-98fb-8173f15751e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447670805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.1447670805 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.1936429886
Short name T1041
Test name
Test status
Simulation time 44958768619 ps
CPU time 717.06 seconds
Started Apr 21 03:43:09 PM PDT 24
Finished Apr 21 03:55:06 PM PDT 24
Peak memory 279864 kb
Host smart-a98c151e-6a52-4f18-b0cb-9e57bdb2b1c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936429886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.1936429886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2290963538
Short name T360
Test name
Test status
Simulation time 20469573211 ps
CPU time 527.15 seconds
Started Apr 21 03:43:07 PM PDT 24
Finished Apr 21 03:51:54 PM PDT 24
Peak memory 255912 kb
Host smart-057f67e5-e81a-4c75-a94a-1fb7def86d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290963538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2290963538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.2440378338
Short name T145
Test name
Test status
Simulation time 1352815763 ps
CPU time 7.39 seconds
Started Apr 21 03:43:03 PM PDT 24
Finished Apr 21 03:43:11 PM PDT 24
Peak memory 226568 kb
Host smart-d2a53eed-4548-412c-9d2f-65454c009eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440378338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2440378338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2089201728
Short name T144
Test name
Test status
Simulation time 108460080520 ps
CPU time 1936.47 seconds
Started Apr 21 03:43:25 PM PDT 24
Finished Apr 21 04:15:42 PM PDT 24
Peak memory 431500 kb
Host smart-40ed8f9b-4a7d-4cb7-a7f3-111e98a4e2bd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2089201728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2089201728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.3982878593
Short name T198
Test name
Test status
Simulation time 370989375 ps
CPU time 6.47 seconds
Started Apr 21 03:43:10 PM PDT 24
Finished Apr 21 03:43:17 PM PDT 24
Peak memory 219484 kb
Host smart-38eaedfb-7a67-433c-b622-bf64b6e34dc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982878593 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.kmac_test_vectors_kmac.3982878593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.3969833708
Short name T334
Test name
Test status
Simulation time 1672194009 ps
CPU time 6.08 seconds
Started Apr 21 03:43:11 PM PDT 24
Finished Apr 21 03:43:17 PM PDT 24
Peak memory 218568 kb
Host smart-5cb7d5e4-2044-4908-9ca0-55cdfd673486
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969833708 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.3969833708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1595428556
Short name T753
Test name
Test status
Simulation time 100744390583 ps
CPU time 2512.55 seconds
Started Apr 21 03:43:09 PM PDT 24
Finished Apr 21 04:25:02 PM PDT 24
Peak memory 392468 kb
Host smart-8ed77395-a17f-4991-9c84-80a966a76fb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1595428556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1595428556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.480625886
Short name T613
Test name
Test status
Simulation time 19978378687 ps
CPU time 2147.97 seconds
Started Apr 21 03:43:09 PM PDT 24
Finished Apr 21 04:18:57 PM PDT 24
Peak memory 383108 kb
Host smart-b25ae430-b5fc-4fd6-84a3-ed0afca9ed4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=480625886 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.480625886 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1896389380
Short name T680
Test name
Test status
Simulation time 262193563831 ps
CPU time 1942.79 seconds
Started Apr 21 03:43:08 PM PDT 24
Finished Apr 21 04:15:31 PM PDT 24
Peak memory 337728 kb
Host smart-3bf4493e-0469-4155-b7b7-516390e89521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1896389380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1896389380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.3537237400
Short name T798
Test name
Test status
Simulation time 126659957688 ps
CPU time 1379.5 seconds
Started Apr 21 03:43:07 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 299828 kb
Host smart-0847ae08-5833-49ba-9acb-106e3e87d483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3537237400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.3537237400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.241617358
Short name T951
Test name
Test status
Simulation time 701375614637 ps
CPU time 5560.88 seconds
Started Apr 21 03:43:10 PM PDT 24
Finished Apr 21 05:15:52 PM PDT 24
Peak memory 650428 kb
Host smart-0f299cf3-049d-4369-b40c-aafb1f0d7986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=241617358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.241617358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3555927274
Short name T627
Test name
Test status
Simulation time 55753418149 ps
CPU time 4565.38 seconds
Started Apr 21 03:43:10 PM PDT 24
Finished Apr 21 04:59:17 PM PDT 24
Peak memory 566428 kb
Host smart-343f620a-d482-48d8-81bf-98cfc8a52235
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3555927274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3555927274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.3237412871
Short name T436
Test name
Test status
Simulation time 25591001 ps
CPU time 0.8 seconds
Started Apr 21 03:43:47 PM PDT 24
Finished Apr 21 03:43:48 PM PDT 24
Peak memory 220364 kb
Host smart-454c5339-6d43-4027-86ab-041705f219d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237412871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.3237412871 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.552542060
Short name T223
Test name
Test status
Simulation time 2737709686 ps
CPU time 12.27 seconds
Started Apr 21 03:43:39 PM PDT 24
Finished Apr 21 03:43:52 PM PDT 24
Peak memory 226876 kb
Host smart-6f2ce4a8-c7c0-4d4d-adee-a1b8f52092b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552542060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.552542060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.266675934
Short name T935
Test name
Test status
Simulation time 464032152 ps
CPU time 21.92 seconds
Started Apr 21 03:43:32 PM PDT 24
Finished Apr 21 03:43:54 PM PDT 24
Peak memory 226648 kb
Host smart-374f153f-bfeb-4042-ab1b-03e1b43c403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266675934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.266675934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.2704982485
Short name T655
Test name
Test status
Simulation time 21259601 ps
CPU time 1 seconds
Started Apr 21 03:43:42 PM PDT 24
Finished Apr 21 03:43:43 PM PDT 24
Peak memory 218276 kb
Host smart-6ea6da52-6744-43a4-9d0f-e945eec835a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2704982485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.2704982485 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2652977994
Short name T65
Test name
Test status
Simulation time 55150066 ps
CPU time 0.9 seconds
Started Apr 21 03:43:42 PM PDT 24
Finished Apr 21 03:43:43 PM PDT 24
Peak memory 220512 kb
Host smart-d720effb-eb8f-486f-820d-26289c9c147b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652977994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2652977994 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.505924732
Short name T62
Test name
Test status
Simulation time 8376838726 ps
CPU time 159.97 seconds
Started Apr 21 03:43:39 PM PDT 24
Finished Apr 21 03:46:19 PM PDT 24
Peak memory 237176 kb
Host smart-fd0f2160-f1e2-4134-9e57-fd793fd6f296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505924732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.505924732 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.4046085276
Short name T415
Test name
Test status
Simulation time 2375087810 ps
CPU time 97.84 seconds
Started Apr 21 03:43:42 PM PDT 24
Finished Apr 21 03:45:20 PM PDT 24
Peak memory 243116 kb
Host smart-9f82a0a8-925e-4db2-a481-6cd1814999a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046085276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.4046085276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2601513749
Short name T971
Test name
Test status
Simulation time 540006896 ps
CPU time 3.33 seconds
Started Apr 21 03:43:43 PM PDT 24
Finished Apr 21 03:43:46 PM PDT 24
Peak memory 218464 kb
Host smart-233181ca-82c8-49ef-bbd6-04d0a8aac5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601513749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2601513749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.3980925571
Short name T956
Test name
Test status
Simulation time 4245161391 ps
CPU time 18.82 seconds
Started Apr 21 03:43:42 PM PDT 24
Finished Apr 21 03:44:01 PM PDT 24
Peak memory 231412 kb
Host smart-e899b190-73c3-4016-8d34-f3660687b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980925571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.3980925571 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2956474948
Short name T591
Test name
Test status
Simulation time 27126031848 ps
CPU time 2805.14 seconds
Started Apr 21 03:43:28 PM PDT 24
Finished Apr 21 04:30:13 PM PDT 24
Peak memory 450628 kb
Host smart-e090aa68-58aa-489b-a6a5-2f6005b972c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956474948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2956474948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.1081923292
Short name T275
Test name
Test status
Simulation time 14858143009 ps
CPU time 489.47 seconds
Started Apr 21 03:43:30 PM PDT 24
Finished Apr 21 03:51:40 PM PDT 24
Peak memory 255840 kb
Host smart-c9e0cbff-ce77-4e24-ab31-85f7c18a4e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081923292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.1081923292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.427722344
Short name T190
Test name
Test status
Simulation time 1444817179 ps
CPU time 29.66 seconds
Started Apr 21 03:43:26 PM PDT 24
Finished Apr 21 03:43:56 PM PDT 24
Peak memory 226648 kb
Host smart-8f3aeaf3-a3a8-45af-a43e-faffc74cd75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427722344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.427722344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.797403496
Short name T849
Test name
Test status
Simulation time 38777048745 ps
CPU time 485.7 seconds
Started Apr 21 03:43:42 PM PDT 24
Finished Apr 21 03:51:48 PM PDT 24
Peak memory 281824 kb
Host smart-56281a6b-7cc0-40bf-ac5a-a03a30257510
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=797403496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.797403496 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.600952678
Short name T822
Test name
Test status
Simulation time 267188866 ps
CPU time 5.79 seconds
Started Apr 21 03:43:39 PM PDT 24
Finished Apr 21 03:43:45 PM PDT 24
Peak memory 218500 kb
Host smart-c2f13c90-af8e-494a-b5c0-cd955efd0fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600952678 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.kmac_test_vectors_kmac.600952678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3070767896
Short name T542
Test name
Test status
Simulation time 4799104389 ps
CPU time 6.52 seconds
Started Apr 21 03:43:39 PM PDT 24
Finished Apr 21 03:43:46 PM PDT 24
Peak memory 226680 kb
Host smart-ad047980-3fc9-470f-bace-4f494365a182
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070767896 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3070767896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.1986853021
Short name T817
Test name
Test status
Simulation time 100644601081 ps
CPU time 2442.65 seconds
Started Apr 21 03:43:30 PM PDT 24
Finished Apr 21 04:24:14 PM PDT 24
Peak memory 396308 kb
Host smart-897ad34a-6f8f-435b-87ad-d3368fac9ade
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1986853021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.1986853021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.742403229
Short name T816
Test name
Test status
Simulation time 89712290894 ps
CPU time 2088.44 seconds
Started Apr 21 03:43:30 PM PDT 24
Finished Apr 21 04:18:19 PM PDT 24
Peak memory 391624 kb
Host smart-db0a156c-e279-4b67-8c8c-559482656ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=742403229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.742403229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.4289028814
Short name T528
Test name
Test status
Simulation time 73177305428 ps
CPU time 1780.2 seconds
Started Apr 21 03:43:32 PM PDT 24
Finished Apr 21 04:13:12 PM PDT 24
Peak memory 341964 kb
Host smart-b7068f8d-f200-41d2-987c-3e576b3847e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4289028814 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.4289028814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.3806060968
Short name T740
Test name
Test status
Simulation time 12586910257 ps
CPU time 1219.66 seconds
Started Apr 21 03:43:35 PM PDT 24
Finished Apr 21 04:03:55 PM PDT 24
Peak memory 299400 kb
Host smart-b3fba4b6-7b6c-4966-8b7c-9a4ac626ac50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3806060968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.3806060968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.111656267
Short name T383
Test name
Test status
Simulation time 3776344104898 ps
CPU time 5952.41 seconds
Started Apr 21 03:43:36 PM PDT 24
Finished Apr 21 05:22:49 PM PDT 24
Peak memory 660568 kb
Host smart-13e8ec3a-4b2a-43fc-8785-2d48918e7ada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=111656267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.111656267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.389393541
Short name T938
Test name
Test status
Simulation time 220518391651 ps
CPU time 5215.73 seconds
Started Apr 21 03:43:35 PM PDT 24
Finished Apr 21 05:10:31 PM PDT 24
Peak memory 577020 kb
Host smart-edf1c097-fe3c-4822-a335-ec8ec949edb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=389393541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.389393541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1859513881
Short name T811
Test name
Test status
Simulation time 24864045 ps
CPU time 0.87 seconds
Started Apr 21 03:44:04 PM PDT 24
Finished Apr 21 03:44:05 PM PDT 24
Peak memory 218296 kb
Host smart-3e9e3e18-353a-49e5-9ae2-c098c4a7207e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859513881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1859513881 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.3157649734
Short name T1044
Test name
Test status
Simulation time 1299323410 ps
CPU time 70.23 seconds
Started Apr 21 03:43:57 PM PDT 24
Finished Apr 21 03:45:07 PM PDT 24
Peak memory 231056 kb
Host smart-50cebc4f-f71b-4b46-9aee-8d9d8eeaea0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157649734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.3157649734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2602510011
Short name T678
Test name
Test status
Simulation time 511300617 ps
CPU time 27.62 seconds
Started Apr 21 03:43:47 PM PDT 24
Finished Apr 21 03:44:15 PM PDT 24
Peak memory 226580 kb
Host smart-85a2ab64-cc1d-4a97-9229-0c579115d30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602510011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2602510011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.1853995076
Short name T54
Test name
Test status
Simulation time 53569826 ps
CPU time 1.12 seconds
Started Apr 21 03:43:58 PM PDT 24
Finished Apr 21 03:43:59 PM PDT 24
Peak memory 222952 kb
Host smart-54858dd4-c6f7-4c55-bdb2-dd835e68bd98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1853995076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1853995076 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.3911705385
Short name T879
Test name
Test status
Simulation time 13793386 ps
CPU time 0.85 seconds
Started Apr 21 03:43:58 PM PDT 24
Finished Apr 21 03:43:59 PM PDT 24
Peak memory 220308 kb
Host smart-a7e226a4-4a3a-4981-8273-88b86eb843c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3911705385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.3911705385 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.866319038
Short name T999
Test name
Test status
Simulation time 24680674027 ps
CPU time 91.03 seconds
Started Apr 21 03:43:57 PM PDT 24
Finished Apr 21 03:45:28 PM PDT 24
Peak memory 230836 kb
Host smart-1713c18f-a769-4701-8773-c4693dfd0412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866319038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.866319038 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.2433812356
Short name T498
Test name
Test status
Simulation time 10487991044 ps
CPU time 96.16 seconds
Started Apr 21 03:43:58 PM PDT 24
Finished Apr 21 03:45:35 PM PDT 24
Peak memory 243132 kb
Host smart-4241e2b0-45ed-448f-b415-cc91501a9184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433812356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2433812356 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3999768573
Short name T896
Test name
Test status
Simulation time 4038434459 ps
CPU time 7.69 seconds
Started Apr 21 03:44:00 PM PDT 24
Finished Apr 21 03:44:08 PM PDT 24
Peak memory 218468 kb
Host smart-7aaaa082-c913-4618-8618-246226db2a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999768573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3999768573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.1673500340
Short name T72
Test name
Test status
Simulation time 32237223 ps
CPU time 1.23 seconds
Started Apr 21 03:43:58 PM PDT 24
Finished Apr 21 03:44:00 PM PDT 24
Peak memory 218424 kb
Host smart-e3750048-fad6-43d3-870b-082a097d82d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673500340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1673500340 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3543823527
Short name T994
Test name
Test status
Simulation time 26424354661 ps
CPU time 1375.4 seconds
Started Apr 21 03:43:47 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 346872 kb
Host smart-c9a53685-611c-44f9-a5e1-4294272a9076
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543823527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3543823527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.2784983770
Short name T358
Test name
Test status
Simulation time 5434381109 ps
CPU time 160.18 seconds
Started Apr 21 03:43:47 PM PDT 24
Finished Apr 21 03:46:27 PM PDT 24
Peak memory 236212 kb
Host smart-88d6335e-42d9-4343-8d5d-b9b785302511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784983770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.2784983770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2733327823
Short name T9
Test name
Test status
Simulation time 27734243 ps
CPU time 1.33 seconds
Started Apr 21 03:43:47 PM PDT 24
Finished Apr 21 03:43:48 PM PDT 24
Peak memory 226512 kb
Host smart-03ca9053-6f5d-4b7d-aaba-91bf28983f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733327823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2733327823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1566600922
Short name T353
Test name
Test status
Simulation time 8933943758 ps
CPU time 189.12 seconds
Started Apr 21 03:44:04 PM PDT 24
Finished Apr 21 03:47:14 PM PDT 24
Peak memory 261076 kb
Host smart-5e22bac0-e10d-4de1-9f19-306a68c92d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1566600922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1566600922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_stress_all_with_rand_reset.744958775
Short name T132
Test name
Test status
Simulation time 83004518696 ps
CPU time 1419.14 seconds
Started Apr 21 03:44:01 PM PDT 24
Finished Apr 21 04:07:40 PM PDT 24
Peak memory 299892 kb
Host smart-ac636fd4-7cbd-4d7a-8375-67608731a628
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744958775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.744958775 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.2218408160
Short name T450
Test name
Test status
Simulation time 346115633 ps
CPU time 6.41 seconds
Started Apr 21 03:43:56 PM PDT 24
Finished Apr 21 03:44:03 PM PDT 24
Peak memory 218584 kb
Host smart-25d3cada-6f89-408b-8e30-1de0b36b56e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218408160 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.kmac_test_vectors_kmac.2218408160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.2877186609
Short name T876
Test name
Test status
Simulation time 202699284 ps
CPU time 6.07 seconds
Started Apr 21 03:43:56 PM PDT 24
Finished Apr 21 03:44:03 PM PDT 24
Peak memory 218564 kb
Host smart-16162313-02c7-47f6-ab8f-3db49ff24a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877186609 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.2877186609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.901126857
Short name T488
Test name
Test status
Simulation time 1660903521999 ps
CPU time 2287.8 seconds
Started Apr 21 03:43:50 PM PDT 24
Finished Apr 21 04:21:58 PM PDT 24
Peak memory 390268 kb
Host smart-d2c50bed-5c9b-493c-b95e-6bbf9f6c25b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=901126857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.901126857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3427447265
Short name T376
Test name
Test status
Simulation time 314002928797 ps
CPU time 2159.12 seconds
Started Apr 21 03:43:52 PM PDT 24
Finished Apr 21 04:19:51 PM PDT 24
Peak memory 379052 kb
Host smart-218927e1-71aa-4c30-9722-8841b1c4d64a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3427447265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3427447265 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.1084784324
Short name T384
Test name
Test status
Simulation time 15227777938 ps
CPU time 1478.43 seconds
Started Apr 21 03:43:53 PM PDT 24
Finished Apr 21 04:08:31 PM PDT 24
Peak memory 337160 kb
Host smart-6235af2f-9a84-4bdc-a88e-9f1fea81aec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1084784324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.1084784324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3563120292
Short name T497
Test name
Test status
Simulation time 64754419219 ps
CPU time 1189.24 seconds
Started Apr 21 03:43:53 PM PDT 24
Finished Apr 21 04:03:43 PM PDT 24
Peak memory 299324 kb
Host smart-b843453c-a965-4eb5-96c2-2a72f03b05e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3563120292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3563120292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.3159445785
Short name T393
Test name
Test status
Simulation time 60823006113 ps
CPU time 4945.18 seconds
Started Apr 21 03:43:55 PM PDT 24
Finished Apr 21 05:06:21 PM PDT 24
Peak memory 650472 kb
Host smart-7e498d51-2c2b-4844-9a6d-c01017d7847a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3159445785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3159445785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.631882165
Short name T328
Test name
Test status
Simulation time 52743177035 ps
CPU time 4862.87 seconds
Started Apr 21 03:43:57 PM PDT 24
Finished Apr 21 05:05:00 PM PDT 24
Peak memory 568616 kb
Host smart-023d9fbf-2b88-409f-99b1-1f5727be5c35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=631882165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.631882165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.120228809
Short name T14
Test name
Test status
Simulation time 16577903 ps
CPU time 0.81 seconds
Started Apr 21 03:35:37 PM PDT 24
Finished Apr 21 03:35:38 PM PDT 24
Peak memory 218328 kb
Host smart-7bed5f8e-88ca-4c7d-8287-3df765cee639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120228809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.120228809 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.2944520923
Short name T41
Test name
Test status
Simulation time 14297350633 ps
CPU time 334.2 seconds
Started Apr 21 03:35:17 PM PDT 24
Finished Apr 21 03:40:51 PM PDT 24
Peak memory 248932 kb
Host smart-f3295cfe-09c0-4455-a7d6-59c5215be5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944520923 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2944520923 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2900743129
Short name T476
Test name
Test status
Simulation time 20242173193 ps
CPU time 312.24 seconds
Started Apr 21 03:35:13 PM PDT 24
Finished Apr 21 03:40:25 PM PDT 24
Peak memory 248056 kb
Host smart-d5cc45aa-e843-419e-b5fb-ce22820d5a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900743129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2900743129 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.2076176390
Short name T526
Test name
Test status
Simulation time 14956401636 ps
CPU time 572.92 seconds
Started Apr 21 03:34:53 PM PDT 24
Finished Apr 21 03:44:27 PM PDT 24
Peak memory 233020 kb
Host smart-1c841474-d139-46ed-84fd-654bf46f03af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076176390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.2076176390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.1126280633
Short name T56
Test name
Test status
Simulation time 138567018 ps
CPU time 1.53 seconds
Started Apr 21 03:35:33 PM PDT 24
Finished Apr 21 03:35:35 PM PDT 24
Peak memory 218380 kb
Host smart-7e2f39c6-54f1-4b1b-837c-1d3e5569e4b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1126280633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1126280633 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.2396739856
Short name T120
Test name
Test status
Simulation time 181216424 ps
CPU time 11.83 seconds
Started Apr 21 03:35:24 PM PDT 24
Finished Apr 21 03:35:36 PM PDT 24
Peak memory 226468 kb
Host smart-18fd3a60-b56b-408b-abbd-a4227384b20f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396739856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.2396739856 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.912712097
Short name T987
Test name
Test status
Simulation time 51091070723 ps
CPU time 63.93 seconds
Started Apr 21 03:35:25 PM PDT 24
Finished Apr 21 03:36:30 PM PDT 24
Peak memory 220068 kb
Host smart-73dc1459-9798-475d-b44e-093ff848d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912712097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.912712097 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.3705540333
Short name T1025
Test name
Test status
Simulation time 3203736201 ps
CPU time 70.71 seconds
Started Apr 21 03:35:23 PM PDT 24
Finished Apr 21 03:36:34 PM PDT 24
Peak memory 230752 kb
Host smart-bcbaadb9-95d0-4c2f-a89f-84b2fc26dc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705540333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.3705540333 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.1332693678
Short name T306
Test name
Test status
Simulation time 27398860179 ps
CPU time 232.56 seconds
Started Apr 21 03:35:19 PM PDT 24
Finished Apr 21 03:39:12 PM PDT 24
Peak memory 251636 kb
Host smart-1247d661-c6b9-44fc-b157-f51f63d10c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332693678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1332693678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.3871178477
Short name T568
Test name
Test status
Simulation time 5050597236 ps
CPU time 3.7 seconds
Started Apr 21 03:35:20 PM PDT 24
Finished Apr 21 03:35:24 PM PDT 24
Peak memory 218540 kb
Host smart-934c1e3f-5139-46d1-a6aa-2e26103233f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871178477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3871178477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.4220855953
Short name T39
Test name
Test status
Simulation time 45101897 ps
CPU time 1.47 seconds
Started Apr 21 03:35:29 PM PDT 24
Finished Apr 21 03:35:31 PM PDT 24
Peak memory 218352 kb
Host smart-582d6498-4a54-4e53-b915-a85a8aec39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220855953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.4220855953 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.2538749175
Short name T518
Test name
Test status
Simulation time 46245699506 ps
CPU time 2694.39 seconds
Started Apr 21 03:34:52 PM PDT 24
Finished Apr 21 04:19:47 PM PDT 24
Peak memory 454268 kb
Host smart-f6281bcb-4a9a-4a60-bc74-d2ea8abfff4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538749175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.2538749175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.3061043240
Short name T623
Test name
Test status
Simulation time 163010146267 ps
CPU time 412.99 seconds
Started Apr 21 03:35:17 PM PDT 24
Finished Apr 21 03:42:10 PM PDT 24
Peak memory 249924 kb
Host smart-0763ce2f-c854-400e-8b37-ec668e36046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061043240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3061043240 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.2570160811
Short name T20
Test name
Test status
Simulation time 4947342629 ps
CPU time 45.72 seconds
Started Apr 21 03:35:36 PM PDT 24
Finished Apr 21 03:36:23 PM PDT 24
Peak memory 255464 kb
Host smart-ffe45416-46b4-46d3-8f10-9992fcd9857d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570160811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.2570160811 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.137886974
Short name T923
Test name
Test status
Simulation time 108673976107 ps
CPU time 581.06 seconds
Started Apr 21 03:35:01 PM PDT 24
Finished Apr 21 03:44:42 PM PDT 24
Peak memory 258080 kb
Host smart-8768fd93-5e8b-4b3b-a803-c05dbbcb8cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137886974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.137886974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.150133744
Short name T579
Test name
Test status
Simulation time 7724744162 ps
CPU time 46.91 seconds
Started Apr 21 03:34:58 PM PDT 24
Finished Apr 21 03:35:45 PM PDT 24
Peak memory 226660 kb
Host smart-ce9de1d9-cf75-4060-ba90-8a188fc65c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150133744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.150133744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.3345461363
Short name T143
Test name
Test status
Simulation time 16512751545 ps
CPU time 1251.97 seconds
Started Apr 21 03:35:27 PM PDT 24
Finished Apr 21 03:56:19 PM PDT 24
Peak memory 333248 kb
Host smart-9650fbfb-c198-4259-bd86-b159f2fa54fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3345461363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.3345461363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.1029899480
Short name T646
Test name
Test status
Simulation time 535850094 ps
CPU time 7.34 seconds
Started Apr 21 03:35:12 PM PDT 24
Finished Apr 21 03:35:20 PM PDT 24
Peak memory 218520 kb
Host smart-4146f72c-2975-42d9-8450-1da4f3978a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029899480 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.kmac_test_vectors_kmac.1029899480 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3419594253
Short name T827
Test name
Test status
Simulation time 445670787 ps
CPU time 7.32 seconds
Started Apr 21 03:35:26 PM PDT 24
Finished Apr 21 03:35:33 PM PDT 24
Peak memory 219536 kb
Host smart-2170dc55-e11c-4d4d-987c-2defddc42d0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419594253 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3419594253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.2512098519
Short name T596
Test name
Test status
Simulation time 349247797452 ps
CPU time 2355.27 seconds
Started Apr 21 03:34:56 PM PDT 24
Finished Apr 21 04:14:12 PM PDT 24
Peak memory 393400 kb
Host smart-17865f64-0143-448c-accb-9d8fc499878e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2512098519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.2512098519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.248742304
Short name T362
Test name
Test status
Simulation time 79624040206 ps
CPU time 1991.64 seconds
Started Apr 21 03:34:57 PM PDT 24
Finished Apr 21 04:08:09 PM PDT 24
Peak memory 385488 kb
Host smart-d4854405-9dbf-459b-b58d-911bb0919065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=248742304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.248742304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.287990800
Short name T592
Test name
Test status
Simulation time 404544581076 ps
CPU time 1869.13 seconds
Started Apr 21 03:34:57 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 344656 kb
Host smart-3f594b00-747d-4074-9640-9611ddc87be7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=287990800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.287990800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1657750862
Short name T1021
Test name
Test status
Simulation time 104587289460 ps
CPU time 1204.01 seconds
Started Apr 21 03:35:03 PM PDT 24
Finished Apr 21 03:55:08 PM PDT 24
Peak memory 300232 kb
Host smart-024e0bad-0f09-4b9e-a150-49d026dc841f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1657750862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1657750862 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.423065876
Short name T694
Test name
Test status
Simulation time 61622408993 ps
CPU time 5204.53 seconds
Started Apr 21 03:34:59 PM PDT 24
Finished Apr 21 05:01:44 PM PDT 24
Peak memory 673036 kb
Host smart-bf01d6e8-bfb7-41b3-a428-a9a5d0b4bcdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=423065876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.423065876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.961020082
Short name T533
Test name
Test status
Simulation time 57043060217 ps
CPU time 4707.15 seconds
Started Apr 21 03:35:01 PM PDT 24
Finished Apr 21 04:53:29 PM PDT 24
Peak memory 576204 kb
Host smart-25bd4108-12d0-4eba-8ab1-5211969a1496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=961020082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.961020082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_app.1551951976
Short name T1007
Test name
Test status
Simulation time 52010097341 ps
CPU time 400.01 seconds
Started Apr 21 03:44:19 PM PDT 24
Finished Apr 21 03:50:59 PM PDT 24
Peak memory 251484 kb
Host smart-bb3dad4d-6e9a-4939-a422-74f2aeb7faf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551951976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.1551951976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2222255256
Short name T199
Test name
Test status
Simulation time 19486037986 ps
CPU time 205.4 seconds
Started Apr 21 03:44:08 PM PDT 24
Finished Apr 21 03:47:34 PM PDT 24
Peak memory 228212 kb
Host smart-b60e5ce2-5e70-4e5b-9a2e-d0b78b7a412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222255256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2222255256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.877973580
Short name T750
Test name
Test status
Simulation time 3929317459 ps
CPU time 140.54 seconds
Started Apr 21 03:44:16 PM PDT 24
Finished Apr 21 03:46:37 PM PDT 24
Peak memory 236324 kb
Host smart-755231c3-d372-42a6-9dbf-fdcd943d2980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877973580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.877973580 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.4150394637
Short name T918
Test name
Test status
Simulation time 12154895104 ps
CPU time 89.03 seconds
Started Apr 21 03:44:19 PM PDT 24
Finished Apr 21 03:45:49 PM PDT 24
Peak memory 243012 kb
Host smart-679183d6-d5b7-469b-b777-7e5625b4e18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150394637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.4150394637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.1241556215
Short name T813
Test name
Test status
Simulation time 133627964 ps
CPU time 1.12 seconds
Started Apr 21 03:44:19 PM PDT 24
Finished Apr 21 03:44:20 PM PDT 24
Peak memory 218316 kb
Host smart-01b38895-3f49-4f2a-8b01-edde60530be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241556215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.1241556215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.794165900
Short name T905
Test name
Test status
Simulation time 26395759 ps
CPU time 1.27 seconds
Started Apr 21 03:44:18 PM PDT 24
Finished Apr 21 03:44:20 PM PDT 24
Peak memory 218376 kb
Host smart-049c8678-25d5-4ca3-945c-544a1c7e2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794165900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.794165900 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1346722309
Short name T470
Test name
Test status
Simulation time 66659750527 ps
CPU time 2465.56 seconds
Started Apr 21 03:44:03 PM PDT 24
Finished Apr 21 04:25:10 PM PDT 24
Peak memory 411272 kb
Host smart-ede4c38c-f27b-408d-9427-5e1fa71e63fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346722309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1346722309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1716515082
Short name T279
Test name
Test status
Simulation time 525897227 ps
CPU time 16.24 seconds
Started Apr 21 03:44:06 PM PDT 24
Finished Apr 21 03:44:22 PM PDT 24
Peak memory 226664 kb
Host smart-3356ef48-f174-4c9a-8a75-422ec805f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716515082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1716515082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.2142498317
Short name T340
Test name
Test status
Simulation time 1006419271 ps
CPU time 32.52 seconds
Started Apr 21 03:44:05 PM PDT 24
Finished Apr 21 03:44:38 PM PDT 24
Peak memory 226636 kb
Host smart-49a166d8-f422-4641-a336-770f1e0e42dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142498317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2142498317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2388142451
Short name T950
Test name
Test status
Simulation time 99215328504 ps
CPU time 753.48 seconds
Started Apr 21 03:44:20 PM PDT 24
Finished Apr 21 03:56:53 PM PDT 24
Peak memory 308908 kb
Host smart-55a88282-aa0c-40e3-97ad-648ffe1b10f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2388142451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2388142451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.1902947986
Short name T346
Test name
Test status
Simulation time 2687760493 ps
CPU time 6.49 seconds
Started Apr 21 03:44:14 PM PDT 24
Finished Apr 21 03:44:21 PM PDT 24
Peak memory 226696 kb
Host smart-487ef270-8783-46a6-a600-bb7b39a05768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902947986 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.1902947986 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.3175734531
Short name T617
Test name
Test status
Simulation time 502280743 ps
CPU time 5.78 seconds
Started Apr 21 03:44:16 PM PDT 24
Finished Apr 21 03:44:22 PM PDT 24
Peak memory 218600 kb
Host smart-252e979a-d9ce-498e-b2c5-4785565d39bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175734531 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.3175734531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.4179765241
Short name T885
Test name
Test status
Simulation time 70639542986 ps
CPU time 2123.26 seconds
Started Apr 21 03:44:08 PM PDT 24
Finished Apr 21 04:19:31 PM PDT 24
Peak memory 406156 kb
Host smart-aa50c405-b260-4910-8a67-49c8eeb94328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4179765241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.4179765241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.330939186
Short name T258
Test name
Test status
Simulation time 329022493870 ps
CPU time 2309.68 seconds
Started Apr 21 03:44:11 PM PDT 24
Finished Apr 21 04:22:41 PM PDT 24
Peak memory 383268 kb
Host smart-82216baf-e39f-465d-9577-80fb3893e1c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=330939186 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.330939186 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.2324005959
Short name T386
Test name
Test status
Simulation time 298935760969 ps
CPU time 1996.28 seconds
Started Apr 21 03:44:14 PM PDT 24
Finished Apr 21 04:17:31 PM PDT 24
Peak memory 344368 kb
Host smart-d2ac1b19-7592-4369-9c9b-90f858c0c6ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2324005959 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.2324005959 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.501396723
Short name T241
Test name
Test status
Simulation time 211138167540 ps
CPU time 1396.94 seconds
Started Apr 21 03:44:14 PM PDT 24
Finished Apr 21 04:07:31 PM PDT 24
Peak memory 298252 kb
Host smart-bb442353-5db7-42c9-8885-adad345efdd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=501396723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.501396723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.767586150
Short name T411
Test name
Test status
Simulation time 569237974658 ps
CPU time 6150.07 seconds
Started Apr 21 03:44:14 PM PDT 24
Finished Apr 21 05:26:45 PM PDT 24
Peak memory 659048 kb
Host smart-c343a5d7-30fa-4172-b56c-f49308e5fabf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=767586150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.767586150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.1641872118
Short name T875
Test name
Test status
Simulation time 218450107858 ps
CPU time 5328.12 seconds
Started Apr 21 03:44:13 PM PDT 24
Finished Apr 21 05:13:02 PM PDT 24
Peak memory 558620 kb
Host smart-c76037f1-c78a-41c9-a275-987c110a72c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1641872118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.1641872118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1738045532
Short name T823
Test name
Test status
Simulation time 19625577 ps
CPU time 0.89 seconds
Started Apr 21 03:44:47 PM PDT 24
Finished Apr 21 03:44:48 PM PDT 24
Peak memory 220344 kb
Host smart-c8ff3c9c-aeb7-4c00-8a49-63e02403bd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738045532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1738045532 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.47143033
Short name T391
Test name
Test status
Simulation time 5630380261 ps
CPU time 167.77 seconds
Started Apr 21 03:44:36 PM PDT 24
Finished Apr 21 03:47:24 PM PDT 24
Peak memory 238476 kb
Host smart-58ae9fd4-7be4-47df-99a6-f69383f4b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47143033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.47143033 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.2029937451
Short name T897
Test name
Test status
Simulation time 37374512146 ps
CPU time 1413.29 seconds
Started Apr 21 03:44:30 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 238084 kb
Host smart-97230297-29de-4bfb-8cc8-c8ca48947771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029937451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.2029937451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.1986893636
Short name T583
Test name
Test status
Simulation time 14913010499 ps
CPU time 390.61 seconds
Started Apr 21 03:44:36 PM PDT 24
Finished Apr 21 03:51:07 PM PDT 24
Peak memory 251384 kb
Host smart-9162122b-85bb-4110-9c5c-4df8b92da5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986893636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.1986893636 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.1274995160
Short name T390
Test name
Test status
Simulation time 2093938662 ps
CPU time 177.21 seconds
Started Apr 21 03:44:35 PM PDT 24
Finished Apr 21 03:47:32 PM PDT 24
Peak memory 259328 kb
Host smart-bf536697-a906-4933-92b1-dd6799b39131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274995160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1274995160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.1476115416
Short name T31
Test name
Test status
Simulation time 741028558 ps
CPU time 1.71 seconds
Started Apr 21 03:44:38 PM PDT 24
Finished Apr 21 03:44:40 PM PDT 24
Peak memory 218452 kb
Host smart-94f11117-801a-40ba-b5b5-d939623683fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476115416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.1476115416 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.3877983727
Short name T119
Test name
Test status
Simulation time 30170317 ps
CPU time 1.36 seconds
Started Apr 21 03:44:46 PM PDT 24
Finished Apr 21 03:44:48 PM PDT 24
Peak memory 218404 kb
Host smart-44943650-ce85-4e23-8b3d-bfacf49ec553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877983727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.3877983727 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_sideload.2089236107
Short name T84
Test name
Test status
Simulation time 4195342106 ps
CPU time 301.39 seconds
Started Apr 21 03:44:27 PM PDT 24
Finished Apr 21 03:49:29 PM PDT 24
Peak memory 247600 kb
Host smart-cda8a662-74b7-4d62-ac4e-b3bf060ade67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089236107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2089236107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.3071060162
Short name T1018
Test name
Test status
Simulation time 1818067801 ps
CPU time 22.79 seconds
Started Apr 21 03:44:25 PM PDT 24
Finished Apr 21 03:44:48 PM PDT 24
Peak memory 223088 kb
Host smart-717b8249-9e2d-4b69-a570-5ecab19c8f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071060162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3071060162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.3657891834
Short name T456
Test name
Test status
Simulation time 16215380230 ps
CPU time 76.81 seconds
Started Apr 21 03:44:45 PM PDT 24
Finished Apr 21 03:46:02 PM PDT 24
Peak memory 241216 kb
Host smart-0a6b8d77-88d3-4472-800e-8fd5a0e7c5ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3657891834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.3657891834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.445398773
Short name T597
Test name
Test status
Simulation time 878215421 ps
CPU time 6.64 seconds
Started Apr 21 03:44:34 PM PDT 24
Finished Apr 21 03:44:42 PM PDT 24
Peak memory 226636 kb
Host smart-df76020f-f691-41e6-a183-13a609abf6cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445398773 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.kmac_test_vectors_kmac.445398773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.2166027211
Short name T794
Test name
Test status
Simulation time 551498696 ps
CPU time 7.19 seconds
Started Apr 21 03:44:37 PM PDT 24
Finished Apr 21 03:44:44 PM PDT 24
Peak memory 218548 kb
Host smart-7a8b1fd9-d6a5-445e-8c71-b984b8a3c946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166027211 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.2166027211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1632026656
Short name T689
Test name
Test status
Simulation time 85907694237 ps
CPU time 2317.51 seconds
Started Apr 21 03:44:30 PM PDT 24
Finished Apr 21 04:23:08 PM PDT 24
Peak memory 396092 kb
Host smart-72c6bc68-3eb2-48af-bfb5-8c7f682f09d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1632026656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1632026656 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2584209882
Short name T679
Test name
Test status
Simulation time 340887528795 ps
CPU time 2171.93 seconds
Started Apr 21 03:44:29 PM PDT 24
Finished Apr 21 04:20:42 PM PDT 24
Peak memory 381628 kb
Host smart-ada300ad-6837-4217-b279-3e0bb4e59a9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2584209882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2584209882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.340978603
Short name T669
Test name
Test status
Simulation time 29847283228 ps
CPU time 1549.58 seconds
Started Apr 21 03:44:33 PM PDT 24
Finished Apr 21 04:10:23 PM PDT 24
Peak memory 337328 kb
Host smart-6a4732fe-ba8c-46f4-8798-8c232106bde4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=340978603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.340978603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.3074353554
Short name T611
Test name
Test status
Simulation time 88037386904 ps
CPU time 1218.66 seconds
Started Apr 21 03:44:33 PM PDT 24
Finished Apr 21 04:04:52 PM PDT 24
Peak memory 298436 kb
Host smart-57242164-d55d-4fe5-a797-587146a303ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3074353554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3074353554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.963755457
Short name T418
Test name
Test status
Simulation time 563619584314 ps
CPU time 6865.33 seconds
Started Apr 21 03:44:34 PM PDT 24
Finished Apr 21 05:39:00 PM PDT 24
Peak memory 657048 kb
Host smart-75227f4d-077a-4da7-8df3-195290ab883c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=963755457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.963755457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.1871491150
Short name T212
Test name
Test status
Simulation time 1491888757573 ps
CPU time 5406.5 seconds
Started Apr 21 03:44:33 PM PDT 24
Finished Apr 21 05:14:41 PM PDT 24
Peak memory 568640 kb
Host smart-24eafdce-8d1e-458c-8def-2fcbc98d8ad7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1871491150 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.1871491150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.1609737155
Short name T193
Test name
Test status
Simulation time 30639636 ps
CPU time 0.88 seconds
Started Apr 21 03:45:07 PM PDT 24
Finished Apr 21 03:45:08 PM PDT 24
Peak memory 218340 kb
Host smart-00000f17-1e4e-41ed-8081-70793154c0b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609737155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.1609737155 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.541500132
Short name T659
Test name
Test status
Simulation time 9537154383 ps
CPU time 237.13 seconds
Started Apr 21 03:44:57 PM PDT 24
Finished Apr 21 03:48:55 PM PDT 24
Peak memory 244156 kb
Host smart-746b2e50-24b9-4b7d-ab5e-9c7939fc64c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541500132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.541500132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1792862175
Short name T561
Test name
Test status
Simulation time 14002456671 ps
CPU time 684.43 seconds
Started Apr 21 03:44:53 PM PDT 24
Finished Apr 21 03:56:18 PM PDT 24
Peak memory 234636 kb
Host smart-5a4b941c-a938-48c2-bde5-04603788b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792862175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1792862175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.368290949
Short name T809
Test name
Test status
Simulation time 12412040022 ps
CPU time 193.39 seconds
Started Apr 21 03:45:02 PM PDT 24
Finished Apr 21 03:48:15 PM PDT 24
Peak memory 241736 kb
Host smart-6df50483-4f74-47db-aa1b-f6382eec1dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368290949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.368290949 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3534187405
Short name T261
Test name
Test status
Simulation time 18298065356 ps
CPU time 479.15 seconds
Started Apr 21 03:45:04 PM PDT 24
Finished Apr 21 03:53:03 PM PDT 24
Peak memory 257204 kb
Host smart-0e56517e-c1cb-47a5-baf7-bd692d839b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534187405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3534187405 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1136222715
Short name T603
Test name
Test status
Simulation time 2598554989 ps
CPU time 4.89 seconds
Started Apr 21 03:45:03 PM PDT 24
Finished Apr 21 03:45:08 PM PDT 24
Peak memory 218444 kb
Host smart-fc7c5d5d-2cc3-4103-a791-d3f4b8f31b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136222715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1136222715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3068387342
Short name T464
Test name
Test status
Simulation time 13436318152 ps
CPU time 215.39 seconds
Started Apr 21 03:44:53 PM PDT 24
Finished Apr 21 03:48:29 PM PDT 24
Peak memory 243032 kb
Host smart-ef217f94-8af2-45d9-9e9a-9e97ac5d7251
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068387342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3068387342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2753375094
Short name T1069
Test name
Test status
Simulation time 12776981502 ps
CPU time 311.21 seconds
Started Apr 21 03:44:52 PM PDT 24
Finished Apr 21 03:50:03 PM PDT 24
Peak memory 246060 kb
Host smart-5405ad32-d597-4b68-a158-fe741d0ca7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753375094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2753375094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.1039049770
Short name T937
Test name
Test status
Simulation time 1811286832 ps
CPU time 66.71 seconds
Started Apr 21 03:44:50 PM PDT 24
Finished Apr 21 03:45:57 PM PDT 24
Peak memory 226596 kb
Host smart-6a1daba2-eea3-4983-a216-0a8871b8cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039049770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.1039049770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.1174110920
Short name T311
Test name
Test status
Simulation time 3538815279 ps
CPU time 161.89 seconds
Started Apr 21 03:45:06 PM PDT 24
Finished Apr 21 03:47:48 PM PDT 24
Peak memory 251268 kb
Host smart-953c3254-2d91-43d6-b61d-714fdd943562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1174110920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.1174110920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1077412850
Short name T323
Test name
Test status
Simulation time 312460014 ps
CPU time 7.22 seconds
Started Apr 21 03:44:58 PM PDT 24
Finished Apr 21 03:45:05 PM PDT 24
Peak memory 226656 kb
Host smart-c89c3a69-0707-4451-854d-611dab3a4ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077412850 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1077412850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.3159155613
Short name T319
Test name
Test status
Simulation time 499937573 ps
CPU time 7.05 seconds
Started Apr 21 03:44:58 PM PDT 24
Finished Apr 21 03:45:05 PM PDT 24
Peak memory 218520 kb
Host smart-358ad606-db6b-4eba-8e92-21e6632cc424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159155613 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.3159155613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.3191925165
Short name T687
Test name
Test status
Simulation time 101584572609 ps
CPU time 2411.7 seconds
Started Apr 21 03:44:53 PM PDT 24
Finished Apr 21 04:25:06 PM PDT 24
Peak memory 396396 kb
Host smart-ec7f6dc5-609a-406b-8e95-2a9c5772a206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3191925165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3191925165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.966167881
Short name T829
Test name
Test status
Simulation time 1287173075251 ps
CPU time 2277.5 seconds
Started Apr 21 03:44:52 PM PDT 24
Finished Apr 21 04:22:50 PM PDT 24
Peak memory 380456 kb
Host smart-754b61e2-48bc-460f-bb0d-6362bb322a22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=966167881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.966167881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.2062428632
Short name T756
Test name
Test status
Simulation time 61684024138 ps
CPU time 1789.21 seconds
Started Apr 21 03:44:52 PM PDT 24
Finished Apr 21 04:14:42 PM PDT 24
Peak memory 342716 kb
Host smart-3601ee15-4aad-4b23-b23c-7e5df758b789
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2062428632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.2062428632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.1733475736
Short name T934
Test name
Test status
Simulation time 206353958958 ps
CPU time 1442.2 seconds
Started Apr 21 03:44:55 PM PDT 24
Finished Apr 21 04:08:57 PM PDT 24
Peak memory 301948 kb
Host smart-e738019d-ccf7-4e49-b56a-87d039c6bf40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1733475736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1733475736 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1612532576
Short name T727
Test name
Test status
Simulation time 271039923261 ps
CPU time 5929.01 seconds
Started Apr 21 03:44:57 PM PDT 24
Finished Apr 21 05:23:47 PM PDT 24
Peak memory 658196 kb
Host smart-b618156f-0758-4553-abf4-d796404de86f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1612532576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1612532576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1521766584
Short name T1060
Test name
Test status
Simulation time 106333246179 ps
CPU time 4405.35 seconds
Started Apr 21 03:44:58 PM PDT 24
Finished Apr 21 04:58:24 PM PDT 24
Peak memory 570348 kb
Host smart-132bbff8-49c8-4a70-93e9-d37d70bdada1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1521766584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1521766584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.3029962977
Short name T900
Test name
Test status
Simulation time 15498701 ps
CPU time 0.82 seconds
Started Apr 21 03:45:22 PM PDT 24
Finished Apr 21 03:45:23 PM PDT 24
Peak memory 220356 kb
Host smart-3ca9643b-854a-420b-a59c-ea5bc55846bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029962977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.3029962977 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.4186741010
Short name T736
Test name
Test status
Simulation time 4001798116 ps
CPU time 255.62 seconds
Started Apr 21 03:45:18 PM PDT 24
Finished Apr 21 03:49:33 PM PDT 24
Peak memory 246212 kb
Host smart-093b3326-094c-483f-b393-2d5cc03c93a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186741010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.4186741010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.4134287108
Short name T425
Test name
Test status
Simulation time 4138307322 ps
CPU time 391.89 seconds
Started Apr 21 03:45:13 PM PDT 24
Finished Apr 21 03:51:45 PM PDT 24
Peak memory 230272 kb
Host smart-212e2b15-84f6-4c48-a9db-974ec943accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134287108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.4134287108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.200507805
Short name T743
Test name
Test status
Simulation time 2407937734 ps
CPU time 65.25 seconds
Started Apr 21 03:45:21 PM PDT 24
Finished Apr 21 03:46:26 PM PDT 24
Peak memory 229732 kb
Host smart-eebdaf91-e1f6-4c82-a78a-00259335068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200507805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.200507805 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3827740333
Short name T1082
Test name
Test status
Simulation time 8777850160 ps
CPU time 523.23 seconds
Started Apr 21 03:45:21 PM PDT 24
Finished Apr 21 03:54:05 PM PDT 24
Peak memory 268312 kb
Host smart-19ca2749-6e51-495f-9425-766d7464d0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827740333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3827740333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.793242849
Short name T653
Test name
Test status
Simulation time 797893726 ps
CPU time 4.58 seconds
Started Apr 21 03:45:20 PM PDT 24
Finished Apr 21 03:45:25 PM PDT 24
Peak memory 218404 kb
Host smart-ba865a73-23f3-4a4d-98ef-08f473e9fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793242849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.793242849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.4157424937
Short name T44
Test name
Test status
Simulation time 157595239 ps
CPU time 1.54 seconds
Started Apr 21 03:45:22 PM PDT 24
Finished Apr 21 03:45:24 PM PDT 24
Peak memory 218440 kb
Host smart-bf5c0fdd-d98b-4e19-a8fb-70ca4aaecfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157424937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.4157424937 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.1825847640
Short name T195
Test name
Test status
Simulation time 35411114921 ps
CPU time 2002.88 seconds
Started Apr 21 03:45:09 PM PDT 24
Finished Apr 21 04:18:33 PM PDT 24
Peak memory 392744 kb
Host smart-b9eb5a41-fc1a-4344-b407-30a367b13bb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825847640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.1825847640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.3285118578
Short name T1066
Test name
Test status
Simulation time 138607107600 ps
CPU time 482.31 seconds
Started Apr 21 03:45:12 PM PDT 24
Finished Apr 21 03:53:14 PM PDT 24
Peak memory 254116 kb
Host smart-95fb947a-3d8c-4088-b656-76e14ddfb84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285118578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.3285118578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.555575947
Short name T699
Test name
Test status
Simulation time 29755192719 ps
CPU time 49.41 seconds
Started Apr 21 03:45:09 PM PDT 24
Finished Apr 21 03:45:59 PM PDT 24
Peak memory 218612 kb
Host smart-2aab128d-b6d4-406d-884c-d824ebd253a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555575947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.555575947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3144438851
Short name T1014
Test name
Test status
Simulation time 30174317761 ps
CPU time 628.53 seconds
Started Apr 21 03:45:23 PM PDT 24
Finished Apr 21 03:55:52 PM PDT 24
Peak memory 282156 kb
Host smart-da6ceb92-7c4b-42c4-b9ec-58698817c5ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3144438851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3144438851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_stress_all_with_rand_reset.4244405602
Short name T135
Test name
Test status
Simulation time 52221992609 ps
CPU time 2556.17 seconds
Started Apr 21 03:45:25 PM PDT 24
Finished Apr 21 04:28:02 PM PDT 24
Peak memory 400360 kb
Host smart-427fd565-b76d-4b0d-869d-b11c865d0f57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4244405602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all_with_rand_reset.4244405602 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1663820660
Short name T864
Test name
Test status
Simulation time 76964877 ps
CPU time 5.87 seconds
Started Apr 21 03:45:15 PM PDT 24
Finished Apr 21 03:45:21 PM PDT 24
Peak memory 226704 kb
Host smart-1412e2f5-6364-4a1b-9052-af5457bf0fbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663820660 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1663820660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1956903451
Short name T421
Test name
Test status
Simulation time 492627870 ps
CPU time 6.91 seconds
Started Apr 21 03:45:17 PM PDT 24
Finished Apr 21 03:45:24 PM PDT 24
Peak memory 219556 kb
Host smart-54060c20-f1c3-4abd-b8c3-d110dbe65de0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956903451 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1956903451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.372978283
Short name T1078
Test name
Test status
Simulation time 101363139732 ps
CPU time 2161.19 seconds
Started Apr 21 03:45:10 PM PDT 24
Finished Apr 21 04:21:12 PM PDT 24
Peak memory 398680 kb
Host smart-bde2d1b0-48eb-4aa4-9b2c-399978a93b37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=372978283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.372978283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.2279319429
Short name T477
Test name
Test status
Simulation time 65304535888 ps
CPU time 2087.41 seconds
Started Apr 21 03:45:12 PM PDT 24
Finished Apr 21 04:20:00 PM PDT 24
Peak memory 387088 kb
Host smart-f382c6d8-0ce8-40a3-8910-4ec4ffa719c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2279319429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.2279319429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2069923970
Short name T354
Test name
Test status
Simulation time 72722834479 ps
CPU time 1746.81 seconds
Started Apr 21 03:45:12 PM PDT 24
Finished Apr 21 04:14:19 PM PDT 24
Peak memory 339328 kb
Host smart-f0bc6185-b9d0-4d4b-ad72-8a8e05e00813
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2069923970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2069923970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.3551358880
Short name T438
Test name
Test status
Simulation time 66916973005 ps
CPU time 1295.75 seconds
Started Apr 21 03:45:11 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 299532 kb
Host smart-68d084a7-85b9-4632-a8db-3d8a2f58897e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3551358880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.3551358880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3495917292
Short name T963
Test name
Test status
Simulation time 62586711684 ps
CPU time 5201.08 seconds
Started Apr 21 03:45:15 PM PDT 24
Finished Apr 21 05:11:57 PM PDT 24
Peak memory 651660 kb
Host smart-26c145d6-b02a-4214-a9a2-226c06b24a2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3495917292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3495917292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.488370596
Short name T188
Test name
Test status
Simulation time 809265230776 ps
CPU time 5289.87 seconds
Started Apr 21 03:45:15 PM PDT 24
Finished Apr 21 05:13:26 PM PDT 24
Peak memory 581120 kb
Host smart-a5c0f46a-b5c6-484e-ab99-43809b343768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=488370596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.488370596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.711977461
Short name T858
Test name
Test status
Simulation time 13469162 ps
CPU time 0.83 seconds
Started Apr 21 03:45:46 PM PDT 24
Finished Apr 21 03:45:47 PM PDT 24
Peak memory 218340 kb
Host smart-5a9dd8b2-902e-4a5d-b0c0-f2c0f62b4a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711977461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.711977461 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.1825421819
Short name T737
Test name
Test status
Simulation time 1235486663 ps
CPU time 8.71 seconds
Started Apr 21 03:45:42 PM PDT 24
Finished Apr 21 03:45:52 PM PDT 24
Peak memory 219436 kb
Host smart-f6df5c84-8823-4df2-bbfa-cea1a1f13365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825421819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1825421819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.4167810709
Short name T552
Test name
Test status
Simulation time 36527710396 ps
CPU time 1389.2 seconds
Started Apr 21 03:45:35 PM PDT 24
Finished Apr 21 04:08:45 PM PDT 24
Peak memory 238232 kb
Host smart-4f3b18bd-df4d-4e9c-9d8e-217fa151a849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167810709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.4167810709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.3549292010
Short name T662
Test name
Test status
Simulation time 8498515196 ps
CPU time 131.85 seconds
Started Apr 21 03:45:43 PM PDT 24
Finished Apr 21 03:47:55 PM PDT 24
Peak memory 233880 kb
Host smart-b273f70f-0c75-440c-8b25-a940da0d18c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549292010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.3549292010 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.3331265087
Short name T300
Test name
Test status
Simulation time 41935744592 ps
CPU time 285 seconds
Started Apr 21 03:45:42 PM PDT 24
Finished Apr 21 03:50:27 PM PDT 24
Peak memory 254760 kb
Host smart-75f72087-248f-42ae-9171-592c7bce5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331265087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3331265087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1206854900
Short name T28
Test name
Test status
Simulation time 3037302028 ps
CPU time 4.75 seconds
Started Apr 21 03:45:41 PM PDT 24
Finished Apr 21 03:45:46 PM PDT 24
Peak memory 218520 kb
Host smart-969708e0-cd6d-472f-840c-2968fd094035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206854900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1206854900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2458633334
Short name T111
Test name
Test status
Simulation time 46588447 ps
CPU time 1.52 seconds
Started Apr 21 03:45:44 PM PDT 24
Finished Apr 21 03:45:46 PM PDT 24
Peak memory 219392 kb
Host smart-c717fa95-50af-45ef-8592-ec92bb151b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458633334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2458633334 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_sideload.1910481012
Short name T244
Test name
Test status
Simulation time 3448713433 ps
CPU time 293.54 seconds
Started Apr 21 03:45:37 PM PDT 24
Finished Apr 21 03:50:31 PM PDT 24
Peak memory 245576 kb
Host smart-bd8076c5-b037-4a4f-bc8c-d0e8b814f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910481012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.1910481012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.2179417292
Short name T645
Test name
Test status
Simulation time 2279367457 ps
CPU time 22.41 seconds
Started Apr 21 03:45:25 PM PDT 24
Finished Apr 21 03:45:48 PM PDT 24
Peak memory 226724 kb
Host smart-7c05ce1e-49b2-4998-b7f6-7da147ab33f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179417292 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.2179417292 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.1690400552
Short name T423
Test name
Test status
Simulation time 6123979424 ps
CPU time 519.62 seconds
Started Apr 21 03:45:44 PM PDT 24
Finished Apr 21 03:54:24 PM PDT 24
Peak memory 302300 kb
Host smart-33d3c5b3-ecd1-49c5-8080-ae1ad8e48b53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1690400552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.1690400552 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.1236743450
Short name T75
Test name
Test status
Simulation time 114752371 ps
CPU time 6.04 seconds
Started Apr 21 03:45:37 PM PDT 24
Finished Apr 21 03:45:43 PM PDT 24
Peak memory 226616 kb
Host smart-24b86067-8d2a-477e-95e7-f67e55696aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236743450 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.1236743450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.948608426
Short name T582
Test name
Test status
Simulation time 204998299 ps
CPU time 5.99 seconds
Started Apr 21 03:45:40 PM PDT 24
Finished Apr 21 03:45:46 PM PDT 24
Peak memory 219504 kb
Host smart-55541ae0-1db8-4ae6-94b3-914b91151301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948608426 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.948608426 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2702519277
Short name T216
Test name
Test status
Simulation time 85334432183 ps
CPU time 2300.24 seconds
Started Apr 21 03:45:34 PM PDT 24
Finished Apr 21 04:23:55 PM PDT 24
Peak memory 407956 kb
Host smart-be986af4-8ced-4e24-b714-f7f22a5d22aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2702519277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2702519277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.3074084493
Short name T674
Test name
Test status
Simulation time 1035369527994 ps
CPU time 2366.49 seconds
Started Apr 21 03:45:36 PM PDT 24
Finished Apr 21 04:25:03 PM PDT 24
Peak memory 387976 kb
Host smart-28a8d2eb-8512-40b5-8c04-468332109fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3074084493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.3074084493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.93694827
Short name T457
Test name
Test status
Simulation time 201026532335 ps
CPU time 1753.3 seconds
Started Apr 21 03:45:36 PM PDT 24
Finished Apr 21 04:14:50 PM PDT 24
Peak memory 344020 kb
Host smart-6c9b43be-de1d-43fd-bca2-6b8cc1b446f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=93694827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.93694827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.892594065
Short name T246
Test name
Test status
Simulation time 34246062514 ps
CPU time 1288.16 seconds
Started Apr 21 03:45:37 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 302472 kb
Host smart-b19eed6b-0d3f-4455-8702-e4891fe1c7b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=892594065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.892594065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.183592427
Short name T841
Test name
Test status
Simulation time 239612688545 ps
CPU time 5214.94 seconds
Started Apr 21 03:45:37 PM PDT 24
Finished Apr 21 05:12:33 PM PDT 24
Peak memory 647016 kb
Host smart-eed8707a-6051-4cb9-9ef4-f197f6e5cd11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=183592427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.183592427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1027308530
Short name T899
Test name
Test status
Simulation time 808629852400 ps
CPU time 5448.67 seconds
Started Apr 21 03:45:37 PM PDT 24
Finished Apr 21 05:16:26 PM PDT 24
Peak memory 575284 kb
Host smart-3385eedc-1bd9-4725-9a71-2e92024c2808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1027308530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1027308530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1793460616
Short name T594
Test name
Test status
Simulation time 14224376 ps
CPU time 0.81 seconds
Started Apr 21 03:46:00 PM PDT 24
Finished Apr 21 03:46:01 PM PDT 24
Peak memory 218340 kb
Host smart-41d6c7e5-beff-4f34-a5e2-c0f07ae00ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793460616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1793460616 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_burst_write.3647202892
Short name T372
Test name
Test status
Simulation time 6502247649 ps
CPU time 283.35 seconds
Started Apr 21 03:45:55 PM PDT 24
Finished Apr 21 03:50:39 PM PDT 24
Peak memory 237092 kb
Host smart-3358c2af-d559-44b2-b485-9af297963b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647202892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3647202892 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.852915360
Short name T634
Test name
Test status
Simulation time 36411035429 ps
CPU time 197.45 seconds
Started Apr 21 03:45:57 PM PDT 24
Finished Apr 21 03:49:15 PM PDT 24
Peak memory 239960 kb
Host smart-c7d9f0ed-3385-4e04-8bbf-360fb51d3414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852915360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.852915360 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.1754762637
Short name T621
Test name
Test status
Simulation time 4095497974 ps
CPU time 51.32 seconds
Started Apr 21 03:45:56 PM PDT 24
Finished Apr 21 03:46:48 PM PDT 24
Peak memory 243084 kb
Host smart-ba4a759e-129b-4519-a340-099ff774b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754762637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1754762637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.4036565125
Short name T658
Test name
Test status
Simulation time 1492018485 ps
CPU time 2.79 seconds
Started Apr 21 03:45:56 PM PDT 24
Finished Apr 21 03:45:59 PM PDT 24
Peak memory 218448 kb
Host smart-461f7a4d-2c89-4153-b597-1a4072feebed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036565125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.4036565125 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.372657114
Short name T66
Test name
Test status
Simulation time 46851738 ps
CPU time 1.55 seconds
Started Apr 21 03:45:56 PM PDT 24
Finished Apr 21 03:45:58 PM PDT 24
Peak memory 219372 kb
Host smart-fc6d520b-afb8-41ec-8b5d-98d916aade4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372657114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.372657114 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.1630137021
Short name T313
Test name
Test status
Simulation time 87953661671 ps
CPU time 1727.93 seconds
Started Apr 21 03:45:51 PM PDT 24
Finished Apr 21 04:14:40 PM PDT 24
Peak memory 361580 kb
Host smart-fddb3288-12ef-46b0-94be-30fcff3460a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630137021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.1630137021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.3206511640
Short name T250
Test name
Test status
Simulation time 5615090898 ps
CPU time 191.59 seconds
Started Apr 21 03:45:52 PM PDT 24
Finished Apr 21 03:49:04 PM PDT 24
Peak memory 238332 kb
Host smart-3a3b3c14-2899-466d-aea2-14a4f1454979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206511640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.3206511640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.2864447034
Short name T396
Test name
Test status
Simulation time 2506239250 ps
CPU time 13.92 seconds
Started Apr 21 03:45:44 PM PDT 24
Finished Apr 21 03:45:58 PM PDT 24
Peak memory 218632 kb
Host smart-7d048bd4-0391-43f0-a782-f3e40384036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864447034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.2864447034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.930870995
Short name T521
Test name
Test status
Simulation time 36009980548 ps
CPU time 1075.32 seconds
Started Apr 21 03:45:58 PM PDT 24
Finished Apr 21 04:03:54 PM PDT 24
Peak memory 304180 kb
Host smart-4ca68b10-4b8f-46b3-8927-71694e7b0150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=930870995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.930870995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.1738122911
Short name T446
Test name
Test status
Simulation time 893426168 ps
CPU time 6.83 seconds
Started Apr 21 03:45:55 PM PDT 24
Finished Apr 21 03:46:02 PM PDT 24
Peak memory 218576 kb
Host smart-9d9633e7-c299-41e8-a61e-792a8e8b17e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738122911 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.1738122911 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.491238158
Short name T806
Test name
Test status
Simulation time 250341798 ps
CPU time 6.05 seconds
Started Apr 21 03:45:53 PM PDT 24
Finished Apr 21 03:46:00 PM PDT 24
Peak memory 218556 kb
Host smart-97d8875a-fe62-4836-ba19-caf80f1c659a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491238158 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.kmac_test_vectors_kmac_xof.491238158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.187187227
Short name T201
Test name
Test status
Simulation time 300420887811 ps
CPU time 2375.56 seconds
Started Apr 21 03:45:55 PM PDT 24
Finished Apr 21 04:25:31 PM PDT 24
Peak memory 402216 kb
Host smart-5f52c107-2314-4c02-826a-d47f515a9363
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=187187227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.187187227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.3541510340
Short name T927
Test name
Test status
Simulation time 93276575020 ps
CPU time 2041.88 seconds
Started Apr 21 03:45:54 PM PDT 24
Finished Apr 21 04:19:56 PM PDT 24
Peak memory 374740 kb
Host smart-d1816ac8-08dc-4d51-959e-ffb6b03c45a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3541510340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.3541510340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.419843766
Short name T784
Test name
Test status
Simulation time 199201585239 ps
CPU time 1734.26 seconds
Started Apr 21 03:45:54 PM PDT 24
Finished Apr 21 04:14:49 PM PDT 24
Peak memory 340452 kb
Host smart-60081071-f083-4d23-b2e2-3d7939cd5ff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=419843766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.419843766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.530258760
Short name T295
Test name
Test status
Simulation time 45619742872 ps
CPU time 1225.91 seconds
Started Apr 21 03:45:54 PM PDT 24
Finished Apr 21 04:06:21 PM PDT 24
Peak memory 299472 kb
Host smart-2baca732-e43c-4af2-ae6d-cae9a7ba30ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=530258760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.530258760 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.1075018673
Short name T317
Test name
Test status
Simulation time 236732670609 ps
CPU time 5196.21 seconds
Started Apr 21 03:45:54 PM PDT 24
Finished Apr 21 05:12:31 PM PDT 24
Peak memory 650784 kb
Host smart-c9e7105c-3b70-40bb-a53e-5660becc5833
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1075018673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.1075018673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.2822493949
Short name T920
Test name
Test status
Simulation time 1161169574125 ps
CPU time 5163.29 seconds
Started Apr 21 03:45:53 PM PDT 24
Finished Apr 21 05:11:57 PM PDT 24
Peak memory 570812 kb
Host smart-a13a0965-f80c-4b81-b48b-5dede1f9f48f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2822493949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2822493949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1543997141
Short name T767
Test name
Test status
Simulation time 49823531 ps
CPU time 0.84 seconds
Started Apr 21 03:46:17 PM PDT 24
Finished Apr 21 03:46:19 PM PDT 24
Peak memory 220320 kb
Host smart-86ea2b51-8f64-40f5-b816-efacf3439cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543997141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1543997141 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.1785296408
Short name T366
Test name
Test status
Simulation time 15518821766 ps
CPU time 234.7 seconds
Started Apr 21 03:46:15 PM PDT 24
Finished Apr 21 03:50:10 PM PDT 24
Peak memory 242900 kb
Host smart-4bb42a68-ece2-40a9-9c07-ee5e7b39005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785296408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1785296408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.2850179913
Short name T506
Test name
Test status
Simulation time 96078640727 ps
CPU time 1437.37 seconds
Started Apr 21 03:46:02 PM PDT 24
Finished Apr 21 04:10:00 PM PDT 24
Peak memory 243104 kb
Host smart-4e981822-4220-4159-920c-65682c2e7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850179913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2850179913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.176310813
Short name T252
Test name
Test status
Simulation time 1705234922 ps
CPU time 89.4 seconds
Started Apr 21 03:46:15 PM PDT 24
Finished Apr 21 03:47:44 PM PDT 24
Peak memory 231556 kb
Host smart-6671c02c-7cae-44ae-b579-d18855aa99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176310813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.176310813 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.2131817756
Short name T607
Test name
Test status
Simulation time 11316319947 ps
CPU time 264.39 seconds
Started Apr 21 03:46:17 PM PDT 24
Finished Apr 21 03:50:42 PM PDT 24
Peak memory 254400 kb
Host smart-3498e481-d92c-433b-bbfe-89d3e2d182cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131817756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.2131817756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.3655479205
Short name T114
Test name
Test status
Simulation time 103468602 ps
CPU time 1.1 seconds
Started Apr 21 03:46:18 PM PDT 24
Finished Apr 21 03:46:20 PM PDT 24
Peak memory 218356 kb
Host smart-10c4d016-49d3-49d4-b60c-151f78e5098a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655479205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.3655479205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.846036812
Short name T489
Test name
Test status
Simulation time 80274258 ps
CPU time 1.48 seconds
Started Apr 21 03:46:20 PM PDT 24
Finished Apr 21 03:46:22 PM PDT 24
Peak memory 218392 kb
Host smart-2544fbbf-62b7-41b8-8a62-81bf3acb6b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846036812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.846036812 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.3543718605
Short name T503
Test name
Test status
Simulation time 29701398526 ps
CPU time 1164.62 seconds
Started Apr 21 03:46:03 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 313632 kb
Host smart-a4d44aa8-3488-4a91-beb9-e436595201b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543718605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.3543718605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.4080089041
Short name T788
Test name
Test status
Simulation time 4080905684 ps
CPU time 300.15 seconds
Started Apr 21 03:46:04 PM PDT 24
Finished Apr 21 03:51:04 PM PDT 24
Peak memory 249216 kb
Host smart-d7af490c-bd0e-44ff-b899-f8b2db6ca163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080089041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.4080089041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2633186562
Short name T845
Test name
Test status
Simulation time 1268118799 ps
CPU time 49.56 seconds
Started Apr 21 03:45:59 PM PDT 24
Finished Apr 21 03:46:49 PM PDT 24
Peak memory 219496 kb
Host smart-aaa8d375-4b19-4786-8804-05eec87859d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633186562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2633186562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.2192856373
Short name T842
Test name
Test status
Simulation time 247534280201 ps
CPU time 1911.14 seconds
Started Apr 21 03:46:19 PM PDT 24
Finished Apr 21 04:18:11 PM PDT 24
Peak memory 390748 kb
Host smart-0a558748-9ad1-428b-88a9-1dc8128d9c76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2192856373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2192856373 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.3230179720
Short name T197
Test name
Test status
Simulation time 3042888876 ps
CPU time 7.32 seconds
Started Apr 21 03:46:08 PM PDT 24
Finished Apr 21 03:46:16 PM PDT 24
Peak memory 226684 kb
Host smart-bfff7e3d-c4a8-448b-b3ab-4219b3e7a839
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230179720 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.3230179720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1867916517
Short name T768
Test name
Test status
Simulation time 402332299 ps
CPU time 6.51 seconds
Started Apr 21 03:46:14 PM PDT 24
Finished Apr 21 03:46:21 PM PDT 24
Peak memory 218536 kb
Host smart-c737f26a-77e8-4432-8cea-bdc470f26c8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867916517 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1867916517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.541790940
Short name T398
Test name
Test status
Simulation time 99499734902 ps
CPU time 2633.02 seconds
Started Apr 21 03:46:03 PM PDT 24
Finished Apr 21 04:29:57 PM PDT 24
Peak memory 397508 kb
Host smart-64c010b0-54bc-48f1-a784-6a8cfa1137aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=541790940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.541790940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.1530492868
Short name T931
Test name
Test status
Simulation time 153103273230 ps
CPU time 2386.05 seconds
Started Apr 21 03:46:03 PM PDT 24
Finished Apr 21 04:25:50 PM PDT 24
Peak memory 388908 kb
Host smart-d3ab7198-fbd4-4c87-942c-eb4f715dfb83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1530492868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.1530492868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.2940133021
Short name T714
Test name
Test status
Simulation time 103425881622 ps
CPU time 1698.59 seconds
Started Apr 21 03:46:07 PM PDT 24
Finished Apr 21 04:14:26 PM PDT 24
Peak memory 342484 kb
Host smart-59a13bd0-c469-487b-bc0f-eb43d8ae1f22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2940133021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.2940133021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.3803011120
Short name T773
Test name
Test status
Simulation time 42876645650 ps
CPU time 1219.23 seconds
Started Apr 21 03:46:06 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 294740 kb
Host smart-47b76b8a-27fe-4c96-978f-3193942b1c28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3803011120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.3803011120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.3446987936
Short name T471
Test name
Test status
Simulation time 238378467915 ps
CPU time 5292.06 seconds
Started Apr 21 03:46:08 PM PDT 24
Finished Apr 21 05:14:21 PM PDT 24
Peak memory 646816 kb
Host smart-f2f69439-bd5e-433f-ba5c-ecb1c00d1a43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3446987936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3446987936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.4221708593
Short name T235
Test name
Test status
Simulation time 904160165255 ps
CPU time 5501.27 seconds
Started Apr 21 03:46:06 PM PDT 24
Finished Apr 21 05:17:49 PM PDT 24
Peak memory 569676 kb
Host smart-927af921-97b0-4a48-be70-d288089d6f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4221708593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.4221708593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.243053078
Short name T1037
Test name
Test status
Simulation time 18625530 ps
CPU time 0.84 seconds
Started Apr 21 03:46:33 PM PDT 24
Finished Apr 21 03:46:34 PM PDT 24
Peak memory 218280 kb
Host smart-31854aae-969a-40df-b337-7331ba89d750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243053078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.243053078 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.894347795
Short name T929
Test name
Test status
Simulation time 7799962216 ps
CPU time 84.43 seconds
Started Apr 21 03:46:25 PM PDT 24
Finished Apr 21 03:47:50 PM PDT 24
Peak memory 231720 kb
Host smart-66a5ce09-36bb-4f04-bbfd-2a5eb28a9cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894347795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.894347795 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.1603786796
Short name T290
Test name
Test status
Simulation time 6536715063 ps
CPU time 164.11 seconds
Started Apr 21 03:46:21 PM PDT 24
Finished Apr 21 03:49:06 PM PDT 24
Peak memory 227364 kb
Host smart-db7cfab7-3db2-49ad-bfc5-34602f70c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603786796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.1603786796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.1379729836
Short name T491
Test name
Test status
Simulation time 31564558368 ps
CPU time 382.12 seconds
Started Apr 21 03:46:27 PM PDT 24
Finished Apr 21 03:52:49 PM PDT 24
Peak memory 249876 kb
Host smart-21519142-c868-4400-abfb-925e4013b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379729836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1379729836 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.910249100
Short name T1074
Test name
Test status
Simulation time 4616677016 ps
CPU time 100.93 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:48:16 PM PDT 24
Peak memory 243084 kb
Host smart-262288dd-eeb2-4d84-ba50-ec29ec49c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910249100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.910249100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.1547977841
Short name T782
Test name
Test status
Simulation time 3523665008 ps
CPU time 6.8 seconds
Started Apr 21 03:46:36 PM PDT 24
Finished Apr 21 03:46:43 PM PDT 24
Peak memory 218508 kb
Host smart-39dacf50-24d8-48f3-bc77-02ce11170d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547977841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1547977841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.1633982911
Short name T69
Test name
Test status
Simulation time 835085606 ps
CPU time 9.72 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:46:45 PM PDT 24
Peak memory 226836 kb
Host smart-fad2312e-7e12-420b-a7fa-daa1295c801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633982911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1633982911 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.3419515037
Short name T874
Test name
Test status
Simulation time 261718620770 ps
CPU time 1788.14 seconds
Started Apr 21 03:46:21 PM PDT 24
Finished Apr 21 04:16:10 PM PDT 24
Peak memory 346116 kb
Host smart-6813db7b-b07a-4a64-b0fe-084bd170c088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419515037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.3419515037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.4176660158
Short name T772
Test name
Test status
Simulation time 12569208296 ps
CPU time 338.51 seconds
Started Apr 21 03:46:29 PM PDT 24
Finished Apr 21 03:52:08 PM PDT 24
Peak memory 250084 kb
Host smart-e62de6f0-6336-480a-864c-3798dfbfb289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176660158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.4176660158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.4286627402
Short name T472
Test name
Test status
Simulation time 12891143540 ps
CPU time 81.36 seconds
Started Apr 21 03:46:22 PM PDT 24
Finished Apr 21 03:47:44 PM PDT 24
Peak memory 226684 kb
Host smart-ddedfb26-dbc1-4d8b-9675-a6d36a1d7af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286627402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4286627402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.1801189708
Short name T774
Test name
Test status
Simulation time 11199198621 ps
CPU time 236.21 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:50:31 PM PDT 24
Peak memory 269700 kb
Host smart-4f3d917d-24c5-48a2-bc93-02dcde0d8563
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1801189708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1801189708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_stress_all_with_rand_reset.195781347
Short name T915
Test name
Test status
Simulation time 65930654297 ps
CPU time 578.39 seconds
Started Apr 21 03:46:35 PM PDT 24
Finished Apr 21 03:56:13 PM PDT 24
Peak memory 251268 kb
Host smart-53e2054b-e697-4106-bce5-ad7e7eccd826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195781347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.195781347 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.1363099780
Short name T2
Test name
Test status
Simulation time 128694225 ps
CPU time 6.12 seconds
Started Apr 21 03:46:26 PM PDT 24
Finished Apr 21 03:46:32 PM PDT 24
Peak memory 226668 kb
Host smart-588589d5-33c2-4efb-a208-cc3634a4b6fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363099780 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.1363099780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3655346486
Short name T400
Test name
Test status
Simulation time 988235301 ps
CPU time 7.12 seconds
Started Apr 21 03:46:26 PM PDT 24
Finished Apr 21 03:46:33 PM PDT 24
Peak memory 219560 kb
Host smart-41c2e9fd-efd5-4ac9-aa7f-de2cc913f05f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655346486 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3655346486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1390526749
Short name T1067
Test name
Test status
Simulation time 100348632344 ps
CPU time 2436.25 seconds
Started Apr 21 03:46:20 PM PDT 24
Finished Apr 21 04:26:57 PM PDT 24
Peak memory 401260 kb
Host smart-c1566b44-3617-4141-97d6-2a5ca6c19fd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1390526749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1390526749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.2640932590
Short name T721
Test name
Test status
Simulation time 39923382463 ps
CPU time 1744.2 seconds
Started Apr 21 03:46:22 PM PDT 24
Finished Apr 21 04:15:27 PM PDT 24
Peak memory 380880 kb
Host smart-b89da413-80de-4b88-9e0f-5c32da220e6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2640932590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.2640932590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.1811695060
Short name T341
Test name
Test status
Simulation time 14685623495 ps
CPU time 1591.8 seconds
Started Apr 21 03:46:24 PM PDT 24
Finished Apr 21 04:12:56 PM PDT 24
Peak memory 340672 kb
Host smart-bcdec493-ef79-4449-b6cf-e2e24f2f92ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1811695060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.1811695060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.4243887622
Short name T1005
Test name
Test status
Simulation time 45875417337 ps
CPU time 1128.71 seconds
Started Apr 21 03:46:23 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 299104 kb
Host smart-135a6153-7877-495f-9852-f79ef65b23d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4243887622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.4243887622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.3807919963
Short name T571
Test name
Test status
Simulation time 193137687889 ps
CPU time 5630.7 seconds
Started Apr 21 03:46:24 PM PDT 24
Finished Apr 21 05:20:15 PM PDT 24
Peak memory 654268 kb
Host smart-df7297a0-0d88-4d47-a947-b23b188e2460
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3807919963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.3807919963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.4151228407
Short name T276
Test name
Test status
Simulation time 151600147609 ps
CPU time 5030.71 seconds
Started Apr 21 03:46:23 PM PDT 24
Finished Apr 21 05:10:15 PM PDT 24
Peak memory 575200 kb
Host smart-b5080029-f1c5-4054-981a-fa873f5040ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4151228407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.4151228407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.1346756769
Short name T893
Test name
Test status
Simulation time 97027723 ps
CPU time 0.81 seconds
Started Apr 21 03:46:54 PM PDT 24
Finished Apr 21 03:46:55 PM PDT 24
Peak memory 218336 kb
Host smart-1e103dce-d1f8-4d4d-ba49-70210d573989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346756769 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.1346756769 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1099289734
Short name T278
Test name
Test status
Simulation time 5682242981 ps
CPU time 80.89 seconds
Started Apr 21 03:46:48 PM PDT 24
Finished Apr 21 03:48:09 PM PDT 24
Peak memory 230460 kb
Host smart-920b56b7-b869-453e-975b-dcf3fe8f558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099289734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1099289734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.3975692145
Short name T284
Test name
Test status
Simulation time 1783937663 ps
CPU time 93.27 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:48:07 PM PDT 24
Peak memory 234824 kb
Host smart-ba65ecfa-a866-4114-84aa-07825640f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975692145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.3975692145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.3552493715
Short name T251
Test name
Test status
Simulation time 10619930082 ps
CPU time 67.46 seconds
Started Apr 21 03:46:47 PM PDT 24
Finished Apr 21 03:47:55 PM PDT 24
Peak memory 229660 kb
Host smart-aae32189-18e9-46cc-858b-4cb6bbb29b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552493715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3552493715 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.971609443
Short name T454
Test name
Test status
Simulation time 14426399758 ps
CPU time 461.5 seconds
Started Apr 21 03:46:50 PM PDT 24
Finished Apr 21 03:54:32 PM PDT 24
Peak memory 266740 kb
Host smart-9c79a259-975d-4347-8ea2-a1b119753dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971609443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.971609443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.4152166940
Short name T112
Test name
Test status
Simulation time 1741703829 ps
CPU time 5.21 seconds
Started Apr 21 03:46:49 PM PDT 24
Finished Apr 21 03:46:55 PM PDT 24
Peak memory 218408 kb
Host smart-d348107d-1d53-4c57-9d9b-51de3f09d62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152166940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.4152166940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.2599541303
Short name T717
Test name
Test status
Simulation time 700684905 ps
CPU time 10.47 seconds
Started Apr 21 03:46:51 PM PDT 24
Finished Apr 21 03:47:01 PM PDT 24
Peak memory 234804 kb
Host smart-bfede194-b125-4102-b7cd-4122fb23a106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599541303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.2599541303 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.3667198145
Short name T527
Test name
Test status
Simulation time 10882945248 ps
CPU time 504.5 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:54:59 PM PDT 24
Peak memory 268588 kb
Host smart-098214a8-1022-44b5-8915-ee21d3e7a2c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667198145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.3667198145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.2886526504
Short name T545
Test name
Test status
Simulation time 465247095 ps
CPU time 11.48 seconds
Started Apr 21 03:46:35 PM PDT 24
Finished Apr 21 03:46:47 PM PDT 24
Peak memory 226560 kb
Host smart-0e52eff2-67a0-467a-8c8b-5eeff337d558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886526504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.2886526504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1085080718
Short name T1072
Test name
Test status
Simulation time 1115246136 ps
CPU time 17.39 seconds
Started Apr 21 03:46:34 PM PDT 24
Finished Apr 21 03:46:52 PM PDT 24
Peak memory 226640 kb
Host smart-de82a2ee-4b0a-48eb-9159-a8696e2e4f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085080718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1085080718 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.4287009167
Short name T712
Test name
Test status
Simulation time 133809077228 ps
CPU time 3657.5 seconds
Started Apr 21 03:46:49 PM PDT 24
Finished Apr 21 04:47:47 PM PDT 24
Peak memory 557140 kb
Host smart-e647b0b9-1a1c-4186-8501-6cce60cb3878
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4287009167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.4287009167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.4280948154
Short name T192
Test name
Test status
Simulation time 967753451 ps
CPU time 6.63 seconds
Started Apr 21 03:46:46 PM PDT 24
Finished Apr 21 03:46:53 PM PDT 24
Peak memory 218584 kb
Host smart-88dddbc9-e9ce-4fc0-963e-255e1254072f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280948154 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.4280948154 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.2524171681
Short name T225
Test name
Test status
Simulation time 86408210638 ps
CPU time 2036.47 seconds
Started Apr 21 03:46:37 PM PDT 24
Finished Apr 21 04:20:34 PM PDT 24
Peak memory 391212 kb
Host smart-52e89d8f-3477-4678-9c18-7fc58cb131f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2524171681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.2524171681 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.163715511
Short name T631
Test name
Test status
Simulation time 129207539493 ps
CPU time 2215.3 seconds
Started Apr 21 03:46:39 PM PDT 24
Finished Apr 21 04:23:35 PM PDT 24
Peak memory 397184 kb
Host smart-3035d3f6-3f49-4f39-b43b-5b573242d534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=163715511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.163715511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2726962081
Short name T461
Test name
Test status
Simulation time 59793985366 ps
CPU time 1617.88 seconds
Started Apr 21 03:46:40 PM PDT 24
Finished Apr 21 04:13:39 PM PDT 24
Peak memory 340988 kb
Host smart-8c325beb-7fdf-48b9-972b-3b7fadd6261d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2726962081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2726962081 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.2118491337
Short name T907
Test name
Test status
Simulation time 44811760092 ps
CPU time 1311.79 seconds
Started Apr 21 03:46:43 PM PDT 24
Finished Apr 21 04:08:35 PM PDT 24
Peak memory 304248 kb
Host smart-966e66f1-2136-4124-aaf6-7df854d3db15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2118491337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.2118491337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.1938930465
Short name T1006
Test name
Test status
Simulation time 737644056916 ps
CPU time 5496.15 seconds
Started Apr 21 03:46:41 PM PDT 24
Finished Apr 21 05:18:18 PM PDT 24
Peak memory 656948 kb
Host smart-9c9d8728-85eb-4f12-8dc9-3cf6e1c31c64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1938930465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.1938930465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.2882152709
Short name T539
Test name
Test status
Simulation time 151507569450 ps
CPU time 4622.53 seconds
Started Apr 21 03:46:40 PM PDT 24
Finished Apr 21 05:03:43 PM PDT 24
Peak memory 569940 kb
Host smart-77750f7f-b670-45a7-a867-bb919b8390d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2882152709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.2882152709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.1906082650
Short name T547
Test name
Test status
Simulation time 12366169 ps
CPU time 0.86 seconds
Started Apr 21 03:47:17 PM PDT 24
Finished Apr 21 03:47:19 PM PDT 24
Peak memory 220324 kb
Host smart-def87fd1-f4a9-408d-adf8-7c5eca4ad8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906082650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1906082650 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.899364321
Short name T293
Test name
Test status
Simulation time 22452058660 ps
CPU time 370.36 seconds
Started Apr 21 03:47:09 PM PDT 24
Finished Apr 21 03:53:20 PM PDT 24
Peak memory 251316 kb
Host smart-1c91d2e9-b11e-490b-8596-9253b78bad1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899364321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.899364321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.594046809
Short name T500
Test name
Test status
Simulation time 24690086756 ps
CPU time 288.12 seconds
Started Apr 21 03:46:59 PM PDT 24
Finished Apr 21 03:51:47 PM PDT 24
Peak memory 229420 kb
Host smart-22b59b2c-0414-4e41-a902-d690d665d6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594046809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.594046809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.268552809
Short name T985
Test name
Test status
Simulation time 21462639383 ps
CPU time 211.38 seconds
Started Apr 21 03:47:15 PM PDT 24
Finished Apr 21 03:50:47 PM PDT 24
Peak memory 243272 kb
Host smart-eb5ce13d-a103-461d-bdb1-a321765a69f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268552809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.268552809 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.3318267366
Short name T828
Test name
Test status
Simulation time 56081384111 ps
CPU time 507.16 seconds
Started Apr 21 03:47:15 PM PDT 24
Finished Apr 21 03:55:43 PM PDT 24
Peak memory 267612 kb
Host smart-721ccff3-63f2-4bce-96c3-a847ea5cf339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318267366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.3318267366 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.2845155266
Short name T793
Test name
Test status
Simulation time 62451610 ps
CPU time 1.57 seconds
Started Apr 21 03:47:18 PM PDT 24
Finished Apr 21 03:47:19 PM PDT 24
Peak memory 219368 kb
Host smart-327ba3fb-01a4-4620-906d-6cc2ca128605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845155266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2845155266 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.2217044991
Short name T976
Test name
Test status
Simulation time 117482626375 ps
CPU time 1852.7 seconds
Started Apr 21 03:46:54 PM PDT 24
Finished Apr 21 04:17:47 PM PDT 24
Peak memory 348908 kb
Host smart-3a25f71d-c783-423d-9a59-38efaeab800f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217044991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.2217044991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.2831485791
Short name T282
Test name
Test status
Simulation time 5521129148 ps
CPU time 462.14 seconds
Started Apr 21 03:46:59 PM PDT 24
Finished Apr 21 03:54:42 PM PDT 24
Peak memory 253492 kb
Host smart-2dbaffdb-67d5-419b-9306-8bb1c9a50c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831485791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.2831485791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.3086982646
Short name T271
Test name
Test status
Simulation time 6732800803 ps
CPU time 39.31 seconds
Started Apr 21 03:46:53 PM PDT 24
Finished Apr 21 03:47:32 PM PDT 24
Peak memory 221736 kb
Host smart-c3e017fc-3392-428e-93c9-bd83a868943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086982646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3086982646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.996148731
Short name T389
Test name
Test status
Simulation time 12556455055 ps
CPU time 169.38 seconds
Started Apr 21 03:47:19 PM PDT 24
Finished Apr 21 03:50:09 PM PDT 24
Peak memory 247764 kb
Host smart-6253d7ce-fd89-4756-b16a-6893d9042f73
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=996148731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.996148731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.155034371
Short name T825
Test name
Test status
Simulation time 276265767 ps
CPU time 6.5 seconds
Started Apr 21 03:47:06 PM PDT 24
Finished Apr 21 03:47:13 PM PDT 24
Peak memory 226564 kb
Host smart-bcc28c4c-a6a9-486d-9faf-62ebc8494756
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155034371 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.kmac_test_vectors_kmac.155034371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2053128411
Short name T257
Test name
Test status
Simulation time 1012586870 ps
CPU time 6.3 seconds
Started Apr 21 03:47:07 PM PDT 24
Finished Apr 21 03:47:13 PM PDT 24
Peak memory 226576 kb
Host smart-afe75f95-4110-4e21-b401-7dd7d7429ab2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053128411 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2053128411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.1950448957
Short name T593
Test name
Test status
Simulation time 1232534481374 ps
CPU time 2738.58 seconds
Started Apr 21 03:46:56 PM PDT 24
Finished Apr 21 04:32:35 PM PDT 24
Peak memory 400596 kb
Host smart-9e5d1dc2-4d5d-404f-8891-a7a2b5b46a62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1950448957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.1950448957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.1416715376
Short name T1064
Test name
Test status
Simulation time 248462062418 ps
CPU time 2249.75 seconds
Started Apr 21 03:46:59 PM PDT 24
Finished Apr 21 04:24:29 PM PDT 24
Peak memory 388016 kb
Host smart-2a549c53-2f66-4196-8b96-0d393742a653
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1416715376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.1416715376 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.3957657568
Short name T468
Test name
Test status
Simulation time 57678573851 ps
CPU time 1517.2 seconds
Started Apr 21 03:47:05 PM PDT 24
Finished Apr 21 04:12:22 PM PDT 24
Peak memory 332852 kb
Host smart-d6da531f-95fd-4ef1-92d3-e0b1d54b8671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3957657568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.3957657568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1638171546
Short name T325
Test name
Test status
Simulation time 21289310474 ps
CPU time 1267.28 seconds
Started Apr 21 03:47:05 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 302992 kb
Host smart-47ae89dd-a6be-404b-bc5e-07cd8abfaa46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1638171546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1638171546 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.198483564
Short name T548
Test name
Test status
Simulation time 422360652928 ps
CPU time 4785.94 seconds
Started Apr 21 03:47:07 PM PDT 24
Finished Apr 21 05:06:53 PM PDT 24
Peak memory 570720 kb
Host smart-88adc241-f7db-48db-80c9-1f230c703dd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=198483564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.198483564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.2178330488
Short name T700
Test name
Test status
Simulation time 114769496 ps
CPU time 0.94 seconds
Started Apr 21 03:36:19 PM PDT 24
Finished Apr 21 03:36:20 PM PDT 24
Peak memory 220400 kb
Host smart-db0aa409-a4b9-48d1-ac2a-8356fce1472d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178330488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.2178330488 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.2639294176
Short name T532
Test name
Test status
Simulation time 71868936735 ps
CPU time 425 seconds
Started Apr 21 03:35:59 PM PDT 24
Finished Apr 21 03:43:04 PM PDT 24
Peak memory 250656 kb
Host smart-a0bd13a7-9011-448b-ab02-35a61b3fe7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639294176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2639294176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2949332706
Short name T595
Test name
Test status
Simulation time 8052136630 ps
CPU time 198.56 seconds
Started Apr 21 03:36:01 PM PDT 24
Finished Apr 21 03:39:20 PM PDT 24
Peak memory 239616 kb
Host smart-16cc46e0-654c-4ef4-8b22-1710b170d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949332706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2949332706 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.1764874275
Short name T347
Test name
Test status
Simulation time 105517267782 ps
CPU time 1316.62 seconds
Started Apr 21 03:35:41 PM PDT 24
Finished Apr 21 03:57:38 PM PDT 24
Peak memory 243056 kb
Host smart-0b25fd16-74a5-47e0-99a0-1d7ca83a1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764874275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1764874275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3604461569
Short name T919
Test name
Test status
Simulation time 1328170533 ps
CPU time 23.17 seconds
Started Apr 21 03:36:08 PM PDT 24
Finished Apr 21 03:36:31 PM PDT 24
Peak memory 225988 kb
Host smart-d8c72bda-fd91-4ab2-83fb-816d4526a62e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3604461569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3604461569 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.4224931859
Short name T754
Test name
Test status
Simulation time 131068618 ps
CPU time 1.31 seconds
Started Apr 21 03:36:10 PM PDT 24
Finished Apr 21 03:36:12 PM PDT 24
Peak memory 222228 kb
Host smart-bcb244a4-2671-402c-8ed6-ddb9e7519231
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4224931859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4224931859 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.880255629
Short name T403
Test name
Test status
Simulation time 5083030693 ps
CPU time 52.1 seconds
Started Apr 21 03:36:09 PM PDT 24
Finished Apr 21 03:37:01 PM PDT 24
Peak memory 219176 kb
Host smart-c667f885-9291-4ed4-87b7-e6e3060f2577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880255629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.880255629 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.2779947624
Short name T661
Test name
Test status
Simulation time 509537644 ps
CPU time 4.09 seconds
Started Apr 21 03:36:01 PM PDT 24
Finished Apr 21 03:36:06 PM PDT 24
Peak memory 218640 kb
Host smart-8b11ea68-9f63-4632-96f9-a1c29b5f7517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779947624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.2779947624 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.3963863846
Short name T724
Test name
Test status
Simulation time 14575604121 ps
CPU time 257.4 seconds
Started Apr 21 03:36:03 PM PDT 24
Finished Apr 21 03:40:21 PM PDT 24
Peak memory 253140 kb
Host smart-753eaeb7-c6e4-448a-8e12-d5b08ee601ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963863846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3963863846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.3599316732
Short name T24
Test name
Test status
Simulation time 945366553 ps
CPU time 5.87 seconds
Started Apr 21 03:36:08 PM PDT 24
Finished Apr 21 03:36:15 PM PDT 24
Peak memory 218404 kb
Host smart-45368fc8-07b4-4a17-bed3-28eac3735fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599316732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.3599316732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.793309082
Short name T1043
Test name
Test status
Simulation time 58735131 ps
CPU time 1.28 seconds
Started Apr 21 03:36:14 PM PDT 24
Finished Apr 21 03:36:15 PM PDT 24
Peak memory 218384 kb
Host smart-0339dad9-5dcf-42d5-b272-bef1993d09b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793309082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.793309082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2075930640
Short name T648
Test name
Test status
Simulation time 93644451913 ps
CPU time 2712.61 seconds
Started Apr 21 03:35:41 PM PDT 24
Finished Apr 21 04:20:54 PM PDT 24
Peak memory 411696 kb
Host smart-f6d683cd-5769-46d5-ba1e-88329315dc76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075930640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2075930640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.469489503
Short name T698
Test name
Test status
Simulation time 1024826447 ps
CPU time 5.13 seconds
Started Apr 21 03:36:08 PM PDT 24
Finished Apr 21 03:36:14 PM PDT 24
Peak memory 223096 kb
Host smart-151cc0c9-ad99-4938-a89d-9740702299b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469489503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.469489503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sideload.4063122428
Short name T765
Test name
Test status
Simulation time 11689309152 ps
CPU time 398.95 seconds
Started Apr 21 03:35:41 PM PDT 24
Finished Apr 21 03:42:20 PM PDT 24
Peak memory 254216 kb
Host smart-61dbcab8-8743-4951-8f8a-768d96b1fffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063122428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.4063122428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.716986102
Short name T416
Test name
Test status
Simulation time 2191124681 ps
CPU time 48.03 seconds
Started Apr 21 03:35:37 PM PDT 24
Finished Apr 21 03:36:25 PM PDT 24
Peak memory 222096 kb
Host smart-015b3e37-cd30-406c-be99-13118d02c09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716986102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.716986102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2534119808
Short name T1052
Test name
Test status
Simulation time 81194321584 ps
CPU time 2359.05 seconds
Started Apr 21 03:36:13 PM PDT 24
Finished Apr 21 04:15:33 PM PDT 24
Peak memory 464472 kb
Host smart-81e8bc42-a9da-4e2f-889b-7ab907e095f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2534119808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2534119808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3929118046
Short name T79
Test name
Test status
Simulation time 36819816108 ps
CPU time 379.5 seconds
Started Apr 21 03:36:13 PM PDT 24
Finished Apr 21 03:42:33 PM PDT 24
Peak memory 269872 kb
Host smart-fb857685-3044-44d9-b161-012a60dde198
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929118046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3929118046 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.3755389286
Short name T626
Test name
Test status
Simulation time 254817186 ps
CPU time 5.68 seconds
Started Apr 21 03:35:57 PM PDT 24
Finished Apr 21 03:36:03 PM PDT 24
Peak memory 218508 kb
Host smart-bcbdd16c-6bad-40dd-af08-6cf1b20fd560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755389286 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.3755389286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2454963167
Short name T685
Test name
Test status
Simulation time 744524472 ps
CPU time 6.85 seconds
Started Apr 21 03:36:59 PM PDT 24
Finished Apr 21 03:37:07 PM PDT 24
Peak memory 219512 kb
Host smart-ff64ccaf-4a95-46f8-b6bc-9e9df0012d07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454963167 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2454963167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.1586331588
Short name T298
Test name
Test status
Simulation time 256407321281 ps
CPU time 2254.23 seconds
Started Apr 21 03:36:07 PM PDT 24
Finished Apr 21 04:13:42 PM PDT 24
Peak memory 387772 kb
Host smart-ace1f7c1-df25-4bcc-94ac-23dbc14b780a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1586331588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.1586331588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.1881372354
Short name T649
Test name
Test status
Simulation time 356216412555 ps
CPU time 2317.83 seconds
Started Apr 21 03:35:50 PM PDT 24
Finished Apr 21 04:14:28 PM PDT 24
Peak memory 375856 kb
Host smart-3046f3a4-d7e6-4e61-a33b-6c43bfd46f52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1881372354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.1881372354 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.3548942965
Short name T709
Test name
Test status
Simulation time 15062031615 ps
CPU time 1522.11 seconds
Started Apr 21 03:35:50 PM PDT 24
Finished Apr 21 04:01:12 PM PDT 24
Peak memory 332708 kb
Host smart-d6d3a917-be50-480b-ad1e-94e424ab57d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3548942965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.3548942965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.2667395402
Short name T681
Test name
Test status
Simulation time 42719996389 ps
CPU time 1130.78 seconds
Started Apr 21 03:35:55 PM PDT 24
Finished Apr 21 03:54:46 PM PDT 24
Peak memory 303252 kb
Host smart-6bfe3415-b190-4864-912d-d2cf38592f5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2667395402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.2667395402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.2784054495
Short name T778
Test name
Test status
Simulation time 1023790939357 ps
CPU time 5236.56 seconds
Started Apr 21 03:35:51 PM PDT 24
Finished Apr 21 05:03:08 PM PDT 24
Peak memory 657056 kb
Host smart-64d6f9b7-9165-4dea-b9d4-1e00d618fd1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2784054495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.2784054495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.499166516
Short name T302
Test name
Test status
Simulation time 207395076109 ps
CPU time 5085.06 seconds
Started Apr 21 03:35:57 PM PDT 24
Finished Apr 21 05:00:43 PM PDT 24
Peak memory 578332 kb
Host smart-a17eb399-c118-4b31-8c60-d88092f3975a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=499166516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.499166516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.851616506
Short name T11
Test name
Test status
Simulation time 40688747 ps
CPU time 0.85 seconds
Started Apr 21 03:47:44 PM PDT 24
Finished Apr 21 03:47:45 PM PDT 24
Peak memory 220344 kb
Host smart-bad6d82e-2c88-4d53-930d-fc0f14a9c9eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851616506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.851616506 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.432099299
Short name T711
Test name
Test status
Simulation time 5877989848 ps
CPU time 201.75 seconds
Started Apr 21 03:47:34 PM PDT 24
Finished Apr 21 03:50:56 PM PDT 24
Peak memory 241564 kb
Host smart-3840fd14-3c9b-48d9-9bd9-a6d530cd76e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432099299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.432099299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.1076934587
Short name T1013
Test name
Test status
Simulation time 1648438175 ps
CPU time 55.67 seconds
Started Apr 21 03:47:23 PM PDT 24
Finished Apr 21 03:48:19 PM PDT 24
Peak memory 226588 kb
Host smart-6686191c-edcf-4cf3-8e62-70aba6de529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076934587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1076934587 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1493506197
Short name T735
Test name
Test status
Simulation time 10090771674 ps
CPU time 256.95 seconds
Started Apr 21 03:47:35 PM PDT 24
Finished Apr 21 03:51:52 PM PDT 24
Peak memory 245300 kb
Host smart-3885c565-4cac-456b-8d65-7d8c754b982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493506197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1493506197 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.2032041521
Short name T693
Test name
Test status
Simulation time 36374726853 ps
CPU time 298.77 seconds
Started Apr 21 03:47:40 PM PDT 24
Finished Apr 21 03:52:39 PM PDT 24
Peak memory 259464 kb
Host smart-b3175271-428a-498f-9d25-28ace8225e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032041521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2032041521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.3263806613
Short name T507
Test name
Test status
Simulation time 3818689895 ps
CPU time 6.23 seconds
Started Apr 21 03:47:39 PM PDT 24
Finished Apr 21 03:47:45 PM PDT 24
Peak memory 218492 kb
Host smart-d190f86f-f5a3-48f5-94bd-2e941b0ca93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263806613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3263806613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.342528361
Short name T746
Test name
Test status
Simulation time 47251441 ps
CPU time 1.38 seconds
Started Apr 21 03:47:41 PM PDT 24
Finished Apr 21 03:47:42 PM PDT 24
Peak memory 218400 kb
Host smart-0090b6a9-1de6-48a9-987a-1ac6d8324665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342528361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.342528361 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.1993107183
Short name T995
Test name
Test status
Simulation time 1822148862 ps
CPU time 54.86 seconds
Started Apr 21 03:47:20 PM PDT 24
Finished Apr 21 03:48:15 PM PDT 24
Peak memory 234820 kb
Host smart-0f2a33bd-c76e-49f1-b598-340e1d6015c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993107183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.1993107183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.2078185703
Short name T243
Test name
Test status
Simulation time 6542019347 ps
CPU time 258.1 seconds
Started Apr 21 03:47:20 PM PDT 24
Finished Apr 21 03:51:38 PM PDT 24
Peak memory 243912 kb
Host smart-c165c97c-6931-4178-830b-54a789b8f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078185703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.2078185703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2895994948
Short name T309
Test name
Test status
Simulation time 501458748 ps
CPU time 14.93 seconds
Started Apr 21 03:47:21 PM PDT 24
Finished Apr 21 03:47:36 PM PDT 24
Peak memory 219832 kb
Host smart-a4e7f954-955a-4672-93c2-1611087117c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895994948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2895994948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all_with_rand_reset.3800011543
Short name T133
Test name
Test status
Simulation time 165843779232 ps
CPU time 2490.58 seconds
Started Apr 21 03:47:44 PM PDT 24
Finished Apr 21 04:29:15 PM PDT 24
Peak memory 403564 kb
Host smart-d4fdf49b-4c83-427a-b3ab-70448c679608
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800011543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.3800011543 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.4236475120
Short name T1039
Test name
Test status
Simulation time 270171519 ps
CPU time 6.4 seconds
Started Apr 21 03:47:32 PM PDT 24
Finished Apr 21 03:47:39 PM PDT 24
Peak memory 219564 kb
Host smart-b1ea3d4d-403d-4004-a6c0-6014b77f4cc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236475120 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.4236475120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.2170782710
Short name T434
Test name
Test status
Simulation time 273677734 ps
CPU time 6.58 seconds
Started Apr 21 03:47:33 PM PDT 24
Finished Apr 21 03:47:40 PM PDT 24
Peak memory 226620 kb
Host smart-bf976f12-aed8-4eee-bc20-f1b2f8e6d892
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170782710 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.2170782710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.4224169643
Short name T1022
Test name
Test status
Simulation time 399646078087 ps
CPU time 2638.99 seconds
Started Apr 21 03:47:22 PM PDT 24
Finished Apr 21 04:31:21 PM PDT 24
Peak memory 393488 kb
Host smart-548f50d5-4f60-4719-a322-cc1af93d60f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4224169643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.4224169643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.1813964450
Short name T667
Test name
Test status
Simulation time 76540444222 ps
CPU time 2016.26 seconds
Started Apr 21 03:47:25 PM PDT 24
Finished Apr 21 04:21:01 PM PDT 24
Peak memory 383296 kb
Host smart-f4a6877b-eec4-4970-81bf-94c4e1ca4ba9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813964450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.1813964450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.745197973
Short name T878
Test name
Test status
Simulation time 167141163978 ps
CPU time 1694.13 seconds
Started Apr 21 03:47:23 PM PDT 24
Finished Apr 21 04:15:38 PM PDT 24
Peak memory 343984 kb
Host smart-85f28df4-3ff4-476a-acac-edcaca1b9e21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=745197973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.745197973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.4151423212
Short name T986
Test name
Test status
Simulation time 206801078494 ps
CPU time 1482.88 seconds
Started Apr 21 03:47:27 PM PDT 24
Finished Apr 21 04:12:10 PM PDT 24
Peak memory 302968 kb
Host smart-8ef9597d-a3e7-43b9-809a-36301b69fbe5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4151423212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.4151423212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.3813279844
Short name T656
Test name
Test status
Simulation time 60217373206 ps
CPU time 5003.13 seconds
Started Apr 21 03:47:25 PM PDT 24
Finished Apr 21 05:10:49 PM PDT 24
Peak memory 658988 kb
Host smart-52c8789b-93a7-4213-acd8-28fe96522948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3813279844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.3813279844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.3889905202
Short name T280
Test name
Test status
Simulation time 52780280997 ps
CPU time 4529.44 seconds
Started Apr 21 03:47:32 PM PDT 24
Finished Apr 21 05:03:02 PM PDT 24
Peak memory 562116 kb
Host smart-37e9c11b-83df-47db-b4c1-43fa2132ec81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3889905202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3889905202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.315496277
Short name T731
Test name
Test status
Simulation time 36465011 ps
CPU time 0.85 seconds
Started Apr 21 03:48:04 PM PDT 24
Finished Apr 21 03:48:05 PM PDT 24
Peak memory 218348 kb
Host smart-7393e36f-b4c7-497b-947b-77c5e6b33153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315496277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.315496277 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.701881462
Short name T511
Test name
Test status
Simulation time 22913932398 ps
CPU time 329.88 seconds
Started Apr 21 03:47:58 PM PDT 24
Finished Apr 21 03:53:28 PM PDT 24
Peak memory 251952 kb
Host smart-787d3d72-0996-4307-ada0-78afa4ee3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701881462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.701881462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.2276004657
Short name T288
Test name
Test status
Simulation time 11523807942 ps
CPU time 223.56 seconds
Started Apr 21 03:47:58 PM PDT 24
Finished Apr 21 03:51:41 PM PDT 24
Peak memory 243456 kb
Host smart-62146f3d-daca-407b-ad56-6395be1d2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276004657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.2276004657 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2445279957
Short name T922
Test name
Test status
Simulation time 37035606277 ps
CPU time 358.15 seconds
Started Apr 21 03:47:58 PM PDT 24
Finished Apr 21 03:53:57 PM PDT 24
Peak memory 251264 kb
Host smart-7c87b139-0a17-411b-a0aa-ad2c68dc1cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445279957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2445279957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.1736566982
Short name T253
Test name
Test status
Simulation time 784318075 ps
CPU time 5.19 seconds
Started Apr 21 03:48:04 PM PDT 24
Finished Apr 21 03:48:10 PM PDT 24
Peak memory 218432 kb
Host smart-bc83e727-92c7-4103-b7ed-7172967582c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736566982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.1736566982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.853541762
Short name T882
Test name
Test status
Simulation time 125947666 ps
CPU time 1.43 seconds
Started Apr 21 03:48:01 PM PDT 24
Finished Apr 21 03:48:02 PM PDT 24
Peak memory 218408 kb
Host smart-23e57101-a881-4142-9357-885295f5927c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853541762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.853541762 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.890102900
Short name T751
Test name
Test status
Simulation time 985949787760 ps
CPU time 1345.04 seconds
Started Apr 21 03:47:42 PM PDT 24
Finished Apr 21 04:10:07 PM PDT 24
Peak memory 320440 kb
Host smart-feaa5178-8b3b-4371-af92-0c9a8b5b01e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890102900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_an
d_output.890102900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.956314224
Short name T242
Test name
Test status
Simulation time 3169780549 ps
CPU time 226.74 seconds
Started Apr 21 03:47:45 PM PDT 24
Finished Apr 21 03:51:32 PM PDT 24
Peak memory 242088 kb
Host smart-ae45608b-7df7-4ae2-af7e-a6296a931cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956314224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.956314224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.3035654950
Short name T189
Test name
Test status
Simulation time 6951913692 ps
CPU time 71.72 seconds
Started Apr 21 03:47:44 PM PDT 24
Finished Apr 21 03:48:56 PM PDT 24
Peak memory 226708 kb
Host smart-bd7bbfee-52b2-4006-aafa-f17ba0cf3cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035654950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3035654950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.2708428973
Short name T29
Test name
Test status
Simulation time 5905490116 ps
CPU time 88.64 seconds
Started Apr 21 03:48:03 PM PDT 24
Finished Apr 21 03:49:32 PM PDT 24
Peak memory 235928 kb
Host smart-be975d2a-10d0-44f5-8a77-a3cc8bd98505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2708428973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2708428973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3318518401
Short name T330
Test name
Test status
Simulation time 131222761 ps
CPU time 6.43 seconds
Started Apr 21 03:47:55 PM PDT 24
Finished Apr 21 03:48:01 PM PDT 24
Peak memory 226620 kb
Host smart-fad07c42-0a7d-4c9e-93bc-43feb3eac69c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318518401 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3318518401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.2492114504
Short name T431
Test name
Test status
Simulation time 808982316 ps
CPU time 6.02 seconds
Started Apr 21 03:47:55 PM PDT 24
Finished Apr 21 03:48:02 PM PDT 24
Peak memory 218544 kb
Host smart-8577f006-a73a-4d7f-87e7-7d5d8533da20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492114504 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.2492114504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.853940164
Short name T598
Test name
Test status
Simulation time 170775539141 ps
CPU time 1983.08 seconds
Started Apr 21 03:47:53 PM PDT 24
Finished Apr 21 04:20:57 PM PDT 24
Peak memory 398064 kb
Host smart-39e6b37c-24fb-446c-852a-e6c2077fbb70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=853940164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.853940164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.189970254
Short name T815
Test name
Test status
Simulation time 62251276689 ps
CPU time 2227.52 seconds
Started Apr 21 03:47:50 PM PDT 24
Finished Apr 21 04:24:58 PM PDT 24
Peak memory 388032 kb
Host smart-4f437eca-c273-4407-b829-11580d5b324c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=189970254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.189970254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.3011729226
Short name T153
Test name
Test status
Simulation time 206180044809 ps
CPU time 1650.07 seconds
Started Apr 21 03:47:52 PM PDT 24
Finished Apr 21 04:15:23 PM PDT 24
Peak memory 337952 kb
Host smart-9e031038-c94c-4cfe-8bd6-07cb37d0f769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3011729226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3011729226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2710390639
Short name T1016
Test name
Test status
Simulation time 33984626928 ps
CPU time 1308.82 seconds
Started Apr 21 03:47:54 PM PDT 24
Finished Apr 21 04:09:43 PM PDT 24
Peak memory 303940 kb
Host smart-baede9dd-d3f0-4e16-b4fa-579149eca1cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2710390639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2710390639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.1599781473
Short name T514
Test name
Test status
Simulation time 444577452219 ps
CPU time 5342.21 seconds
Started Apr 21 03:47:53 PM PDT 24
Finished Apr 21 05:16:55 PM PDT 24
Peak memory 639532 kb
Host smart-62892896-a558-4f80-9d08-e6f4e04af478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1599781473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1599781473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.2257503624
Short name T821
Test name
Test status
Simulation time 895886978911 ps
CPU time 5298.18 seconds
Started Apr 21 03:47:51 PM PDT 24
Finished Apr 21 05:16:10 PM PDT 24
Peak memory 564024 kb
Host smart-ffcd5f1d-e9a9-4b79-9baf-3f198e9b98cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2257503624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.2257503624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.640757907
Short name T10
Test name
Test status
Simulation time 46979139 ps
CPU time 0.88 seconds
Started Apr 21 03:48:26 PM PDT 24
Finished Apr 21 03:48:27 PM PDT 24
Peak memory 220280 kb
Host smart-14fe08a0-795c-4818-9851-392aee262370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640757907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.640757907 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2688729136
Short name T647
Test name
Test status
Simulation time 34943311303 ps
CPU time 291.15 seconds
Started Apr 21 03:48:18 PM PDT 24
Finished Apr 21 03:53:09 PM PDT 24
Peak memory 245632 kb
Host smart-aae3f718-4932-4981-b5a9-e2af6c7f72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688729136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2688729136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1099749297
Short name T335
Test name
Test status
Simulation time 31049528431 ps
CPU time 844.6 seconds
Started Apr 21 03:48:10 PM PDT 24
Finished Apr 21 04:02:15 PM PDT 24
Peak memory 242800 kb
Host smart-6437e0ad-d95f-4294-b4ca-d9d142046aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099749297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1099749297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.3834180197
Short name T812
Test name
Test status
Simulation time 7937165527 ps
CPU time 30.96 seconds
Started Apr 21 03:48:16 PM PDT 24
Finished Apr 21 03:48:47 PM PDT 24
Peak memory 225536 kb
Host smart-a757cdb0-e529-4b05-a91a-ad7d85d6ba47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834180197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3834180197 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.2763406144
Short name T166
Test name
Test status
Simulation time 17996206984 ps
CPU time 499.94 seconds
Started Apr 21 03:48:23 PM PDT 24
Finished Apr 21 03:56:43 PM PDT 24
Peak memory 259444 kb
Host smart-a32efccc-5bb4-4f78-bdea-fe6973c00a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763406144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2763406144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.2507326616
Short name T492
Test name
Test status
Simulation time 4668150776 ps
CPU time 5.96 seconds
Started Apr 21 03:48:20 PM PDT 24
Finished Apr 21 03:48:26 PM PDT 24
Peak memory 218516 kb
Host smart-c9501662-bc7d-41c3-832e-f50ac81b4cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507326616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2507326616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.623937843
Short name T48
Test name
Test status
Simulation time 1201610297 ps
CPU time 31.24 seconds
Started Apr 21 03:48:22 PM PDT 24
Finished Apr 21 03:48:53 PM PDT 24
Peak memory 236068 kb
Host smart-27b6cb0a-8773-4eae-af97-c2cd095d132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623937843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.623937843 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.82574369
Short name T206
Test name
Test status
Simulation time 97929753729 ps
CPU time 2644.06 seconds
Started Apr 21 03:48:06 PM PDT 24
Finished Apr 21 04:32:10 PM PDT 24
Peak memory 431596 kb
Host smart-93cf4b23-737d-4dbe-9262-42995a06441a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82574369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_and
_output.82574369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3465044021
Short name T760
Test name
Test status
Simulation time 38607860337 ps
CPU time 276.18 seconds
Started Apr 21 03:48:08 PM PDT 24
Finished Apr 21 03:52:44 PM PDT 24
Peak memory 240764 kb
Host smart-64ad75eb-faee-43c1-924c-1a4ef0be9c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465044021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3465044021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1302690932
Short name T730
Test name
Test status
Simulation time 2839687831 ps
CPU time 59.18 seconds
Started Apr 21 03:48:03 PM PDT 24
Finished Apr 21 03:49:02 PM PDT 24
Peak memory 226716 kb
Host smart-9f6d4f56-de84-4798-90af-49ac8dd48120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302690932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1302690932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.703278728
Short name T857
Test name
Test status
Simulation time 14234326692 ps
CPU time 392.04 seconds
Started Apr 21 03:48:25 PM PDT 24
Finished Apr 21 03:54:58 PM PDT 24
Peak memory 274684 kb
Host smart-831018e9-f661-4738-8018-f390f4a4da5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=703278728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.703278728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.2605044659
Short name T703
Test name
Test status
Simulation time 796100706 ps
CPU time 6.25 seconds
Started Apr 21 03:48:17 PM PDT 24
Finished Apr 21 03:48:23 PM PDT 24
Peak memory 226628 kb
Host smart-4130cea5-02bb-4f74-ac5e-192e91cdf6a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605044659 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.2605044659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.3570630088
Short name T359
Test name
Test status
Simulation time 286392074 ps
CPU time 6.85 seconds
Started Apr 21 03:48:17 PM PDT 24
Finished Apr 21 03:48:24 PM PDT 24
Peak memory 218584 kb
Host smart-3dac5317-d971-413c-9631-c474ef248643
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570630088 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.3570630088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.1662295268
Short name T463
Test name
Test status
Simulation time 65575972016 ps
CPU time 2338.01 seconds
Started Apr 21 03:48:13 PM PDT 24
Finished Apr 21 04:27:12 PM PDT 24
Peak memory 390928 kb
Host smart-3d9cea70-2363-4ec2-810f-4d37ab02f0ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1662295268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.1662295268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.2623283282
Short name T608
Test name
Test status
Simulation time 516371405170 ps
CPU time 2325.97 seconds
Started Apr 21 03:48:13 PM PDT 24
Finished Apr 21 04:26:59 PM PDT 24
Peak memory 387160 kb
Host smart-aba0e2d4-1ae5-4960-bb04-368c4a263b9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2623283282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2623283282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.1373671073
Short name T3
Test name
Test status
Simulation time 259901365996 ps
CPU time 1801.77 seconds
Started Apr 21 03:48:17 PM PDT 24
Finished Apr 21 04:18:19 PM PDT 24
Peak memory 344452 kb
Host smart-dcd01729-aba6-46ba-be5b-f89cd9d73d10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1373671073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1373671073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1799362282
Short name T745
Test name
Test status
Simulation time 97648758334 ps
CPU time 1258.87 seconds
Started Apr 21 03:48:14 PM PDT 24
Finished Apr 21 04:09:13 PM PDT 24
Peak memory 302944 kb
Host smart-50a57dd6-92ae-44d8-ae69-6b9345aacb3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1799362282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1799362282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3556909534
Short name T575
Test name
Test status
Simulation time 303508019353 ps
CPU time 5125.79 seconds
Started Apr 21 03:48:14 PM PDT 24
Finished Apr 21 05:13:40 PM PDT 24
Peak memory 664208 kb
Host smart-4b05b9ed-4049-4ee5-83b5-36e591c1b79c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3556909534 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3556909534 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.2664128635
Short name T1033
Test name
Test status
Simulation time 1739448326322 ps
CPU time 5035.6 seconds
Started Apr 21 03:48:13 PM PDT 24
Finished Apr 21 05:12:10 PM PDT 24
Peak memory 569236 kb
Host smart-14418631-bd74-4805-93a6-5ea04c8c0926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2664128635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2664128635 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3630849909
Short name T374
Test name
Test status
Simulation time 46837420 ps
CPU time 0.84 seconds
Started Apr 21 03:48:49 PM PDT 24
Finished Apr 21 03:48:50 PM PDT 24
Peak memory 218304 kb
Host smart-f16f90f4-91ac-4812-880a-537c034b26d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630849909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3630849909 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.1086040668
Short name T33
Test name
Test status
Simulation time 36487476726 ps
CPU time 372.18 seconds
Started Apr 21 03:48:39 PM PDT 24
Finished Apr 21 03:54:52 PM PDT 24
Peak memory 252316 kb
Host smart-188dc57b-dec0-4c04-a787-896481c32c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086040668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1086040668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.3479414801
Short name T932
Test name
Test status
Simulation time 63461990755 ps
CPU time 1679.1 seconds
Started Apr 21 03:48:26 PM PDT 24
Finished Apr 21 04:16:26 PM PDT 24
Peak memory 239736 kb
Host smart-42617209-f12c-4c92-ae3e-dd2fdad91921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479414801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3479414801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.4267551431
Short name T713
Test name
Test status
Simulation time 8354172144 ps
CPU time 107.31 seconds
Started Apr 21 03:48:44 PM PDT 24
Finished Apr 21 03:50:31 PM PDT 24
Peak memory 233276 kb
Host smart-05a17f75-1368-48e3-8110-39fe95702417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267551431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.4267551431 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.418270926
Short name T701
Test name
Test status
Simulation time 8583173461 ps
CPU time 280.38 seconds
Started Apr 21 03:48:45 PM PDT 24
Finished Apr 21 03:53:26 PM PDT 24
Peak memory 259468 kb
Host smart-5c99f10d-cb56-4b1f-a9f3-2b1c7d14decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418270926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.418270926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.2097881129
Short name T345
Test name
Test status
Simulation time 322482997 ps
CPU time 1.69 seconds
Started Apr 21 03:48:44 PM PDT 24
Finished Apr 21 03:48:46 PM PDT 24
Peak memory 218500 kb
Host smart-0c093615-7abc-4e55-8ca6-2a53eeb6e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097881129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2097881129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.2264794633
Short name T49
Test name
Test status
Simulation time 117241449 ps
CPU time 1.39 seconds
Started Apr 21 03:48:47 PM PDT 24
Finished Apr 21 03:48:49 PM PDT 24
Peak memory 218372 kb
Host smart-4147ab4c-c3f2-4ad8-b49c-fc77ceb026b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264794633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.2264794633 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.3369598253
Short name T524
Test name
Test status
Simulation time 6247402291 ps
CPU time 219.05 seconds
Started Apr 21 03:48:24 PM PDT 24
Finished Apr 21 03:52:04 PM PDT 24
Peak memory 243064 kb
Host smart-e5a87aca-577e-4aa6-a230-37c62dc3ad33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369598253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.3369598253 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.1673891672
Short name T85
Test name
Test status
Simulation time 13145890985 ps
CPU time 349.67 seconds
Started Apr 21 03:48:29 PM PDT 24
Finished Apr 21 03:54:19 PM PDT 24
Peak memory 248332 kb
Host smart-79c7ddbc-dd90-4eb4-8890-c08ef5fee7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673891672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.1673891672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.4021543608
Short name T854
Test name
Test status
Simulation time 2693479344 ps
CPU time 38.81 seconds
Started Apr 21 03:48:26 PM PDT 24
Finished Apr 21 03:49:05 PM PDT 24
Peak memory 226580 kb
Host smart-0b0caec0-d9cd-4d3c-82aa-412ef0f68125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021543608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.4021543608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.4042706667
Short name T947
Test name
Test status
Simulation time 19307869186 ps
CPU time 765.6 seconds
Started Apr 21 03:48:47 PM PDT 24
Finished Apr 21 04:01:33 PM PDT 24
Peak memory 301400 kb
Host smart-427ec81e-a87c-4b9a-8bd3-472c4468b6c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4042706667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.4042706667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.591014239
Short name T975
Test name
Test status
Simulation time 121833382 ps
CPU time 6.04 seconds
Started Apr 21 03:48:40 PM PDT 24
Finished Apr 21 03:48:46 PM PDT 24
Peak memory 226592 kb
Host smart-e4276976-1a5d-46d8-83ee-53c4d09ed0e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591014239 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.kmac_test_vectors_kmac.591014239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.540193550
Short name T516
Test name
Test status
Simulation time 87501413 ps
CPU time 5.85 seconds
Started Apr 21 03:48:40 PM PDT 24
Finished Apr 21 03:48:46 PM PDT 24
Peak memory 218548 kb
Host smart-a157305b-081c-4341-8bda-a51afc5a603a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540193550 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.kmac_test_vectors_kmac_xof.540193550 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.848307215
Short name T361
Test name
Test status
Simulation time 41735671021 ps
CPU time 2045.02 seconds
Started Apr 21 03:48:29 PM PDT 24
Finished Apr 21 04:22:34 PM PDT 24
Peak memory 397160 kb
Host smart-1ae98324-830f-47dc-9d6e-86d7aaad34c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=848307215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.848307215 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.3948965847
Short name T1051
Test name
Test status
Simulation time 162900829653 ps
CPU time 2142.11 seconds
Started Apr 21 03:48:30 PM PDT 24
Finished Apr 21 04:24:13 PM PDT 24
Peak memory 379972 kb
Host smart-472bb37d-935f-4fc5-a9b4-c831e98f745f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3948965847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.3948965847 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.4191847958
Short name T513
Test name
Test status
Simulation time 70122722495 ps
CPU time 1787.64 seconds
Started Apr 21 03:48:34 PM PDT 24
Finished Apr 21 04:18:22 PM PDT 24
Peak memory 334388 kb
Host smart-d626ce3e-5d88-4f44-9870-8078607c9979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4191847958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.4191847958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.2089053712
Short name T1048
Test name
Test status
Simulation time 51740472509 ps
CPU time 1333.87 seconds
Started Apr 21 03:48:32 PM PDT 24
Finished Apr 21 04:10:46 PM PDT 24
Peak memory 296940 kb
Host smart-81169929-f050-449f-b4fb-3bc69fe21660
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2089053712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.2089053712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.285946443
Short name T155
Test name
Test status
Simulation time 1063100680133 ps
CPU time 6013.24 seconds
Started Apr 21 03:48:36 PM PDT 24
Finished Apr 21 05:28:51 PM PDT 24
Peak memory 645700 kb
Host smart-a887593d-6d29-462c-84c0-69e54a71533a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=285946443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.285946443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2493215706
Short name T807
Test name
Test status
Simulation time 896395366796 ps
CPU time 5405.45 seconds
Started Apr 21 03:48:35 PM PDT 24
Finished Apr 21 05:18:41 PM PDT 24
Peak memory 590652 kb
Host smart-5f6c9c8e-5d53-4e05-847f-015b8bc8a3bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2493215706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2493215706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.3244743049
Short name T791
Test name
Test status
Simulation time 53948486 ps
CPU time 0.86 seconds
Started Apr 21 03:49:18 PM PDT 24
Finished Apr 21 03:49:19 PM PDT 24
Peak memory 218016 kb
Host smart-fba5ad50-722c-4d4d-9b92-54e629232f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244743049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3244743049 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.2518775055
Short name T804
Test name
Test status
Simulation time 149827802165 ps
CPU time 252.32 seconds
Started Apr 21 03:49:12 PM PDT 24
Finished Apr 21 03:53:25 PM PDT 24
Peak memory 244828 kb
Host smart-7ee75044-69db-48e2-aab6-6848769e2867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518775055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.2518775055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.2386280167
Short name T268
Test name
Test status
Simulation time 753709581 ps
CPU time 35.82 seconds
Started Apr 21 03:48:55 PM PDT 24
Finished Apr 21 03:49:31 PM PDT 24
Peak memory 226584 kb
Host smart-80d97642-4842-4bcd-95e7-8fea4d8f33e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386280167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.2386280167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.206030326
Short name T236
Test name
Test status
Simulation time 20967700146 ps
CPU time 123.54 seconds
Started Apr 21 03:49:15 PM PDT 24
Finished Apr 21 03:51:19 PM PDT 24
Peak memory 234376 kb
Host smart-3faffed7-326c-4cb8-b4ab-1f4e816e15e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206030326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.206030326 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.1888846812
Short name T165
Test name
Test status
Simulation time 22076573286 ps
CPU time 379.24 seconds
Started Apr 21 03:49:19 PM PDT 24
Finished Apr 21 03:55:39 PM PDT 24
Peak memory 259476 kb
Host smart-6ae424da-96d7-4d45-924e-e050faf106d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888846812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1888846812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.157298151
Short name T742
Test name
Test status
Simulation time 282562192 ps
CPU time 1.06 seconds
Started Apr 21 03:49:19 PM PDT 24
Finished Apr 21 03:49:21 PM PDT 24
Peak memory 218324 kb
Host smart-d5a086c4-dfe5-4b6a-abb2-fa41f4055e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157298151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.157298151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2473624209
Short name T70
Test name
Test status
Simulation time 86751779 ps
CPU time 1.24 seconds
Started Apr 21 03:49:19 PM PDT 24
Finished Apr 21 03:49:21 PM PDT 24
Peak memory 218468 kb
Host smart-4206b501-9c7d-4239-a782-b40b15059191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473624209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2473624209 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_sideload.1231637430
Short name T410
Test name
Test status
Simulation time 43053899963 ps
CPU time 401.5 seconds
Started Apr 21 03:48:51 PM PDT 24
Finished Apr 21 03:55:33 PM PDT 24
Peak memory 251572 kb
Host smart-55f74418-51a7-47d0-b8b8-eba5ea82966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231637430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.1231637430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2587547269
Short name T543
Test name
Test status
Simulation time 3628769930 ps
CPU time 75.1 seconds
Started Apr 21 03:48:51 PM PDT 24
Finished Apr 21 03:50:07 PM PDT 24
Peak memory 219260 kb
Host smart-39b4ca35-9dfb-4881-9e8f-1e20fef1b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587547269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2587547269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.3251301658
Short name T972
Test name
Test status
Simulation time 1556629586 ps
CPU time 54.49 seconds
Started Apr 21 03:49:17 PM PDT 24
Finished Apr 21 03:50:12 PM PDT 24
Peak memory 236448 kb
Host smart-fc04d641-0941-4703-a526-2c33b8621408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3251301658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3251301658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.3442681224
Short name T838
Test name
Test status
Simulation time 418036080 ps
CPU time 6.51 seconds
Started Apr 21 03:49:11 PM PDT 24
Finished Apr 21 03:49:18 PM PDT 24
Peak memory 226668 kb
Host smart-b5a40817-787a-460f-8822-a75116c14700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442681224 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.3442681224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.321465872
Short name T967
Test name
Test status
Simulation time 400132797 ps
CPU time 6.42 seconds
Started Apr 21 03:49:12 PM PDT 24
Finished Apr 21 03:49:18 PM PDT 24
Peak memory 226644 kb
Host smart-64d5d7b2-15a2-4993-a1f7-72a9b399ca44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321465872 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.kmac_test_vectors_kmac_xof.321465872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.850642955
Short name T267
Test name
Test status
Simulation time 408514445841 ps
CPU time 2172.47 seconds
Started Apr 21 03:48:56 PM PDT 24
Finished Apr 21 04:25:09 PM PDT 24
Peak memory 396312 kb
Host smart-30d13d42-b3bd-4e5b-ba49-581284a2d1bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=850642955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.850642955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.3179542435
Short name T226
Test name
Test status
Simulation time 48481390863 ps
CPU time 1683.9 seconds
Started Apr 21 03:48:58 PM PDT 24
Finished Apr 21 04:17:03 PM PDT 24
Peak memory 337960 kb
Host smart-60a7e42d-ffbe-4a70-b677-be9595e5775d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3179542435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.3179542435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.682204864
Short name T850
Test name
Test status
Simulation time 2532341443775 ps
CPU time 6215.14 seconds
Started Apr 21 03:49:09 PM PDT 24
Finished Apr 21 05:32:45 PM PDT 24
Peak memory 656452 kb
Host smart-3d211c6d-6c98-4a2f-b9d1-6e2ae2197cae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=682204864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.682204864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.2640315583
Short name T859
Test name
Test status
Simulation time 437474257695 ps
CPU time 5241.73 seconds
Started Apr 21 03:49:09 PM PDT 24
Finished Apr 21 05:16:32 PM PDT 24
Peak memory 568884 kb
Host smart-6ac7c6af-2cd3-44ce-9dfb-69816f78eb57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2640315583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2640315583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.1896247386
Short name T351
Test name
Test status
Simulation time 125434719 ps
CPU time 0.83 seconds
Started Apr 21 03:49:39 PM PDT 24
Finished Apr 21 03:49:40 PM PDT 24
Peak memory 220368 kb
Host smart-1c159858-be78-4cf4-b62c-864d68063058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896247386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.1896247386 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.891089362
Short name T218
Test name
Test status
Simulation time 23885784656 ps
CPU time 347.84 seconds
Started Apr 21 03:49:33 PM PDT 24
Finished Apr 21 03:55:21 PM PDT 24
Peak memory 250820 kb
Host smart-c353aad5-8ebf-4a2e-96ee-0ecad70c5b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891089362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.891089362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3062807837
Short name T748
Test name
Test status
Simulation time 1470022259 ps
CPU time 107.01 seconds
Started Apr 21 03:49:20 PM PDT 24
Finished Apr 21 03:51:07 PM PDT 24
Peak memory 226604 kb
Host smart-092f84c8-ae30-4e9e-b25b-7d3bba7b0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062807837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3062807837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.603659376
Short name T447
Test name
Test status
Simulation time 378028768 ps
CPU time 14.2 seconds
Started Apr 21 03:49:32 PM PDT 24
Finished Apr 21 03:49:47 PM PDT 24
Peak memory 230544 kb
Host smart-2b89d233-e1ae-41f1-b9f5-caec6e38a200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603659376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.603659376 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.2581062229
Short name T287
Test name
Test status
Simulation time 4704220624 ps
CPU time 337.92 seconds
Started Apr 21 03:49:36 PM PDT 24
Finished Apr 21 03:55:14 PM PDT 24
Peak memory 259456 kb
Host smart-a7869408-00e8-4b62-84b7-6723c494832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581062229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.2581062229 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2763026001
Short name T984
Test name
Test status
Simulation time 10605993880 ps
CPU time 7.38 seconds
Started Apr 21 03:49:36 PM PDT 24
Finished Apr 21 03:49:44 PM PDT 24
Peak memory 218504 kb
Host smart-51d00eb4-9e5a-4cbc-8d78-7c34395df055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763026001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2763026001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.2151911858
Short name T26
Test name
Test status
Simulation time 70594096 ps
CPU time 1.34 seconds
Started Apr 21 03:49:36 PM PDT 24
Finished Apr 21 03:49:38 PM PDT 24
Peak memory 218412 kb
Host smart-a7dc84c3-32f1-49d9-b3f4-2cebb6bd409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151911858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.2151911858 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.1433020220
Short name T462
Test name
Test status
Simulation time 18943227750 ps
CPU time 632.59 seconds
Started Apr 21 03:49:20 PM PDT 24
Finished Apr 21 03:59:53 PM PDT 24
Peak memory 277624 kb
Host smart-2ab67a06-4813-4cda-becf-052bcf29d9f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433020220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.1433020220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.4150969655
Short name T630
Test name
Test status
Simulation time 1328038583 ps
CPU time 31.45 seconds
Started Apr 21 03:49:20 PM PDT 24
Finished Apr 21 03:49:52 PM PDT 24
Peak memory 226556 kb
Host smart-6a0f4276-a2c4-47e1-b17c-ab0b4b386c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150969655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.4150969655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3499260831
Short name T307
Test name
Test status
Simulation time 12852911903 ps
CPU time 53.97 seconds
Started Apr 21 03:49:19 PM PDT 24
Finished Apr 21 03:50:14 PM PDT 24
Peak memory 226644 kb
Host smart-0b84fbba-9274-4132-b577-2dd835fe2fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499260831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3499260831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.75328345
Short name T519
Test name
Test status
Simulation time 30473741009 ps
CPU time 1072.49 seconds
Started Apr 21 03:49:35 PM PDT 24
Finished Apr 21 04:07:28 PM PDT 24
Peak memory 341656 kb
Host smart-e9d7bba4-4d51-4624-bf50-dc78763fe49a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=75328345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.75328345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3388383449
Short name T458
Test name
Test status
Simulation time 348904949 ps
CPU time 6.27 seconds
Started Apr 21 03:49:27 PM PDT 24
Finished Apr 21 03:49:33 PM PDT 24
Peak memory 218544 kb
Host smart-c47ae921-ad61-4977-afb9-36008748569a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388383449 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3388383449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.1954319170
Short name T600
Test name
Test status
Simulation time 329869794 ps
CPU time 5.89 seconds
Started Apr 21 03:49:29 PM PDT 24
Finished Apr 21 03:49:35 PM PDT 24
Peak memory 218512 kb
Host smart-4535d2b9-99cf-4c22-9375-97f9c1931631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954319170 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.1954319170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.798754871
Short name T1073
Test name
Test status
Simulation time 49317822795 ps
CPU time 2161.26 seconds
Started Apr 21 03:49:22 PM PDT 24
Finished Apr 21 04:25:24 PM PDT 24
Peak memory 389336 kb
Host smart-9e0ab628-8453-49ec-8152-66a4eca53e4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=798754871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.798754871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.1796447073
Short name T1054
Test name
Test status
Simulation time 93007169384 ps
CPU time 2178.11 seconds
Started Apr 21 03:49:23 PM PDT 24
Finished Apr 21 04:25:41 PM PDT 24
Peak memory 377148 kb
Host smart-a5a5650d-d3c2-49ac-a038-b1bd932007d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1796447073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.1796447073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3241902058
Short name T371
Test name
Test status
Simulation time 613289938329 ps
CPU time 1898.1 seconds
Started Apr 21 03:49:22 PM PDT 24
Finished Apr 21 04:21:01 PM PDT 24
Peak memory 339036 kb
Host smart-3648a064-ca38-4524-96eb-0fe09870c4f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3241902058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3241902058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.79963765
Short name T417
Test name
Test status
Simulation time 156718422331 ps
CPU time 1362.54 seconds
Started Apr 21 03:49:26 PM PDT 24
Finished Apr 21 04:12:09 PM PDT 24
Peak memory 297872 kb
Host smart-a46d9c36-4494-41f4-81e2-cd95937f563c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79963765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.79963765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.408142996
Short name T1070
Test name
Test status
Simulation time 3556165188043 ps
CPU time 6072.81 seconds
Started Apr 21 03:49:25 PM PDT 24
Finished Apr 21 05:30:38 PM PDT 24
Peak memory 662072 kb
Host smart-2cfadafc-458c-498f-ab2b-063e6a91def2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=408142996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.408142996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.2213263975
Short name T628
Test name
Test status
Simulation time 301733467920 ps
CPU time 3936.99 seconds
Started Apr 21 03:49:28 PM PDT 24
Finished Apr 21 04:55:05 PM PDT 24
Peak memory 569932 kb
Host smart-828915e3-a79c-41f8-bed3-241a4a8a989c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2213263975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2213263975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.491010790
Short name T958
Test name
Test status
Simulation time 43341957 ps
CPU time 0.84 seconds
Started Apr 21 03:50:06 PM PDT 24
Finished Apr 21 03:50:07 PM PDT 24
Peak memory 218024 kb
Host smart-fbe16407-35ba-43d7-9915-99cdfb0e541e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491010790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.491010790 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.2240784362
Short name T123
Test name
Test status
Simulation time 42267533723 ps
CPU time 200.64 seconds
Started Apr 21 03:50:03 PM PDT 24
Finished Apr 21 03:53:24 PM PDT 24
Peak memory 243068 kb
Host smart-f870c25f-5ce1-47c0-8fd7-87eb1172e803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240784362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2240784362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3377991615
Short name T285
Test name
Test status
Simulation time 110412011708 ps
CPU time 1126.26 seconds
Started Apr 21 03:49:52 PM PDT 24
Finished Apr 21 04:08:38 PM PDT 24
Peak memory 243032 kb
Host smart-ac47f36f-e916-4643-a810-54a89590753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377991615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3377991615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.3492664731
Short name T52
Test name
Test status
Simulation time 3379858053 ps
CPU time 51.51 seconds
Started Apr 21 03:50:03 PM PDT 24
Finished Apr 21 03:50:55 PM PDT 24
Peak memory 227644 kb
Host smart-4578f1a0-f49f-4fba-a6ca-cfdc0025912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492664731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.3492664731 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.4284645030
Short name T338
Test name
Test status
Simulation time 18704160719 ps
CPU time 489.48 seconds
Started Apr 21 03:50:03 PM PDT 24
Finished Apr 21 03:58:13 PM PDT 24
Peak memory 259460 kb
Host smart-c35f07fc-60f0-4ac5-b427-0769cfd4d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284645030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.4284645030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3509822393
Short name T233
Test name
Test status
Simulation time 808140191 ps
CPU time 2.73 seconds
Started Apr 21 03:50:06 PM PDT 24
Finished Apr 21 03:50:09 PM PDT 24
Peak memory 218416 kb
Host smart-e48e7757-d56e-43d0-9a62-b0dbe41d4983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509822393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3509822393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3412744163
Short name T453
Test name
Test status
Simulation time 54266482 ps
CPU time 1.5 seconds
Started Apr 21 03:50:07 PM PDT 24
Finished Apr 21 03:50:08 PM PDT 24
Peak memory 219384 kb
Host smart-d2826f9a-df68-4dc4-a08f-1c33d75de070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412744163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3412744163 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.324327786
Short name T441
Test name
Test status
Simulation time 10452796649 ps
CPU time 277.32 seconds
Started Apr 21 03:49:52 PM PDT 24
Finished Apr 21 03:54:29 PM PDT 24
Peak memory 245792 kb
Host smart-cfba534e-791d-4a51-835c-cb67967bb828
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324327786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_an
d_output.324327786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1547927898
Short name T640
Test name
Test status
Simulation time 21011833126 ps
CPU time 371.79 seconds
Started Apr 21 03:49:51 PM PDT 24
Finished Apr 21 03:56:03 PM PDT 24
Peak memory 247936 kb
Host smart-6ade344b-a5a1-4503-9487-c6f53f61d670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547927898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1547927898 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.1277583883
Short name T688
Test name
Test status
Simulation time 1439136826 ps
CPU time 15.41 seconds
Started Apr 21 03:49:48 PM PDT 24
Finished Apr 21 03:50:04 PM PDT 24
Peak memory 226192 kb
Host smart-04223884-c1f4-4a61-9079-17103484d46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277583883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.1277583883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.1442443353
Short name T729
Test name
Test status
Simulation time 10605200925 ps
CPU time 897.71 seconds
Started Apr 21 03:50:08 PM PDT 24
Finished Apr 21 04:05:06 PM PDT 24
Peak memory 324084 kb
Host smart-46793404-916e-4498-81fe-6c8dad6527ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1442443353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1442443353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.68969297
Short name T214
Test name
Test status
Simulation time 207102527 ps
CPU time 5.67 seconds
Started Apr 21 03:50:00 PM PDT 24
Finished Apr 21 03:50:06 PM PDT 24
Peak memory 219524 kb
Host smart-3f8ca16d-1d08-49be-9681-326bd4eec8f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68969297 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.kmac_test_vectors_kmac.68969297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.2446989181
Short name T894
Test name
Test status
Simulation time 398697649 ps
CPU time 6.21 seconds
Started Apr 21 03:50:01 PM PDT 24
Finished Apr 21 03:50:08 PM PDT 24
Peak memory 218624 kb
Host smart-5838a5b2-058d-4c92-93f3-b358e10fbf61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446989181 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.2446989181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.2198680007
Short name T399
Test name
Test status
Simulation time 21944090845 ps
CPU time 2180.29 seconds
Started Apr 21 03:49:51 PM PDT 24
Finished Apr 21 04:26:12 PM PDT 24
Peak memory 393252 kb
Host smart-88c6c004-f1a6-4752-ba52-5a5e20d7d0fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2198680007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.2198680007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.1412218790
Short name T299
Test name
Test status
Simulation time 282859498405 ps
CPU time 1972.91 seconds
Started Apr 21 03:49:54 PM PDT 24
Finished Apr 21 04:22:48 PM PDT 24
Peak memory 389504 kb
Host smart-497184f7-641d-4c30-b952-9a1374e3a509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1412218790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.1412218790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.3382068383
Short name T517
Test name
Test status
Simulation time 49457952653 ps
CPU time 1590.59 seconds
Started Apr 21 03:49:53 PM PDT 24
Finished Apr 21 04:16:24 PM PDT 24
Peak memory 342420 kb
Host smart-b45cbb98-b6e5-4f89-ad12-992b167378bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3382068383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.3382068383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.552330422
Short name T800
Test name
Test status
Simulation time 23670786971 ps
CPU time 1265.69 seconds
Started Apr 21 03:50:01 PM PDT 24
Finished Apr 21 04:11:07 PM PDT 24
Peak memory 301608 kb
Host smart-e7c6abf6-1776-4cb9-a590-66d8140f37e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=552330422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.552330422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1643092727
Short name T337
Test name
Test status
Simulation time 195614829286 ps
CPU time 5435.32 seconds
Started Apr 21 03:49:59 PM PDT 24
Finished Apr 21 05:20:36 PM PDT 24
Peak memory 640176 kb
Host smart-5b3b0c26-19ce-46ac-8a47-bd700653daca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1643092727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1643092727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.2855463650
Short name T564
Test name
Test status
Simulation time 1739728299573 ps
CPU time 5546.87 seconds
Started Apr 21 03:50:00 PM PDT 24
Finished Apr 21 05:22:27 PM PDT 24
Peak memory 577316 kb
Host smart-dc91bce9-bb0e-46c5-af6e-6a8e3b40dbba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2855463650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.2855463650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.1284473942
Short name T732
Test name
Test status
Simulation time 164111427 ps
CPU time 0.87 seconds
Started Apr 21 03:50:37 PM PDT 24
Finished Apr 21 03:50:38 PM PDT 24
Peak memory 218316 kb
Host smart-3ae4746d-e124-4a18-86ed-fef49b576e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284473942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1284473942 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.411133949
Short name T1034
Test name
Test status
Simulation time 126802105120 ps
CPU time 330.94 seconds
Started Apr 21 03:50:22 PM PDT 24
Finished Apr 21 03:55:53 PM PDT 24
Peak memory 245860 kb
Host smart-c7f16c22-5381-4be9-aa7b-57a41001e95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411133949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.411133949 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.3881462044
Short name T141
Test name
Test status
Simulation time 154966085562 ps
CPU time 598.62 seconds
Started Apr 21 03:50:13 PM PDT 24
Finished Apr 21 04:00:12 PM PDT 24
Peak memory 242848 kb
Host smart-be9c48bc-d64b-4bb9-b478-3e4c6f33899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881462044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.3881462044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.3742567168
Short name T572
Test name
Test status
Simulation time 2323172805 ps
CPU time 117.99 seconds
Started Apr 21 03:50:22 PM PDT 24
Finished Apr 21 03:52:20 PM PDT 24
Peak memory 234880 kb
Host smart-d9201587-4347-44aa-a259-2a263be99e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742567168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3742567168 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3870187758
Short name T538
Test name
Test status
Simulation time 5808634556 ps
CPU time 201.12 seconds
Started Apr 21 03:50:26 PM PDT 24
Finished Apr 21 03:53:48 PM PDT 24
Peak memory 252032 kb
Host smart-ab5c2ec3-f942-4c2c-8721-34bf9ca95fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870187758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3870187758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1505392580
Short name T474
Test name
Test status
Simulation time 1678829744 ps
CPU time 2.84 seconds
Started Apr 21 03:50:26 PM PDT 24
Finished Apr 21 03:50:29 PM PDT 24
Peak memory 218452 kb
Host smart-2c6d012d-e2df-4a0d-96b2-31355c1c65f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505392580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1505392580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2984396985
Short name T706
Test name
Test status
Simulation time 10714250550 ps
CPU time 262.59 seconds
Started Apr 21 03:50:11 PM PDT 24
Finished Apr 21 03:54:34 PM PDT 24
Peak memory 244024 kb
Host smart-ef5f6d17-c11a-49a1-ad84-d072dff1f3d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984396985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2984396985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2499354832
Short name T210
Test name
Test status
Simulation time 35262449929 ps
CPU time 547.04 seconds
Started Apr 21 03:50:11 PM PDT 24
Finished Apr 21 03:59:19 PM PDT 24
Peak memory 256244 kb
Host smart-71e911f8-16bd-4402-ae29-8f9b56bb2322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499354832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2499354832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3256571036
Short name T535
Test name
Test status
Simulation time 4456143725 ps
CPU time 85.47 seconds
Started Apr 21 03:50:09 PM PDT 24
Finished Apr 21 03:51:35 PM PDT 24
Peak memory 226648 kb
Host smart-25279471-15c5-47a1-b79d-e52d253ace39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256571036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3256571036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.1572375364
Short name T733
Test name
Test status
Simulation time 146121412050 ps
CPU time 793.42 seconds
Started Apr 21 03:50:35 PM PDT 24
Finished Apr 21 04:03:49 PM PDT 24
Peak memory 323220 kb
Host smart-54361ce3-9b2d-47f3-b64b-ff291c30a675
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1572375364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.1572375364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.3536434997
Short name T787
Test name
Test status
Simulation time 805983674 ps
CPU time 5.99 seconds
Started Apr 21 03:50:19 PM PDT 24
Finished Apr 21 03:50:26 PM PDT 24
Peak memory 219656 kb
Host smart-7d42bae3-a8ed-4d4e-8845-26e317bab45b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536434997 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.3536434997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.2751448317
Short name T292
Test name
Test status
Simulation time 841108700 ps
CPU time 7.07 seconds
Started Apr 21 03:50:21 PM PDT 24
Finished Apr 21 03:50:28 PM PDT 24
Peak memory 226664 kb
Host smart-c7aa898b-34ae-4f3a-b574-1f538411656e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751448317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.2751448317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.1780995392
Short name T305
Test name
Test status
Simulation time 177709491822 ps
CPU time 2270.24 seconds
Started Apr 21 03:50:12 PM PDT 24
Finished Apr 21 04:28:02 PM PDT 24
Peak memory 400492 kb
Host smart-f28c4b30-95a8-400e-9dad-564be12c0c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1780995392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.1780995392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.2839589359
Short name T846
Test name
Test status
Simulation time 80431824392 ps
CPU time 1820.45 seconds
Started Apr 21 03:50:14 PM PDT 24
Finished Apr 21 04:20:35 PM PDT 24
Peak memory 384960 kb
Host smart-2ac91bb5-e1a2-47ea-8e33-c3e8e7a6108c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2839589359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2839589359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3114007744
Short name T777
Test name
Test status
Simulation time 305928038918 ps
CPU time 1723.38 seconds
Started Apr 21 03:50:12 PM PDT 24
Finished Apr 21 04:18:55 PM PDT 24
Peak memory 335600 kb
Host smart-24ea0f06-142d-46cb-aab5-ee7862280298
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3114007744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3114007744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.3478980345
Short name T1062
Test name
Test status
Simulation time 10686766360 ps
CPU time 1238.25 seconds
Started Apr 21 03:50:15 PM PDT 24
Finished Apr 21 04:10:54 PM PDT 24
Peak memory 300188 kb
Host smart-8db84171-ffc4-4637-ad63-4014f2c3a3ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3478980345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.3478980345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.4154963759
Short name T385
Test name
Test status
Simulation time 1080561426140 ps
CPU time 6446.35 seconds
Started Apr 21 03:50:15 PM PDT 24
Finished Apr 21 05:37:42 PM PDT 24
Peak memory 659308 kb
Host smart-fccab30e-fa5f-4277-ad23-434985238c0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4154963759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.4154963759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.2555386899
Short name T739
Test name
Test status
Simulation time 114632002723 ps
CPU time 4583.41 seconds
Started Apr 21 03:50:17 PM PDT 24
Finished Apr 21 05:06:42 PM PDT 24
Peak memory 574376 kb
Host smart-b7db88dc-6bdb-42d4-8cf8-d4b1dbfd9870
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2555386899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.2555386899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.2325641163
Short name T231
Test name
Test status
Simulation time 12109460 ps
CPU time 0.86 seconds
Started Apr 21 03:51:02 PM PDT 24
Finished Apr 21 03:51:03 PM PDT 24
Peak memory 218336 kb
Host smart-09e9d825-2b3f-45d0-bebe-73ef316d04da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325641163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.2325641163 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.752043029
Short name T651
Test name
Test status
Simulation time 3948312111 ps
CPU time 261.84 seconds
Started Apr 21 03:50:46 PM PDT 24
Finished Apr 21 03:55:08 PM PDT 24
Peak memory 244724 kb
Host smart-efbbf9d2-65e7-4082-8602-36f956810196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752043029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.752043029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.868052936
Short name T996
Test name
Test status
Simulation time 3014104376 ps
CPU time 37.26 seconds
Started Apr 21 03:50:54 PM PDT 24
Finished Apr 21 03:51:31 PM PDT 24
Peak memory 227836 kb
Host smart-76cd5e7a-5920-4cd1-b9d4-05e6e2f21c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868052936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.868052936 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.2959043900
Short name T889
Test name
Test status
Simulation time 7708523077 ps
CPU time 61.52 seconds
Started Apr 21 03:50:54 PM PDT 24
Finished Apr 21 03:51:56 PM PDT 24
Peak memory 243024 kb
Host smart-b484ddfa-b17e-4f84-bb92-0fd860cc8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959043900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2959043900 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.4025819110
Short name T27
Test name
Test status
Simulation time 595746378 ps
CPU time 4.2 seconds
Started Apr 21 03:50:53 PM PDT 24
Finished Apr 21 03:50:57 PM PDT 24
Peak memory 218496 kb
Host smart-32c7c963-0304-493e-9821-9f45993be512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025819110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.4025819110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.2818790688
Short name T831
Test name
Test status
Simulation time 47364111 ps
CPU time 1.43 seconds
Started Apr 21 03:50:58 PM PDT 24
Finished Apr 21 03:50:59 PM PDT 24
Peak memory 218356 kb
Host smart-cf1a1259-433f-4324-a51c-a1193b9d7a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818790688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.2818790688 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3619559642
Short name T848
Test name
Test status
Simulation time 16465645054 ps
CPU time 1958.85 seconds
Started Apr 21 03:50:38 PM PDT 24
Finished Apr 21 04:23:17 PM PDT 24
Peak memory 379740 kb
Host smart-928738e5-f86f-4c44-8326-7d528b5f23ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619559642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3619559642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.3388078040
Short name T766
Test name
Test status
Simulation time 19337673649 ps
CPU time 351.05 seconds
Started Apr 21 03:50:41 PM PDT 24
Finished Apr 21 03:56:32 PM PDT 24
Peak memory 252836 kb
Host smart-890a8627-431e-44b1-8a76-2bec6e805b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388078040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3388078040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.734267622
Short name T433
Test name
Test status
Simulation time 634977732 ps
CPU time 23.81 seconds
Started Apr 21 03:50:38 PM PDT 24
Finished Apr 21 03:51:02 PM PDT 24
Peak memory 225752 kb
Host smart-76d42799-eb15-446a-b11e-e42d5d5f6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734267622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.734267622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.1257231667
Short name T81
Test name
Test status
Simulation time 42460447076 ps
CPU time 1044.69 seconds
Started Apr 21 03:50:59 PM PDT 24
Finished Apr 21 04:08:24 PM PDT 24
Peak memory 324076 kb
Host smart-b988fbb4-9f23-4527-8dcf-d119cada5340
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1257231667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1257231667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_stress_all_with_rand_reset.4088873474
Short name T30
Test name
Test status
Simulation time 50817335551 ps
CPU time 1919.47 seconds
Started Apr 21 03:50:59 PM PDT 24
Finished Apr 21 04:22:58 PM PDT 24
Peak memory 381580 kb
Host smart-16bc9f62-e23c-40c0-a43b-f047149c8b01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088873474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.4088873474 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.898446562
Short name T427
Test name
Test status
Simulation time 479689754 ps
CPU time 6.34 seconds
Started Apr 21 03:50:41 PM PDT 24
Finished Apr 21 03:50:48 PM PDT 24
Peak memory 226588 kb
Host smart-b9cfb086-cdf1-4d1e-88f3-2954dc61b37f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898446562 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.kmac_test_vectors_kmac.898446562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.4241363732
Short name T227
Test name
Test status
Simulation time 116500604 ps
CPU time 5.68 seconds
Started Apr 21 03:50:45 PM PDT 24
Finished Apr 21 03:50:51 PM PDT 24
Peak memory 218584 kb
Host smart-2601d897-725e-46b9-bdce-350abafe535d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241363732 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.4241363732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.4135677672
Short name T445
Test name
Test status
Simulation time 225037987243 ps
CPU time 2276.68 seconds
Started Apr 21 03:50:41 PM PDT 24
Finished Apr 21 04:28:38 PM PDT 24
Peak memory 400112 kb
Host smart-e86660a2-d011-4252-95ec-26cc7729d402
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4135677672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.4135677672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.2597310223
Short name T966
Test name
Test status
Simulation time 136904654368 ps
CPU time 2152.86 seconds
Started Apr 21 03:50:39 PM PDT 24
Finished Apr 21 04:26:33 PM PDT 24
Peak memory 386252 kb
Host smart-7b934519-df46-40df-be28-1b9d5be97c0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2597310223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.2597310223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3765765191
Short name T402
Test name
Test status
Simulation time 29376862344 ps
CPU time 1578.58 seconds
Started Apr 21 03:50:39 PM PDT 24
Finished Apr 21 04:16:58 PM PDT 24
Peak memory 338312 kb
Host smart-97fccc41-558c-49cc-88ba-8606c711731a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3765765191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3765765191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.3272496251
Short name T414
Test name
Test status
Simulation time 34988979771 ps
CPU time 1293.3 seconds
Started Apr 21 03:50:43 PM PDT 24
Finished Apr 21 04:12:17 PM PDT 24
Peak memory 302288 kb
Host smart-008cb928-681e-498e-9376-00bb420e0eef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3272496251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3272496251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.3793960077
Short name T865
Test name
Test status
Simulation time 61714244321 ps
CPU time 4661.32 seconds
Started Apr 21 03:50:42 PM PDT 24
Finished Apr 21 05:08:24 PM PDT 24
Peak memory 641480 kb
Host smart-3f0d8508-3be4-44c7-90d1-621c3def9405
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3793960077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.3793960077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.3468672671
Short name T615
Test name
Test status
Simulation time 241336556999 ps
CPU time 4233.77 seconds
Started Apr 21 03:50:41 PM PDT 24
Finished Apr 21 05:01:16 PM PDT 24
Peak memory 567548 kb
Host smart-bf50271c-d998-4151-ab00-5968aec86dee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3468672671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3468672671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.2177194307
Short name T339
Test name
Test status
Simulation time 57948198 ps
CPU time 0.87 seconds
Started Apr 21 03:51:29 PM PDT 24
Finished Apr 21 03:51:30 PM PDT 24
Peak memory 220320 kb
Host smart-869372eb-e00c-42e9-996c-732daf27d213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177194307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.2177194307 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3882572270
Short name T943
Test name
Test status
Simulation time 5608320647 ps
CPU time 332.75 seconds
Started Apr 21 03:51:13 PM PDT 24
Finished Apr 21 03:56:46 PM PDT 24
Peak memory 249724 kb
Host smart-c9718ec7-d16d-4400-8c87-b0f0021403f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882572270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3882572270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.1056388336
Short name T460
Test name
Test status
Simulation time 7704702491 ps
CPU time 364.43 seconds
Started Apr 21 03:51:03 PM PDT 24
Finished Apr 21 03:57:08 PM PDT 24
Peak memory 230920 kb
Host smart-93710065-1b8e-477e-8a0e-60f8fa3c5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056388336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.1056388336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.216301572
Short name T924
Test name
Test status
Simulation time 19691303952 ps
CPU time 190.7 seconds
Started Apr 21 03:51:14 PM PDT 24
Finished Apr 21 03:54:25 PM PDT 24
Peak memory 241776 kb
Host smart-c59f55ce-adf5-4886-b6ae-c4c26b17b9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216301572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.216301572 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.3689335600
Short name T318
Test name
Test status
Simulation time 77502672885 ps
CPU time 527.57 seconds
Started Apr 21 03:51:13 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 267716 kb
Host smart-20775cab-90de-4fb7-9a66-d7d2455ec059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689335600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3689335600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.3174332341
Short name T1009
Test name
Test status
Simulation time 79031614 ps
CPU time 1.2 seconds
Started Apr 21 03:51:19 PM PDT 24
Finished Apr 21 03:51:21 PM PDT 24
Peak memory 218320 kb
Host smart-2c1c89ca-c078-4754-8dd5-174481311e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174332341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.3174332341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.2988669320
Short name T891
Test name
Test status
Simulation time 77178168611 ps
CPU time 1582.8 seconds
Started Apr 21 03:51:00 PM PDT 24
Finished Apr 21 04:17:23 PM PDT 24
Peak memory 341700 kb
Host smart-4b022fda-38b9-4252-a77e-5ff6a9f39d28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988669320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.2988669320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.877468943
Short name T1046
Test name
Test status
Simulation time 10830784287 ps
CPU time 217.88 seconds
Started Apr 21 03:51:01 PM PDT 24
Finished Apr 21 03:54:40 PM PDT 24
Peak memory 241876 kb
Host smart-71dad2aa-8ac1-4247-937d-698357a464b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877468943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.877468943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.3679197808
Short name T988
Test name
Test status
Simulation time 1547497759 ps
CPU time 41.92 seconds
Started Apr 21 03:51:00 PM PDT 24
Finished Apr 21 03:51:43 PM PDT 24
Peak memory 226592 kb
Host smart-a069c344-c507-4ef7-98fa-b9b54826c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679197808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3679197808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3247443508
Short name T861
Test name
Test status
Simulation time 7464621632 ps
CPU time 168.16 seconds
Started Apr 21 03:51:24 PM PDT 24
Finished Apr 21 03:54:12 PM PDT 24
Peak memory 247552 kb
Host smart-79e27fa0-fa3b-4b0f-bdaf-bf500b038bed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3247443508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3247443508 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.3414754079
Short name T247
Test name
Test status
Simulation time 914151260 ps
CPU time 6.88 seconds
Started Apr 21 03:51:11 PM PDT 24
Finished Apr 21 03:51:18 PM PDT 24
Peak memory 218544 kb
Host smart-3bc165b6-69fc-4dfa-8b98-8b8ac034d454
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414754079 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.3414754079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.1355996086
Short name T569
Test name
Test status
Simulation time 1190008307 ps
CPU time 6.52 seconds
Started Apr 21 03:51:11 PM PDT 24
Finished Apr 21 03:51:18 PM PDT 24
Peak memory 218588 kb
Host smart-a78c5bf5-ce64-45a2-8210-f2a0b04b33ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355996086 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.1355996086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.3521531578
Short name T221
Test name
Test status
Simulation time 96584577353 ps
CPU time 2574.36 seconds
Started Apr 21 03:51:03 PM PDT 24
Finished Apr 21 04:33:58 PM PDT 24
Peak memory 395536 kb
Host smart-b2d53248-e7e7-4832-b817-4d8e65253b87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3521531578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.3521531578 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.3026318762
Short name T1058
Test name
Test status
Simulation time 20389093526 ps
CPU time 1990.75 seconds
Started Apr 21 03:51:04 PM PDT 24
Finished Apr 21 04:24:15 PM PDT 24
Peak memory 393632 kb
Host smart-44f1b47d-e6b1-4583-af4c-8700497719cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3026318762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.3026318762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.1866582270
Short name T728
Test name
Test status
Simulation time 19093029309 ps
CPU time 1414.64 seconds
Started Apr 21 03:51:01 PM PDT 24
Finished Apr 21 04:14:36 PM PDT 24
Peak memory 338384 kb
Host smart-13d2dc02-b2f1-47f5-b199-7bd987a0fedb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1866582270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1866582270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.1705140908
Short name T74
Test name
Test status
Simulation time 21550090787 ps
CPU time 1193.98 seconds
Started Apr 21 03:51:07 PM PDT 24
Finished Apr 21 04:11:02 PM PDT 24
Peak memory 303132 kb
Host smart-633f1cf8-1cb2-4247-af44-00fe896b03d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1705140908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1705140908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.828185226
Short name T1023
Test name
Test status
Simulation time 124789507807 ps
CPU time 5092.86 seconds
Started Apr 21 03:51:10 PM PDT 24
Finished Apr 21 05:16:04 PM PDT 24
Peak memory 656964 kb
Host smart-bef6ba5e-e8e0-4d02-9331-9f71d22d6736
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=828185226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.828185226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.93053523
Short name T734
Test name
Test status
Simulation time 613829341670 ps
CPU time 4765.98 seconds
Started Apr 21 03:51:10 PM PDT 24
Finished Apr 21 05:10:37 PM PDT 24
Peak memory 557712 kb
Host smart-017567ff-a389-4d9f-baf6-87c11fa8ca81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=93053523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.93053523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.1890702338
Short name T455
Test name
Test status
Simulation time 15315117 ps
CPU time 0.85 seconds
Started Apr 21 03:37:06 PM PDT 24
Finished Apr 21 03:37:07 PM PDT 24
Peak memory 218300 kb
Host smart-b41076db-efb4-4502-89ee-ca649d7079ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890702338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1890702338 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.1720039739
Short name T911
Test name
Test status
Simulation time 26264653115 ps
CPU time 366.19 seconds
Started Apr 21 03:36:45 PM PDT 24
Finished Apr 21 03:42:51 PM PDT 24
Peak memory 251492 kb
Host smart-01d8e44f-df7c-4657-9c1e-a70617af36d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720039739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.1720039739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3688115351
Short name T928
Test name
Test status
Simulation time 20301024627 ps
CPU time 362 seconds
Started Apr 21 03:36:44 PM PDT 24
Finished Apr 21 03:42:46 PM PDT 24
Peak memory 248348 kb
Host smart-0df8a255-5773-4d6d-92a9-78d97e3794c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688115351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3688115351 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.3053694087
Short name T8
Test name
Test status
Simulation time 8524019974 ps
CPU time 978.02 seconds
Started Apr 21 03:36:35 PM PDT 24
Finished Apr 21 03:52:53 PM PDT 24
Peak memory 234536 kb
Host smart-45d428a7-3440-41a5-940a-c36da8af04bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053694087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3053694087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.1412907994
Short name T264
Test name
Test status
Simulation time 1428954719 ps
CPU time 41.39 seconds
Started Apr 21 03:36:53 PM PDT 24
Finished Apr 21 03:37:34 PM PDT 24
Peak memory 227124 kb
Host smart-6be0b875-404d-4849-a7ac-6512cac168e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1412907994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.1412907994 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2438215028
Short name T726
Test name
Test status
Simulation time 34215458 ps
CPU time 0.98 seconds
Started Apr 21 03:36:56 PM PDT 24
Finished Apr 21 03:36:57 PM PDT 24
Peak memory 221460 kb
Host smart-4436f80f-0c2e-4d77-895b-858654232d03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438215028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2438215028 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.3693625180
Short name T420
Test name
Test status
Simulation time 26927092089 ps
CPU time 79.92 seconds
Started Apr 21 03:36:57 PM PDT 24
Finished Apr 21 03:38:18 PM PDT 24
Peak memory 219860 kb
Host smart-269a197d-4097-4eb9-aa7f-412567e35cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693625180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.3693625180 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.1763078578
Short name T974
Test name
Test status
Simulation time 6769442503 ps
CPU time 265.14 seconds
Started Apr 21 03:36:49 PM PDT 24
Finished Apr 21 03:41:14 PM PDT 24
Peak memory 247212 kb
Host smart-bb62cffa-09a8-43f3-8509-824a59e7e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763078578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1763078578 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.2436335673
Short name T256
Test name
Test status
Simulation time 3491365093 ps
CPU time 308.67 seconds
Started Apr 21 03:36:46 PM PDT 24
Finished Apr 21 03:41:55 PM PDT 24
Peak memory 259420 kb
Host smart-b58500f7-1284-4ed7-b71e-9fc05108fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436335673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2436335673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.1464776520
Short name T15
Test name
Test status
Simulation time 845032010 ps
CPU time 5.32 seconds
Started Apr 21 03:36:50 PM PDT 24
Finished Apr 21 03:36:55 PM PDT 24
Peak memory 218460 kb
Host smart-906e7c2b-3462-4a26-90c4-74f4406f2677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464776520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1464776520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.1018517395
Short name T978
Test name
Test status
Simulation time 1414790311 ps
CPU time 9.54 seconds
Started Apr 21 03:36:58 PM PDT 24
Finished Apr 21 03:37:07 PM PDT 24
Peak memory 234692 kb
Host smart-f658f02c-8ce1-46d6-992b-f2abfe2159d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018517395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1018517395 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.3918057176
Short name T270
Test name
Test status
Simulation time 404994671237 ps
CPU time 2167.96 seconds
Started Apr 21 03:36:18 PM PDT 24
Finished Apr 21 04:12:26 PM PDT 24
Peak memory 393840 kb
Host smart-401c7119-9818-4857-9086-777aeb6041f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918057176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.3918057176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.2529703216
Short name T80
Test name
Test status
Simulation time 12136576007 ps
CPU time 170.76 seconds
Started Apr 21 03:36:48 PM PDT 24
Finished Apr 21 03:39:39 PM PDT 24
Peak memory 238136 kb
Host smart-b16b6ce9-0f1c-4168-ac62-b08ee7e149d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529703216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.2529703216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sideload.986729880
Short name T501
Test name
Test status
Simulation time 7371675712 ps
CPU time 317.79 seconds
Started Apr 21 03:36:25 PM PDT 24
Finished Apr 21 03:41:43 PM PDT 24
Peak memory 245132 kb
Host smart-432608d8-b58c-4ddc-b2ff-fd7823beb4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986729880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.986729880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1886303720
Short name T469
Test name
Test status
Simulation time 763807232 ps
CPU time 16.53 seconds
Started Apr 21 03:36:35 PM PDT 24
Finished Apr 21 03:36:52 PM PDT 24
Peak memory 226608 kb
Host smart-7a5f1aa1-ac99-4dc0-a921-f9ad507a4fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886303720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1886303720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3796855540
Short name T525
Test name
Test status
Simulation time 36089706716 ps
CPU time 1303.25 seconds
Started Apr 21 03:36:57 PM PDT 24
Finished Apr 21 03:58:40 PM PDT 24
Peak memory 356192 kb
Host smart-e96ba7d2-b18a-4606-806f-184c4c1d3566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3796855540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3796855540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.860982360
Short name T1059
Test name
Test status
Simulation time 154278719145 ps
CPU time 706.87 seconds
Started Apr 21 03:37:01 PM PDT 24
Finished Apr 21 03:48:49 PM PDT 24
Peak memory 287108 kb
Host smart-a377a896-ccc6-41cd-bcb8-4483846c35df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=860982360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.860982360 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.1955265881
Short name T716
Test name
Test status
Simulation time 121126478 ps
CPU time 5.54 seconds
Started Apr 21 03:36:54 PM PDT 24
Finished Apr 21 03:37:00 PM PDT 24
Peak memory 226580 kb
Host smart-a0d6fa50-cf7d-470a-9a6f-5b135b5f5bd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955265881 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.1955265881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.4083607263
Short name T704
Test name
Test status
Simulation time 1866348925 ps
CPU time 7.67 seconds
Started Apr 21 03:36:45 PM PDT 24
Finished Apr 21 03:36:53 PM PDT 24
Peak memory 218584 kb
Host smart-f25a383d-02f1-427a-afce-d4cc3bf0c625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083607263 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.4083607263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.1368108398
Short name T73
Test name
Test status
Simulation time 126616103945 ps
CPU time 2123.58 seconds
Started Apr 21 03:36:32 PM PDT 24
Finished Apr 21 04:11:56 PM PDT 24
Peak memory 396640 kb
Host smart-8c8287a3-2b2f-4747-a8ee-485c21145fa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1368108398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1368108398 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.1684960390
Short name T51
Test name
Test status
Simulation time 63936760715 ps
CPU time 2173.18 seconds
Started Apr 21 03:36:32 PM PDT 24
Finished Apr 21 04:12:45 PM PDT 24
Peak memory 394716 kb
Host smart-2f601da6-4e4c-4ac6-b9ff-0610abf3cb7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1684960390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1684960390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2560180733
Short name T232
Test name
Test status
Simulation time 506857869041 ps
CPU time 1848.49 seconds
Started Apr 21 03:36:33 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 333856 kb
Host smart-6fb6c416-12ae-4fb3-8559-71805921dd12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2560180733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2560180733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.1870731793
Short name T565
Test name
Test status
Simulation time 137408415817 ps
CPU time 1356.4 seconds
Started Apr 21 03:36:34 PM PDT 24
Finished Apr 21 03:59:10 PM PDT 24
Peak memory 299176 kb
Host smart-9d354423-2b97-41d4-8ca3-f4de584e4ef7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1870731793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.1870731793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3711059028
Short name T512
Test name
Test status
Simulation time 276529761141 ps
CPU time 5380.67 seconds
Started Apr 21 03:36:36 PM PDT 24
Finished Apr 21 05:06:17 PM PDT 24
Peak memory 648532 kb
Host smart-5eddc96b-e9d3-46a8-b88f-175dd9382fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3711059028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3711059028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.822780493
Short name T833
Test name
Test status
Simulation time 73122353831 ps
CPU time 4883.83 seconds
Started Apr 21 03:36:42 PM PDT 24
Finished Apr 21 04:58:06 PM PDT 24
Peak memory 566008 kb
Host smart-04c2f229-955d-422a-9660-9b6032da0bd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=822780493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.822780493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.700887239
Short name T673
Test name
Test status
Simulation time 26268975 ps
CPU time 0.86 seconds
Started Apr 21 03:51:49 PM PDT 24
Finished Apr 21 03:51:50 PM PDT 24
Peak memory 220348 kb
Host smart-84e2f52a-84d6-4b3b-be83-667415a47880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700887239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.700887239 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.1967199436
Short name T672
Test name
Test status
Simulation time 11413339895 ps
CPU time 296.76 seconds
Started Apr 21 03:51:37 PM PDT 24
Finished Apr 21 03:56:34 PM PDT 24
Peak memory 249676 kb
Host smart-51a4cf67-f30e-422f-9621-dbb569502ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967199436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1967199436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.1805792410
Short name T483
Test name
Test status
Simulation time 16836241587 ps
CPU time 1483.68 seconds
Started Apr 21 03:51:32 PM PDT 24
Finished Apr 21 04:16:17 PM PDT 24
Peak memory 243080 kb
Host smart-bc762fa8-f2c6-4839-9bd9-c4694d75d6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805792410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1805792410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.220758684
Short name T35
Test name
Test status
Simulation time 8165577622 ps
CPU time 354.11 seconds
Started Apr 21 03:51:38 PM PDT 24
Finished Apr 21 03:57:32 PM PDT 24
Peak memory 251096 kb
Host smart-86aa1f52-5e12-4ee5-8d97-ad3493ca93ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220758684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.220758684 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.1380759684
Short name T763
Test name
Test status
Simulation time 81209710838 ps
CPU time 356.88 seconds
Started Apr 21 03:51:41 PM PDT 24
Finished Apr 21 03:57:38 PM PDT 24
Peak memory 259472 kb
Host smart-f5fb8aec-721b-4dfb-a8ed-80109f0f970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380759684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.1380759684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1331641866
Short name T1028
Test name
Test status
Simulation time 168459935 ps
CPU time 1.43 seconds
Started Apr 21 03:51:45 PM PDT 24
Finished Apr 21 03:51:46 PM PDT 24
Peak memory 218352 kb
Host smart-97110a18-b996-4e47-8157-934d30bd8548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331641866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1331641866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.3675250355
Short name T620
Test name
Test status
Simulation time 92431617 ps
CPU time 1.71 seconds
Started Apr 21 03:51:44 PM PDT 24
Finished Apr 21 03:51:46 PM PDT 24
Peak memory 219364 kb
Host smart-803e2dde-c362-43e2-b5b6-40eff85497b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675250355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3675250355 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_sideload.3573826275
Short name T710
Test name
Test status
Simulation time 7976471907 ps
CPU time 83.06 seconds
Started Apr 21 03:51:27 PM PDT 24
Finished Apr 21 03:52:51 PM PDT 24
Peak memory 230132 kb
Host smart-548ded04-ab32-45f9-ae5c-1f3d7a82282d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573826275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.3573826275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1402449782
Short name T660
Test name
Test status
Simulation time 1718305560 ps
CPU time 70.78 seconds
Started Apr 21 03:51:29 PM PDT 24
Finished Apr 21 03:52:40 PM PDT 24
Peak memory 222488 kb
Host smart-0b75f51d-53e7-453a-b635-94856018800d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402449782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1402449782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.1431426041
Short name T638
Test name
Test status
Simulation time 55873303718 ps
CPU time 1140.12 seconds
Started Apr 21 03:51:49 PM PDT 24
Finished Apr 21 04:10:49 PM PDT 24
Peak memory 349856 kb
Host smart-f604db3c-a0ce-47e5-8900-be6b74227c91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1431426041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.1431426041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.2697878123
Short name T495
Test name
Test status
Simulation time 622933224 ps
CPU time 5.58 seconds
Started Apr 21 03:51:34 PM PDT 24
Finished Apr 21 03:51:40 PM PDT 24
Peak memory 226644 kb
Host smart-780a0699-81f1-49b0-ab33-4a213f5e7855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697878123 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.kmac_test_vectors_kmac.2697878123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.4201956669
Short name T1055
Test name
Test status
Simulation time 1223191973 ps
CPU time 6.95 seconds
Started Apr 21 03:51:35 PM PDT 24
Finished Apr 21 03:51:42 PM PDT 24
Peak memory 218576 kb
Host smart-db41a20e-8bab-435d-bae2-070d4e2a2593
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201956669 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.4201956669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.47093213
Short name T643
Test name
Test status
Simulation time 44423952491 ps
CPU time 2281.89 seconds
Started Apr 21 03:51:33 PM PDT 24
Finished Apr 21 04:29:35 PM PDT 24
Peak memory 404880 kb
Host smart-43e76b12-27bc-44b2-a530-ccae172ffff9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=47093213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.47093213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.453498958
Short name T336
Test name
Test status
Simulation time 843821955589 ps
CPU time 2685.04 seconds
Started Apr 21 03:51:33 PM PDT 24
Finished Apr 21 04:36:19 PM PDT 24
Peak memory 392132 kb
Host smart-f156ae6d-416e-46e5-99e4-874635d869a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=453498958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.453498958 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.2853096541
Short name T940
Test name
Test status
Simulation time 34976178651 ps
CPU time 1488.41 seconds
Started Apr 21 03:51:33 PM PDT 24
Finished Apr 21 04:16:22 PM PDT 24
Peak memory 340588 kb
Host smart-e975d498-36d0-4ca6-8bd6-46f0fec76cc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2853096541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.2853096541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2707620994
Short name T749
Test name
Test status
Simulation time 103293351259 ps
CPU time 1452.03 seconds
Started Apr 21 03:51:35 PM PDT 24
Finished Apr 21 04:15:47 PM PDT 24
Peak memory 301804 kb
Host smart-21366146-f793-48ac-816b-7e6b399cb335
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2707620994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2707620994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2717488554
Short name T719
Test name
Test status
Simulation time 188162516789 ps
CPU time 5747.3 seconds
Started Apr 21 03:51:33 PM PDT 24
Finished Apr 21 05:27:21 PM PDT 24
Peak memory 673636 kb
Host smart-93966553-656c-4929-a7b9-1b4e6a1bfa2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2717488554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2717488554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.3108944770
Short name T880
Test name
Test status
Simulation time 124970024906 ps
CPU time 4330.53 seconds
Started Apr 21 03:51:35 PM PDT 24
Finished Apr 21 05:03:46 PM PDT 24
Peak memory 572940 kb
Host smart-2717371f-c25c-460f-b17e-7b36366ce02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3108944770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.3108944770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.746852321
Short name T910
Test name
Test status
Simulation time 65770566 ps
CPU time 0.87 seconds
Started Apr 21 03:52:17 PM PDT 24
Finished Apr 21 03:52:18 PM PDT 24
Peak memory 218360 kb
Host smart-4fd56213-b82d-4168-bb43-0f91f51a0aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746852321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.746852321 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2076310136
Short name T156
Test name
Test status
Simulation time 28259325446 ps
CPU time 311.59 seconds
Started Apr 21 03:52:12 PM PDT 24
Finished Apr 21 03:57:24 PM PDT 24
Peak memory 249652 kb
Host smart-f4412506-e0fd-4752-8db9-5916ba6789e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076310136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2076310136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.3520614406
Short name T1080
Test name
Test status
Simulation time 24124783474 ps
CPU time 739.02 seconds
Started Apr 21 03:51:55 PM PDT 24
Finished Apr 21 04:04:15 PM PDT 24
Peak memory 234352 kb
Host smart-26eb8cfd-658e-4fc1-8882-0b6c16cadabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520614406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.3520614406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.4113599398
Short name T509
Test name
Test status
Simulation time 5077543336 ps
CPU time 363.61 seconds
Started Apr 21 03:52:13 PM PDT 24
Finished Apr 21 03:58:17 PM PDT 24
Peak memory 250964 kb
Host smart-bf3b5bdf-5ba6-4ffc-bdaa-5647cbc5f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113599398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.4113599398 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.3590083995
Short name T904
Test name
Test status
Simulation time 7574902803 ps
CPU time 184.81 seconds
Started Apr 21 03:52:10 PM PDT 24
Finished Apr 21 03:55:15 PM PDT 24
Peak memory 251240 kb
Host smart-6afadc55-8188-4753-982c-5ffa9b68738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590083995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.3590083995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.1698087202
Short name T352
Test name
Test status
Simulation time 836953434 ps
CPU time 5 seconds
Started Apr 21 03:52:13 PM PDT 24
Finished Apr 21 03:52:18 PM PDT 24
Peak memory 218448 kb
Host smart-08414138-346c-48eb-b525-171e755a3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698087202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1698087202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.750480673
Short name T898
Test name
Test status
Simulation time 53755325 ps
CPU time 1.46 seconds
Started Apr 21 03:52:14 PM PDT 24
Finished Apr 21 03:52:16 PM PDT 24
Peak memory 218368 kb
Host smart-ec9101e1-7602-44a0-bb3a-1cbadac3733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750480673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.750480673 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.308987457
Short name T1077
Test name
Test status
Simulation time 12742043126 ps
CPU time 235.67 seconds
Started Apr 21 03:51:52 PM PDT 24
Finished Apr 21 03:55:48 PM PDT 24
Peak memory 243108 kb
Host smart-009d07a5-25c5-44d6-bf45-80a5b693c013
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308987457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_an
d_output.308987457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2338869589
Short name T566
Test name
Test status
Simulation time 3426635297 ps
CPU time 285.99 seconds
Started Apr 21 03:51:54 PM PDT 24
Finished Apr 21 03:56:40 PM PDT 24
Peak memory 243896 kb
Host smart-d9eea164-1500-45c5-9b37-c8ba0d83cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338869589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2338869589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1184393973
Short name T312
Test name
Test status
Simulation time 3042280254 ps
CPU time 62.24 seconds
Started Apr 21 03:51:51 PM PDT 24
Finished Apr 21 03:52:54 PM PDT 24
Peak memory 226700 kb
Host smart-e5aa0290-2c6a-49aa-bd62-e5637cc65cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184393973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1184393973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.677101202
Short name T590
Test name
Test status
Simulation time 18406216928 ps
CPU time 101.92 seconds
Started Apr 21 03:52:15 PM PDT 24
Finished Apr 21 03:53:57 PM PDT 24
Peak memory 243124 kb
Host smart-1fca33bb-6238-4ba4-87c6-1e2bc9d23687
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=677101202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.677101202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.1305118523
Short name T555
Test name
Test status
Simulation time 446689398 ps
CPU time 5.93 seconds
Started Apr 21 03:52:10 PM PDT 24
Finished Apr 21 03:52:16 PM PDT 24
Peak memory 226636 kb
Host smart-418426ce-6f4e-4f8e-88d8-2720ba89de39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305118523 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.kmac_test_vectors_kmac.1305118523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.811375576
Short name T409
Test name
Test status
Simulation time 3081924156 ps
CPU time 5.85 seconds
Started Apr 21 03:52:08 PM PDT 24
Finished Apr 21 03:52:14 PM PDT 24
Peak memory 218684 kb
Host smart-2d4d00c4-8f5a-457a-9ae7-b1800fe5d444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811375576 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.kmac_test_vectors_kmac_xof.811375576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2605806234
Short name T329
Test name
Test status
Simulation time 21994474624 ps
CPU time 2147.15 seconds
Started Apr 21 03:51:55 PM PDT 24
Finished Apr 21 04:27:43 PM PDT 24
Peak memory 402840 kb
Host smart-dc6a1b7b-4090-4e23-81b0-922846f255a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2605806234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2605806234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1070093972
Short name T925
Test name
Test status
Simulation time 192188747375 ps
CPU time 2099.66 seconds
Started Apr 21 03:52:00 PM PDT 24
Finished Apr 21 04:27:00 PM PDT 24
Peak memory 389040 kb
Host smart-bbf1ff9b-9f31-4b14-b8a6-55131c2e9ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1070093972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1070093972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.726954203
Short name T789
Test name
Test status
Simulation time 83174582234 ps
CPU time 1945.18 seconds
Started Apr 21 03:52:01 PM PDT 24
Finished Apr 21 04:24:26 PM PDT 24
Peak memory 340232 kb
Host smart-0b8e10e5-c8af-4ff3-a843-a6dab0ceb1f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=726954203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.726954203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.558591362
Short name T448
Test name
Test status
Simulation time 43913995907 ps
CPU time 1222.83 seconds
Started Apr 21 03:52:03 PM PDT 24
Finished Apr 21 04:12:26 PM PDT 24
Peak memory 298976 kb
Host smart-054b929b-fc13-490b-8449-bb707f26e5bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=558591362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.558591362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.1693826235
Short name T578
Test name
Test status
Simulation time 243309575883 ps
CPU time 5020.76 seconds
Started Apr 21 03:52:04 PM PDT 24
Finished Apr 21 05:15:45 PM PDT 24
Peak memory 658444 kb
Host smart-4bda5f9e-080c-4083-b414-79b66b7eb8c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1693826235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.1693826235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.301142223
Short name T430
Test name
Test status
Simulation time 274633178945 ps
CPU time 4181.65 seconds
Started Apr 21 03:52:06 PM PDT 24
Finished Apr 21 05:01:48 PM PDT 24
Peak memory 556948 kb
Host smart-bebd12e3-327d-45d3-9286-e8c0ef39a38d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=301142223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.301142223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2797032614
Short name T357
Test name
Test status
Simulation time 17687288 ps
CPU time 0.81 seconds
Started Apr 21 03:52:50 PM PDT 24
Finished Apr 21 03:52:51 PM PDT 24
Peak memory 218360 kb
Host smart-f6c949a7-a789-443f-9547-9471aa9f4d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797032614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2797032614 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2226649317
Short name T109
Test name
Test status
Simulation time 50896344259 ps
CPU time 273.74 seconds
Started Apr 21 03:52:40 PM PDT 24
Finished Apr 21 03:57:14 PM PDT 24
Peak memory 244124 kb
Host smart-0a66331a-0767-41e2-9ff1-c3b42d5f64f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226649317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2226649317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.833160006
Short name T872
Test name
Test status
Simulation time 13612674262 ps
CPU time 1563.64 seconds
Started Apr 21 03:52:20 PM PDT 24
Finished Apr 21 04:18:24 PM PDT 24
Peak memory 237348 kb
Host smart-d8a9c545-6249-499b-bc26-9291a77c13e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833160006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.833160006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2330979183
Short name T283
Test name
Test status
Simulation time 3014259855 ps
CPU time 64.9 seconds
Started Apr 21 03:52:42 PM PDT 24
Finished Apr 21 03:53:47 PM PDT 24
Peak memory 229160 kb
Host smart-3a251497-a765-4679-bec2-c44eb4b5614c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330979183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2330979183 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.514386548
Short name T203
Test name
Test status
Simulation time 22461605850 ps
CPU time 334.26 seconds
Started Apr 21 03:52:44 PM PDT 24
Finished Apr 21 03:58:19 PM PDT 24
Peak memory 256812 kb
Host smart-55442ee6-e4bf-48c8-ac6d-a7096ea22931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514386548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.514386548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.3036109224
Short name T115
Test name
Test status
Simulation time 719399250 ps
CPU time 2.6 seconds
Started Apr 21 03:52:48 PM PDT 24
Finished Apr 21 03:52:51 PM PDT 24
Peak memory 218440 kb
Host smart-823a5e90-98da-4584-88b7-72ede8435624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036109224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.3036109224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.1884711326
Short name T71
Test name
Test status
Simulation time 159997404 ps
CPU time 1.46 seconds
Started Apr 21 03:52:49 PM PDT 24
Finished Apr 21 03:52:51 PM PDT 24
Peak memory 218452 kb
Host smart-bddd99a5-9490-422e-b841-2d7c7c1dc857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884711326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1884711326 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.880111472
Short name T413
Test name
Test status
Simulation time 57723997579 ps
CPU time 2045.74 seconds
Started Apr 21 03:52:17 PM PDT 24
Finished Apr 21 04:26:23 PM PDT 24
Peak memory 384724 kb
Host smart-182a862e-d5fa-465b-b925-57d025465bd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880111472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_an
d_output.880111472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.531398624
Short name T222
Test name
Test status
Simulation time 9666095079 ps
CPU time 198.62 seconds
Started Apr 21 03:52:20 PM PDT 24
Finished Apr 21 03:55:39 PM PDT 24
Peak memory 241236 kb
Host smart-23e65bdc-144d-48dd-993d-623e23c7f354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531398624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.531398624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.124267846
Short name T452
Test name
Test status
Simulation time 1251219538 ps
CPU time 8.73 seconds
Started Apr 21 03:52:18 PM PDT 24
Finished Apr 21 03:52:27 PM PDT 24
Peak memory 226632 kb
Host smart-b070a04b-0e9f-4f32-ba8d-dfc7941fe3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124267846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.124267846 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1343470751
Short name T58
Test name
Test status
Simulation time 180856511558 ps
CPU time 1392.87 seconds
Started Apr 21 03:52:51 PM PDT 24
Finished Apr 21 04:16:04 PM PDT 24
Peak memory 374424 kb
Host smart-ab00efc3-0d92-4faa-84a3-622914fbbfd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1343470751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1343470751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.353969384
Short name T541
Test name
Test status
Simulation time 857521398 ps
CPU time 6.2 seconds
Started Apr 21 03:52:34 PM PDT 24
Finished Apr 21 03:52:41 PM PDT 24
Peak memory 219492 kb
Host smart-5dace5ad-708f-45ea-94b2-fb620dde28ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353969384 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.kmac_test_vectors_kmac.353969384 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.3841829710
Short name T191
Test name
Test status
Simulation time 173188865 ps
CPU time 6.62 seconds
Started Apr 21 03:52:38 PM PDT 24
Finished Apr 21 03:52:45 PM PDT 24
Peak memory 219460 kb
Host smart-4593918f-43a0-402b-9580-0d3a059b2441
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841829710 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.3841829710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.3492489288
Short name T473
Test name
Test status
Simulation time 169347167849 ps
CPU time 1931.79 seconds
Started Apr 21 03:52:22 PM PDT 24
Finished Apr 21 04:24:34 PM PDT 24
Peak memory 394560 kb
Host smart-2ad22aeb-2a74-4920-946b-c5e9c8ab568f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3492489288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.3492489288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3236608220
Short name T13
Test name
Test status
Simulation time 22314111708 ps
CPU time 2091.79 seconds
Started Apr 21 03:52:26 PM PDT 24
Finished Apr 21 04:27:18 PM PDT 24
Peak memory 391328 kb
Host smart-695c2b61-3286-4e87-b56d-0879c2530e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3236608220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3236608220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.4085299553
Short name T692
Test name
Test status
Simulation time 31276946657 ps
CPU time 1667.66 seconds
Started Apr 21 03:52:26 PM PDT 24
Finished Apr 21 04:20:14 PM PDT 24
Peak memory 343168 kb
Host smart-c7b3cd24-c7dc-47b9-98d6-c22f95276d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4085299553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.4085299553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.1127415175
Short name T194
Test name
Test status
Simulation time 10713049828 ps
CPU time 1235.23 seconds
Started Apr 21 03:52:29 PM PDT 24
Finished Apr 21 04:13:05 PM PDT 24
Peak memory 302420 kb
Host smart-e5e2423b-91de-4772-9caf-2d3c5b91871d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1127415175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.1127415175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.4106611927
Short name T1008
Test name
Test status
Simulation time 488973091633 ps
CPU time 5746.7 seconds
Started Apr 21 03:52:28 PM PDT 24
Finished Apr 21 05:28:15 PM PDT 24
Peak memory 649748 kb
Host smart-11aca8aa-14bb-4083-ab5c-70730ae25d33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4106611927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.4106611927 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.2982769783
Short name T612
Test name
Test status
Simulation time 608473103242 ps
CPU time 4793.63 seconds
Started Apr 21 03:52:28 PM PDT 24
Finished Apr 21 05:12:22 PM PDT 24
Peak memory 576372 kb
Host smart-120b0498-1e8e-4ffd-b15e-c95eb7012770
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2982769783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2982769783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1609986706
Short name T110
Test name
Test status
Simulation time 71540886 ps
CPU time 0.87 seconds
Started Apr 21 03:53:25 PM PDT 24
Finished Apr 21 03:53:26 PM PDT 24
Peak memory 218340 kb
Host smart-6d0086d8-dd74-47fd-bd54-28d3fa9b47a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609986706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1609986706 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2971816894
Short name T34
Test name
Test status
Simulation time 19561548344 ps
CPU time 339.58 seconds
Started Apr 21 03:53:19 PM PDT 24
Finished Apr 21 03:58:59 PM PDT 24
Peak memory 248940 kb
Host smart-ff9975db-8ce7-41ba-8f0c-d8fe04358c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971816894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2971816894 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.3418584644
Short name T761
Test name
Test status
Simulation time 20639431660 ps
CPU time 840 seconds
Started Apr 21 03:52:58 PM PDT 24
Finished Apr 21 04:06:59 PM PDT 24
Peak memory 238268 kb
Host smart-358cdfe4-9759-42d7-b965-35dc46e3a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418584644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.3418584644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.3579384259
Short name T61
Test name
Test status
Simulation time 7560271773 ps
CPU time 160.44 seconds
Started Apr 21 03:53:21 PM PDT 24
Finished Apr 21 03:56:02 PM PDT 24
Peak memory 238032 kb
Host smart-3569de9b-4954-4a6a-b596-86b597584bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579384259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.3579384259 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.3694990950
Short name T668
Test name
Test status
Simulation time 47646115722 ps
CPU time 236.75 seconds
Started Apr 21 03:53:22 PM PDT 24
Finished Apr 21 03:57:19 PM PDT 24
Peak memory 259468 kb
Host smart-a9691661-0e0f-4875-aaba-e7736b8037ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694990950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.3694990950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.3058772295
Short name T301
Test name
Test status
Simulation time 9410095938 ps
CPU time 4.71 seconds
Started Apr 21 03:53:21 PM PDT 24
Finished Apr 21 03:53:26 PM PDT 24
Peak memory 218508 kb
Host smart-1236a567-8ddc-4faf-a986-dba98f584fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058772295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.3058772295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.1603141321
Short name T803
Test name
Test status
Simulation time 4043434426 ps
CPU time 59.66 seconds
Started Apr 21 03:53:21 PM PDT 24
Finished Apr 21 03:54:21 PM PDT 24
Peak memory 239416 kb
Host smart-7f838c91-c833-4232-bf67-fcef9f08cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603141321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1603141321 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.3034717626
Short name T1042
Test name
Test status
Simulation time 115901981744 ps
CPU time 2848.27 seconds
Started Apr 21 03:52:54 PM PDT 24
Finished Apr 21 04:40:23 PM PDT 24
Peak memory 429852 kb
Host smart-5da46ae9-0a42-4bcf-866b-59acc6fc018b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034717626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.3034717626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.896756957
Short name T508
Test name
Test status
Simulation time 7858000598 ps
CPU time 178.3 seconds
Started Apr 21 03:53:00 PM PDT 24
Finished Apr 21 03:55:59 PM PDT 24
Peak memory 236728 kb
Host smart-81bcf71c-124d-4f9c-b2cf-e5d56f05b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896756957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.896756957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1827087855
Short name T769
Test name
Test status
Simulation time 2946220447 ps
CPU time 74.58 seconds
Started Apr 21 03:52:50 PM PDT 24
Finished Apr 21 03:54:05 PM PDT 24
Peak memory 226668 kb
Host smart-5485a29b-5ecc-4c2b-bcbd-4f624cdd55b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827087855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1827087855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.580757632
Short name T504
Test name
Test status
Simulation time 2870959084 ps
CPU time 101.43 seconds
Started Apr 21 03:53:21 PM PDT 24
Finished Apr 21 03:55:03 PM PDT 24
Peak memory 243128 kb
Host smart-e3f1acca-752f-49a8-beae-986054187ff6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=580757632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.580757632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.1581360353
Short name T296
Test name
Test status
Simulation time 844856429 ps
CPU time 6.25 seconds
Started Apr 21 03:53:14 PM PDT 24
Finished Apr 21 03:53:20 PM PDT 24
Peak memory 218528 kb
Host smart-72c57352-7b6c-414b-8fec-f8eea3b36a7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581360353 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.kmac_test_vectors_kmac.1581360353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1350665515
Short name T529
Test name
Test status
Simulation time 588803399 ps
CPU time 7.22 seconds
Started Apr 21 03:53:14 PM PDT 24
Finished Apr 21 03:53:22 PM PDT 24
Peak memory 226612 kb
Host smart-0e07e37c-4bff-49fa-bcc5-a6936df6a908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350665515 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1350665515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.2106825753
Short name T373
Test name
Test status
Simulation time 139918173224 ps
CPU time 2465.02 seconds
Started Apr 21 03:53:02 PM PDT 24
Finished Apr 21 04:34:08 PM PDT 24
Peak memory 407132 kb
Host smart-d186fd45-03c7-4139-9813-44b0a9728f8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2106825753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2106825753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.1015329881
Short name T487
Test name
Test status
Simulation time 181771449651 ps
CPU time 2176.1 seconds
Started Apr 21 03:53:09 PM PDT 24
Finished Apr 21 04:29:26 PM PDT 24
Peak memory 388656 kb
Host smart-fd676b0a-1936-4d9f-a103-942a579aaf91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1015329881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.1015329881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.2420303588
Short name T802
Test name
Test status
Simulation time 66048829972 ps
CPU time 1797.33 seconds
Started Apr 21 03:53:08 PM PDT 24
Finished Apr 21 04:23:06 PM PDT 24
Peak memory 344672 kb
Host smart-e4b1d644-9a26-4f61-8e98-a23f3947603b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2420303588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.2420303588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1944481386
Short name T625
Test name
Test status
Simulation time 80081775910 ps
CPU time 1275.58 seconds
Started Apr 21 03:53:10 PM PDT 24
Finished Apr 21 04:14:26 PM PDT 24
Peak memory 299464 kb
Host smart-74be9619-0d0d-4982-9883-0b0481d3236f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1944481386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1944481386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.399610498
Short name T204
Test name
Test status
Simulation time 63223117423 ps
CPU time 5359.34 seconds
Started Apr 21 03:53:10 PM PDT 24
Finished Apr 21 05:22:31 PM PDT 24
Peak memory 664260 kb
Host smart-48049f57-714e-43ad-9034-525343add77d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=399610498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.399610498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.2695062166
Short name T560
Test name
Test status
Simulation time 196813639271 ps
CPU time 4949.51 seconds
Started Apr 21 03:53:14 PM PDT 24
Finished Apr 21 05:15:44 PM PDT 24
Peak memory 560056 kb
Host smart-5d4c9b7e-b560-4f71-8858-e3121c1fc84f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2695062166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2695062166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.3178854201
Short name T294
Test name
Test status
Simulation time 53639768 ps
CPU time 0.89 seconds
Started Apr 21 03:53:58 PM PDT 24
Finished Apr 21 03:53:59 PM PDT 24
Peak memory 218344 kb
Host smart-e6c78bd1-0a7f-4217-bf1b-d9a40fb80158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178854201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3178854201 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.2323304377
Short name T635
Test name
Test status
Simulation time 29539576187 ps
CPU time 365.37 seconds
Started Apr 21 03:53:51 PM PDT 24
Finished Apr 21 03:59:57 PM PDT 24
Peak memory 249720 kb
Host smart-5426fc6e-e85a-4202-96a9-6c64ae975843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323304377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.2323304377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.1343239015
Short name T428
Test name
Test status
Simulation time 10751584750 ps
CPU time 297.1 seconds
Started Apr 21 03:53:35 PM PDT 24
Finished Apr 21 03:58:32 PM PDT 24
Peak memory 228364 kb
Host smart-e1a7a5ba-2f1b-4b0b-846d-42b2e221b6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343239015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.1343239015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.4237857912
Short name T695
Test name
Test status
Simulation time 3389428143 ps
CPU time 79.69 seconds
Started Apr 21 03:53:52 PM PDT 24
Finished Apr 21 03:55:12 PM PDT 24
Peak memory 230608 kb
Host smart-4f49c818-afc1-4a48-8051-2a59c4a3773d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237857912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.4237857912 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.2302546983
Short name T349
Test name
Test status
Simulation time 7199269119 ps
CPU time 228.95 seconds
Started Apr 21 03:53:53 PM PDT 24
Finished Apr 21 03:57:42 PM PDT 24
Peak memory 259420 kb
Host smart-38acdea6-ec62-4f9d-b6ed-700e6fbb86aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302546983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.2302546983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.3773358051
Short name T965
Test name
Test status
Simulation time 659409078 ps
CPU time 4.44 seconds
Started Apr 21 03:53:55 PM PDT 24
Finished Apr 21 03:53:59 PM PDT 24
Peak memory 218504 kb
Host smart-1421b840-e91d-4f98-b689-ac30a73c1322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773358051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3773358051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.1447310847
Short name T78
Test name
Test status
Simulation time 3696526583 ps
CPU time 62.96 seconds
Started Apr 21 03:53:57 PM PDT 24
Finished Apr 21 03:55:00 PM PDT 24
Peak memory 239436 kb
Host smart-abe490dd-57bd-4fb2-8e7d-89a5ac47120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447310847 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1447310847 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2260725377
Short name T691
Test name
Test status
Simulation time 49078636070 ps
CPU time 706.59 seconds
Started Apr 21 03:53:25 PM PDT 24
Finished Apr 21 04:05:12 PM PDT 24
Peak memory 275224 kb
Host smart-103fecf7-5bfb-4008-b58b-7250e50a396e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260725377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2260725377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.3667008236
Short name T783
Test name
Test status
Simulation time 7541073093 ps
CPU time 100.79 seconds
Started Apr 21 03:53:26 PM PDT 24
Finished Apr 21 03:55:07 PM PDT 24
Peak memory 231332 kb
Host smart-c93a6a71-364d-4377-8571-a5ec8889ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667008236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.3667008236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.3754521694
Short name T364
Test name
Test status
Simulation time 31013267101 ps
CPU time 51.13 seconds
Started Apr 21 03:53:26 PM PDT 24
Finished Apr 21 03:54:17 PM PDT 24
Peak memory 223668 kb
Host smart-ec2a2678-94fa-4af2-85ac-e7fc49613d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754521694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.3754521694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.1893588039
Short name T930
Test name
Test status
Simulation time 705355043 ps
CPU time 6.4 seconds
Started Apr 21 03:53:49 PM PDT 24
Finished Apr 21 03:53:56 PM PDT 24
Peak memory 226568 kb
Host smart-6fc1ad04-25aa-44fd-8c30-1e245e97e1c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893588039 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.1893588039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2142932564
Short name T440
Test name
Test status
Simulation time 107207348 ps
CPU time 5.59 seconds
Started Apr 21 03:53:51 PM PDT 24
Finished Apr 21 03:53:56 PM PDT 24
Peak memory 218568 kb
Host smart-c0d0f32c-01d0-4a80-9d05-f1e5d1cf7b9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142932564 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2142932564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2407980973
Short name T1000
Test name
Test status
Simulation time 354370214114 ps
CPU time 2151.69 seconds
Started Apr 21 03:53:38 PM PDT 24
Finished Apr 21 04:29:30 PM PDT 24
Peak memory 388176 kb
Host smart-d58d4365-4c6c-4316-b2ab-449a1b45a276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2407980973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2407980973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.4215055423
Short name T158
Test name
Test status
Simulation time 96221145764 ps
CPU time 2303.9 seconds
Started Apr 21 03:53:39 PM PDT 24
Finished Apr 21 04:32:04 PM PDT 24
Peak memory 397824 kb
Host smart-29dc2aae-2e00-47ad-91bd-43b45ce1beec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4215055423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.4215055423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.2101120473
Short name T520
Test name
Test status
Simulation time 198629328517 ps
CPU time 1717.24 seconds
Started Apr 21 03:53:41 PM PDT 24
Finished Apr 21 04:22:18 PM PDT 24
Peak memory 340832 kb
Host smart-31a30ade-0a35-426e-b202-c411718ec910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2101120473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.2101120473 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1650618429
Short name T801
Test name
Test status
Simulation time 366234831927 ps
CPU time 1401.09 seconds
Started Apr 21 03:53:43 PM PDT 24
Finished Apr 21 04:17:05 PM PDT 24
Peak memory 299488 kb
Host smart-871801ae-f246-4827-a78b-9bf848bd07b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1650618429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1650618429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.2084442320
Short name T262
Test name
Test status
Simulation time 246140097472 ps
CPU time 5181.18 seconds
Started Apr 21 03:53:46 PM PDT 24
Finished Apr 21 05:20:08 PM PDT 24
Peak memory 652672 kb
Host smart-2891784d-7f9c-4d4d-bd0d-e5386bc9c827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2084442320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2084442320 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.4022379824
Short name T771
Test name
Test status
Simulation time 830291601349 ps
CPU time 5220.51 seconds
Started Apr 21 03:53:47 PM PDT 24
Finished Apr 21 05:20:49 PM PDT 24
Peak memory 583236 kb
Host smart-ef7df265-33d6-486f-ac2e-34c293abc0f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4022379824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.4022379824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.853892359
Short name T266
Test name
Test status
Simulation time 45708039 ps
CPU time 0.81 seconds
Started Apr 21 03:54:49 PM PDT 24
Finished Apr 21 03:54:51 PM PDT 24
Peak memory 218308 kb
Host smart-c87a13c2-4c98-4b95-87cd-306bda6579a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853892359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.853892359 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.625328141
Short name T903
Test name
Test status
Simulation time 63920053468 ps
CPU time 392.07 seconds
Started Apr 21 03:54:37 PM PDT 24
Finished Apr 21 04:01:10 PM PDT 24
Peak memory 248260 kb
Host smart-36fbf84c-633e-4c35-a557-79e31357a9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625328141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.625328141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.494396066
Short name T723
Test name
Test status
Simulation time 59160266775 ps
CPU time 957.48 seconds
Started Apr 21 03:54:19 PM PDT 24
Finished Apr 21 04:10:17 PM PDT 24
Peak memory 234736 kb
Host smart-809ec036-67e8-4778-ac88-a66b4f84edb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494396066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.494396066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1644199374
Short name T855
Test name
Test status
Simulation time 13203494180 ps
CPU time 220.57 seconds
Started Apr 21 03:54:38 PM PDT 24
Finished Apr 21 03:58:19 PM PDT 24
Peak memory 235352 kb
Host smart-6c42f477-0244-4104-8e59-2c5176146e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644199374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1644199374 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.2812941342
Short name T686
Test name
Test status
Simulation time 2542812740 ps
CPU time 45.52 seconds
Started Apr 21 03:54:41 PM PDT 24
Finished Apr 21 03:55:26 PM PDT 24
Peak memory 243120 kb
Host smart-51a32860-cfac-4ad2-b34e-87b3211661d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812941342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2812941342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.820256040
Short name T1015
Test name
Test status
Simulation time 470625797 ps
CPU time 3.22 seconds
Started Apr 21 03:54:43 PM PDT 24
Finished Apr 21 03:54:46 PM PDT 24
Peak memory 218448 kb
Host smart-0bd763bd-0320-4c03-81d9-8d712f4a6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820256040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.820256040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.2754549835
Short name T1020
Test name
Test status
Simulation time 29556535644 ps
CPU time 1933.86 seconds
Started Apr 21 03:54:07 PM PDT 24
Finished Apr 21 04:26:21 PM PDT 24
Peak memory 386848 kb
Host smart-8cb18bec-c66c-4401-b8ea-38c0a3b80ee9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754549835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.2754549835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1134999365
Short name T546
Test name
Test status
Simulation time 781274241 ps
CPU time 20.74 seconds
Started Apr 21 03:54:15 PM PDT 24
Finished Apr 21 03:54:35 PM PDT 24
Peak memory 227792 kb
Host smart-35d32cc4-7289-4e97-8e5e-ce67d8f553c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134999365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1134999365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.911761521
Short name T675
Test name
Test status
Simulation time 3641519339 ps
CPU time 76.63 seconds
Started Apr 21 03:54:00 PM PDT 24
Finished Apr 21 03:55:17 PM PDT 24
Peak memory 226740 kb
Host smart-4b454ff3-cc72-429b-8f22-244637d07576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911761521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.911761521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.1676761333
Short name T6
Test name
Test status
Simulation time 271224052 ps
CPU time 6.08 seconds
Started Apr 21 03:54:33 PM PDT 24
Finished Apr 21 03:54:39 PM PDT 24
Peak memory 218568 kb
Host smart-74ed15be-c015-44bd-abde-cfe46eb0c55f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676761333 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.1676761333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.2984677896
Short name T494
Test name
Test status
Simulation time 229786682 ps
CPU time 6.8 seconds
Started Apr 21 03:54:37 PM PDT 24
Finished Apr 21 03:54:44 PM PDT 24
Peak memory 218564 kb
Host smart-52806d53-9485-433e-829c-db3b065eac66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984677896 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.2984677896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.755938597
Short name T224
Test name
Test status
Simulation time 66358564002 ps
CPU time 2373.02 seconds
Started Apr 21 03:54:22 PM PDT 24
Finished Apr 21 04:33:56 PM PDT 24
Peak memory 398728 kb
Host smart-9f5dec9c-5175-4a27-8dc1-41c420a9aa3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=755938597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.755938597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1984052197
Short name T952
Test name
Test status
Simulation time 156728941597 ps
CPU time 2012.91 seconds
Started Apr 21 03:54:25 PM PDT 24
Finished Apr 21 04:27:59 PM PDT 24
Peak memory 379368 kb
Host smart-a99a3f37-6a4b-4245-a9c9-77a189141a4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1984052197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1984052197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.270905700
Short name T315
Test name
Test status
Simulation time 196675434762 ps
CPU time 1823.77 seconds
Started Apr 21 03:54:28 PM PDT 24
Finished Apr 21 04:24:53 PM PDT 24
Peak memory 339316 kb
Host smart-d07fab97-e93a-4dc2-99d7-7803c6c59d15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=270905700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.270905700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.374302180
Short name T786
Test name
Test status
Simulation time 53649596121 ps
CPU time 1366.02 seconds
Started Apr 21 03:54:29 PM PDT 24
Finished Apr 21 04:17:15 PM PDT 24
Peak memory 301320 kb
Host smart-5b56bc00-f4a3-4cee-8d26-7ad00549dc44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=374302180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.374302180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.4086944051
Short name T576
Test name
Test status
Simulation time 248221741761 ps
CPU time 5179.59 seconds
Started Apr 21 03:54:29 PM PDT 24
Finished Apr 21 05:20:49 PM PDT 24
Peak memory 647468 kb
Host smart-0eb1ea23-b8f0-4ce3-8f97-f53adc1c396a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4086944051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.4086944051 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.3446345745
Short name T954
Test name
Test status
Simulation time 584014681502 ps
CPU time 4525.34 seconds
Started Apr 21 03:54:32 PM PDT 24
Finished Apr 21 05:09:59 PM PDT 24
Peak memory 578984 kb
Host smart-02c94e74-6c88-48d5-ab3a-082a8064067d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3446345745 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3446345745 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.1031438412
Short name T556
Test name
Test status
Simulation time 56222062 ps
CPU time 0.86 seconds
Started Apr 21 03:55:14 PM PDT 24
Finished Apr 21 03:55:15 PM PDT 24
Peak memory 218352 kb
Host smart-07f918db-d509-4555-bc30-da26e1b5eeb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031438412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.1031438412 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.3282013691
Short name T289
Test name
Test status
Simulation time 4412969972 ps
CPU time 278.49 seconds
Started Apr 21 03:55:13 PM PDT 24
Finished Apr 21 03:59:51 PM PDT 24
Peak memory 248316 kb
Host smart-613e6533-1dd1-428a-b49b-193aee4565f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282013691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.3282013691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.390546448
Short name T705
Test name
Test status
Simulation time 25302729014 ps
CPU time 588.07 seconds
Started Apr 21 03:54:57 PM PDT 24
Finished Apr 21 04:04:46 PM PDT 24
Peak memory 235072 kb
Host smart-f6aeabf7-5a8f-45df-a741-1786b99c5b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390546448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.390546448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.741912868
Short name T59
Test name
Test status
Simulation time 2217389108 ps
CPU time 91.08 seconds
Started Apr 21 03:55:13 PM PDT 24
Finished Apr 21 03:56:45 PM PDT 24
Peak memory 240040 kb
Host smart-dcb18851-cc42-48f5-a4cd-b5590e61e12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741912868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.741912868 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.3306446629
Short name T977
Test name
Test status
Simulation time 8274774960 ps
CPU time 218.86 seconds
Started Apr 21 03:55:13 PM PDT 24
Finished Apr 21 03:58:52 PM PDT 24
Peak memory 253588 kb
Host smart-c0ced009-ffce-40bd-89b0-e896245e3441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306446629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.3306446629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.1394335428
Short name T422
Test name
Test status
Simulation time 213087671 ps
CPU time 1.09 seconds
Started Apr 21 03:55:13 PM PDT 24
Finished Apr 21 03:55:14 PM PDT 24
Peak memory 218348 kb
Host smart-0be4c8ff-40e4-4097-9559-8aea7a86193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394335428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.1394335428 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.2928771409
Short name T650
Test name
Test status
Simulation time 56581559 ps
CPU time 1.68 seconds
Started Apr 21 03:55:13 PM PDT 24
Finished Apr 21 03:55:15 PM PDT 24
Peak memory 219572 kb
Host smart-4f4519ab-6d2c-4484-8644-89d28cd37c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928771409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.2928771409 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.2198808099
Short name T549
Test name
Test status
Simulation time 927504089 ps
CPU time 121.71 seconds
Started Apr 21 03:54:55 PM PDT 24
Finished Apr 21 03:56:57 PM PDT 24
Peak memory 226708 kb
Host smart-712f8863-e302-41f3-915f-fa8355988750
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198808099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.2198808099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.858243064
Short name T605
Test name
Test status
Simulation time 1502747957 ps
CPU time 46.24 seconds
Started Apr 21 03:54:55 PM PDT 24
Finished Apr 21 03:55:41 PM PDT 24
Peak memory 226788 kb
Host smart-60abf803-7449-4dd6-8e13-d3fc1460d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858243064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.858243064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1444857271
Short name T326
Test name
Test status
Simulation time 4756400845 ps
CPU time 48.43 seconds
Started Apr 21 03:54:53 PM PDT 24
Finished Apr 21 03:55:42 PM PDT 24
Peak memory 226656 kb
Host smart-f9b97ee7-b7a6-47fd-8ab1-266cfdec2773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444857271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1444857271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3392312961
Short name T443
Test name
Test status
Simulation time 253231792619 ps
CPU time 1472.42 seconds
Started Apr 21 03:55:12 PM PDT 24
Finished Apr 21 04:19:45 PM PDT 24
Peak memory 375252 kb
Host smart-29124c68-71ef-4bae-9d02-04f90201f88b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3392312961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3392312961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3115468205
Short name T407
Test name
Test status
Simulation time 801895103 ps
CPU time 6.18 seconds
Started Apr 21 03:55:06 PM PDT 24
Finished Apr 21 03:55:13 PM PDT 24
Peak memory 226628 kb
Host smart-27435c89-0746-435f-88c9-3838f4ececc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115468205 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3115468205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.210061060
Short name T480
Test name
Test status
Simulation time 286541996 ps
CPU time 6.49 seconds
Started Apr 21 03:55:07 PM PDT 24
Finished Apr 21 03:55:14 PM PDT 24
Peak memory 218536 kb
Host smart-e8ac15df-711e-47d1-b97a-4299f60b00c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210061060 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.kmac_test_vectors_kmac_xof.210061060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1697387807
Short name T826
Test name
Test status
Simulation time 273450018796 ps
CPU time 2335.18 seconds
Started Apr 21 03:54:58 PM PDT 24
Finished Apr 21 04:33:54 PM PDT 24
Peak memory 396260 kb
Host smart-09f310bd-acca-456d-a464-4d8e7f842b2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1697387807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1697387807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.2599610831
Short name T332
Test name
Test status
Simulation time 39361625517 ps
CPU time 2079.72 seconds
Started Apr 21 03:55:02 PM PDT 24
Finished Apr 21 04:29:42 PM PDT 24
Peak memory 382704 kb
Host smart-94de98b6-954e-4ec3-a1d4-0c267eee3e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2599610831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.2599610831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.3729599197
Short name T586
Test name
Test status
Simulation time 145315776772 ps
CPU time 1935.4 seconds
Started Apr 21 03:55:00 PM PDT 24
Finished Apr 21 04:27:16 PM PDT 24
Peak memory 342796 kb
Host smart-cd8f415d-a879-4fca-87d5-e16e965f5868
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3729599197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.3729599197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2923911381
Short name T1071
Test name
Test status
Simulation time 136805961252 ps
CPU time 1288.85 seconds
Started Apr 21 03:55:03 PM PDT 24
Finished Apr 21 04:16:33 PM PDT 24
Peak memory 298808 kb
Host smart-e26b575b-e63b-4467-96a0-02bbb0067c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2923911381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2923911381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1275379430
Short name T752
Test name
Test status
Simulation time 196368416041 ps
CPU time 5216.89 seconds
Started Apr 21 03:55:08 PM PDT 24
Finished Apr 21 05:22:06 PM PDT 24
Peak memory 654556 kb
Host smart-34dddbd7-3c12-4959-a221-8cc738849b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1275379430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1275379430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.2924178890
Short name T394
Test name
Test status
Simulation time 218690679787 ps
CPU time 4618.17 seconds
Started Apr 21 03:55:06 PM PDT 24
Finished Apr 21 05:12:05 PM PDT 24
Peak memory 569620 kb
Host smart-00f26c83-26bc-48e7-b904-5c669a540734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2924178890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.2924178890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.660303704
Short name T217
Test name
Test status
Simulation time 122117725 ps
CPU time 0.82 seconds
Started Apr 21 03:55:40 PM PDT 24
Finished Apr 21 03:55:41 PM PDT 24
Peak memory 218360 kb
Host smart-d01e7715-12e0-4864-91d7-8fe9294eaa90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660303704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.660303704 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.2649643017
Short name T805
Test name
Test status
Simulation time 13753091429 ps
CPU time 164.86 seconds
Started Apr 21 03:55:32 PM PDT 24
Finished Apr 21 03:58:17 PM PDT 24
Peak memory 243036 kb
Host smart-6f1f7ce5-0f76-4504-8d1e-d144b8c242a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649643017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.2649643017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1355125618
Short name T152
Test name
Test status
Simulation time 42606322389 ps
CPU time 268.79 seconds
Started Apr 21 03:55:21 PM PDT 24
Finished Apr 21 03:59:50 PM PDT 24
Peak memory 237296 kb
Host smart-e1b5762b-da02-4d01-9089-d0c87a333968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355125618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1355125618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.3314906899
Short name T654
Test name
Test status
Simulation time 813951699 ps
CPU time 2.02 seconds
Started Apr 21 03:55:38 PM PDT 24
Finished Apr 21 03:55:40 PM PDT 24
Peak memory 218588 kb
Host smart-a5624443-3d76-4215-aa34-0a43658b9f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314906899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.3314906899 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.666471389
Short name T609
Test name
Test status
Simulation time 34249093431 ps
CPU time 217.48 seconds
Started Apr 21 03:55:33 PM PDT 24
Finished Apr 21 03:59:11 PM PDT 24
Peak memory 259464 kb
Host smart-15694ff0-ec62-4c75-a6d2-c894fad01539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666471389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.666471389 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1144052468
Short name T388
Test name
Test status
Simulation time 16991697850 ps
CPU time 5.87 seconds
Started Apr 21 03:55:37 PM PDT 24
Finished Apr 21 03:55:43 PM PDT 24
Peak memory 218504 kb
Host smart-47ace3a9-f3b4-4e05-b9c1-7ce3ea3be167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144052468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1144052468 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.1232760896
Short name T40
Test name
Test status
Simulation time 38662334 ps
CPU time 1.36 seconds
Started Apr 21 03:55:38 PM PDT 24
Finished Apr 21 03:55:39 PM PDT 24
Peak memory 218352 kb
Host smart-995f1540-1486-4375-8519-acbc965c1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232760896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.1232760896 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.1677937618
Short name T871
Test name
Test status
Simulation time 113502777549 ps
CPU time 3145.05 seconds
Started Apr 21 03:55:18 PM PDT 24
Finished Apr 21 04:47:44 PM PDT 24
Peak memory 451544 kb
Host smart-f765fb96-0491-4616-8398-5fa4cd62a465
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677937618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.1677937618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.552685441
Short name T619
Test name
Test status
Simulation time 30802997473 ps
CPU time 377.16 seconds
Started Apr 21 03:55:18 PM PDT 24
Finished Apr 21 04:01:36 PM PDT 24
Peak memory 252252 kb
Host smart-b602a591-4979-402d-a921-5fdc8c19ec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552685441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.552685441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.880746365
Short name T159
Test name
Test status
Simulation time 18246323447 ps
CPU time 88.2 seconds
Started Apr 21 03:55:19 PM PDT 24
Finished Apr 21 03:56:48 PM PDT 24
Peak memory 222708 kb
Host smart-16952993-2f99-4792-938e-46434799d235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880746365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.880746365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.828680557
Short name T53
Test name
Test status
Simulation time 78103320232 ps
CPU time 1726.04 seconds
Started Apr 21 03:55:37 PM PDT 24
Finished Apr 21 04:24:23 PM PDT 24
Peak memory 322912 kb
Host smart-1cca5e4a-7f9b-4171-849d-3f4b4be004d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=828680557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.828680557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.147607530
Short name T895
Test name
Test status
Simulation time 251332241 ps
CPU time 7.01 seconds
Started Apr 21 03:55:31 PM PDT 24
Finished Apr 21 03:55:38 PM PDT 24
Peak memory 218508 kb
Host smart-9c261fbb-a33c-4a62-9a77-ce17f16e96d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147607530 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.147607530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3861914841
Short name T664
Test name
Test status
Simulation time 202118410 ps
CPU time 6.86 seconds
Started Apr 21 03:55:33 PM PDT 24
Finished Apr 21 03:55:40 PM PDT 24
Peak memory 226620 kb
Host smart-d6d641e3-bb04-4b26-b71b-c333f5ae610a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861914841 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3861914841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.79539765
Short name T553
Test name
Test status
Simulation time 252353295374 ps
CPU time 2276.89 seconds
Started Apr 21 03:55:21 PM PDT 24
Finished Apr 21 04:33:19 PM PDT 24
Peak memory 398908 kb
Host smart-520bceee-ac83-490b-874f-c65cc0209d59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79539765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.79539765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.3885795052
Short name T901
Test name
Test status
Simulation time 76221040419 ps
CPU time 2070.7 seconds
Started Apr 21 03:55:22 PM PDT 24
Finished Apr 21 04:29:53 PM PDT 24
Peak memory 383804 kb
Host smart-0320f6ba-f989-4175-9dcc-fa3efd52ea22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3885795052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.3885795052 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1882092711
Short name T955
Test name
Test status
Simulation time 15549886184 ps
CPU time 1551.62 seconds
Started Apr 21 03:55:24 PM PDT 24
Finished Apr 21 04:21:16 PM PDT 24
Peak memory 343924 kb
Host smart-b427d7cc-b44d-41e3-ac7c-d4c9a14a208f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1882092711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1882092711 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.1660963140
Short name T814
Test name
Test status
Simulation time 72427410216 ps
CPU time 1202.79 seconds
Started Apr 21 03:55:27 PM PDT 24
Finished Apr 21 04:15:30 PM PDT 24
Peak memory 300156 kb
Host smart-a90a45ea-f28f-48ac-b581-834b787dfe44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1660963140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.1660963140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3872848984
Short name T209
Test name
Test status
Simulation time 494351243073 ps
CPU time 5626.82 seconds
Started Apr 21 03:55:29 PM PDT 24
Finished Apr 21 05:29:17 PM PDT 24
Peak memory 651828 kb
Host smart-728712b2-c2cb-4f1a-8303-b69962c45187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3872848984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3872848984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.643838988
Short name T614
Test name
Test status
Simulation time 194564163657 ps
CPU time 4771.58 seconds
Started Apr 21 03:55:31 PM PDT 24
Finished Apr 21 05:15:03 PM PDT 24
Peak memory 564712 kb
Host smart-443c34b6-8661-4181-90fd-a6e74fe5c3c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=643838988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.643838988 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.2845720536
Short name T1032
Test name
Test status
Simulation time 21194480 ps
CPU time 0.83 seconds
Started Apr 21 03:55:56 PM PDT 24
Finished Apr 21 03:55:57 PM PDT 24
Peak memory 220348 kb
Host smart-2a108213-f495-4a72-a9dc-4981ba93c204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845720536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2845720536 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.3282869782
Short name T683
Test name
Test status
Simulation time 4560382302 ps
CPU time 259.31 seconds
Started Apr 21 03:55:48 PM PDT 24
Finished Apr 21 04:00:07 PM PDT 24
Peak memory 242656 kb
Host smart-ad611071-078a-4b58-84eb-18846e04443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282869782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.3282869782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2355649533
Short name T914
Test name
Test status
Simulation time 41453755003 ps
CPU time 1331.79 seconds
Started Apr 21 03:55:43 PM PDT 24
Finished Apr 21 04:17:55 PM PDT 24
Peak memory 238880 kb
Host smart-03910382-159f-460f-a98d-52dfc099bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355649533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2355649533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.656177377
Short name T629
Test name
Test status
Simulation time 26820868967 ps
CPU time 315.23 seconds
Started Apr 21 03:55:51 PM PDT 24
Finished Apr 21 04:01:07 PM PDT 24
Peak memory 247316 kb
Host smart-5648ed59-c92b-4e10-b922-4a00190e15d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656177377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.656177377 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.2776022074
Short name T157
Test name
Test status
Simulation time 158172178 ps
CPU time 12.48 seconds
Started Apr 21 03:55:50 PM PDT 24
Finished Apr 21 03:56:03 PM PDT 24
Peak memory 226332 kb
Host smart-f341ec0c-33d2-42da-b5ea-80df66389a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776022074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2776022074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.2363377269
Short name T588
Test name
Test status
Simulation time 1240446754 ps
CPU time 2.35 seconds
Started Apr 21 03:55:54 PM PDT 24
Finished Apr 21 03:55:56 PM PDT 24
Peak memory 218436 kb
Host smart-e10b1cc8-f195-4310-8ffd-66c174d91a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363377269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.2363377269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1119543226
Short name T989
Test name
Test status
Simulation time 68023761060 ps
CPU time 391.54 seconds
Started Apr 21 03:55:41 PM PDT 24
Finished Apr 21 04:02:12 PM PDT 24
Peak memory 249624 kb
Host smart-80e6674c-d8dd-4b3b-9a54-c2b9502a5a14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119543226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1119543226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3435853065
Short name T912
Test name
Test status
Simulation time 19977196236 ps
CPU time 338.41 seconds
Started Apr 21 03:55:40 PM PDT 24
Finished Apr 21 04:01:18 PM PDT 24
Peak memory 246296 kb
Host smart-88dd2807-d217-4a27-8bc3-337b9c4e8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435853065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3435853065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.305927188
Short name T795
Test name
Test status
Simulation time 3810456669 ps
CPU time 53.86 seconds
Started Apr 21 03:55:40 PM PDT 24
Finished Apr 21 03:56:34 PM PDT 24
Peak memory 226624 kb
Host smart-4199304e-e0a9-4299-b129-3f7087a2cb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305927188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.305927188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.160369193
Short name T122
Test name
Test status
Simulation time 98744141815 ps
CPU time 971.98 seconds
Started Apr 21 03:55:54 PM PDT 24
Finished Apr 21 04:12:07 PM PDT 24
Peak memory 304132 kb
Host smart-49a3d2ee-4d90-40f9-b1ea-8c9cbbdd3512
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=160369193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.160369193 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3648997830
Short name T327
Test name
Test status
Simulation time 860832498 ps
CPU time 6.54 seconds
Started Apr 21 03:55:44 PM PDT 24
Finished Apr 21 03:55:51 PM PDT 24
Peak memory 218568 kb
Host smart-48827be7-40ab-48a8-ad99-09d738aa739b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648997830 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3648997830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.1911235804
Short name T387
Test name
Test status
Simulation time 176071803 ps
CPU time 5.74 seconds
Started Apr 21 03:55:51 PM PDT 24
Finished Apr 21 03:55:57 PM PDT 24
Peak memory 226628 kb
Host smart-ea550838-2c79-458b-95be-c842b9feb066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911235804 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.1911235804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.4147349594
Short name T602
Test name
Test status
Simulation time 42520326144 ps
CPU time 2276.58 seconds
Started Apr 21 03:55:43 PM PDT 24
Finished Apr 21 04:33:40 PM PDT 24
Peak memory 397168 kb
Host smart-09d5122e-770b-4904-aec0-6af064d7230d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4147349594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.4147349594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.3539812868
Short name T375
Test name
Test status
Simulation time 42332975656 ps
CPU time 2044.39 seconds
Started Apr 21 03:55:44 PM PDT 24
Finished Apr 21 04:29:49 PM PDT 24
Peak memory 389076 kb
Host smart-b53881b6-b14d-4cab-bdfe-5ea1f1e60528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3539812868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3539812868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3351063269
Short name T444
Test name
Test status
Simulation time 16012520766 ps
CPU time 1711.56 seconds
Started Apr 21 03:55:45 PM PDT 24
Finished Apr 21 04:24:17 PM PDT 24
Peak memory 341292 kb
Host smart-08173c51-1468-4330-9fac-402c253f05a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3351063269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3351063269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1032815601
Short name T230
Test name
Test status
Simulation time 41887575706 ps
CPU time 1289.76 seconds
Started Apr 21 03:55:46 PM PDT 24
Finished Apr 21 04:17:16 PM PDT 24
Peak memory 302268 kb
Host smart-30691d7c-625b-42f0-b699-9150a7b1017e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1032815601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1032815601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.3815346609
Short name T269
Test name
Test status
Simulation time 320833223307 ps
CPU time 4864.71 seconds
Started Apr 21 03:55:46 PM PDT 24
Finished Apr 21 05:16:52 PM PDT 24
Peak memory 670980 kb
Host smart-368d37c5-8632-43a6-8e5b-a85b2b738b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3815346609 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3815346609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.410746211
Short name T1076
Test name
Test status
Simulation time 139229641719 ps
CPU time 4484.32 seconds
Started Apr 21 03:55:45 PM PDT 24
Finished Apr 21 05:10:29 PM PDT 24
Peak memory 561436 kb
Host smart-15b7ab8c-64a5-4880-a977-6f688a19f2fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=410746211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.410746211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.4285635100
Short name T624
Test name
Test status
Simulation time 13319608 ps
CPU time 0.84 seconds
Started Apr 21 03:56:20 PM PDT 24
Finished Apr 21 03:56:21 PM PDT 24
Peak memory 220320 kb
Host smart-47d3bd22-bbcd-4e0f-aefa-4f9467b081ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285635100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.4285635100 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.415836065
Short name T982
Test name
Test status
Simulation time 4980524292 ps
CPU time 45.2 seconds
Started Apr 21 03:56:11 PM PDT 24
Finished Apr 21 03:56:56 PM PDT 24
Peak memory 227096 kb
Host smart-645d4d5a-71c7-495e-9893-0af2e38e5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415836065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.415836065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.1842294789
Short name T599
Test name
Test status
Simulation time 21664715439 ps
CPU time 133.15 seconds
Started Apr 21 03:56:04 PM PDT 24
Finished Apr 21 03:58:17 PM PDT 24
Peak memory 234800 kb
Host smart-3150dfca-c9ac-40fa-b73f-0a81b1994bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842294789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.1842294789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.1709562521
Short name T344
Test name
Test status
Simulation time 51741319010 ps
CPU time 202.25 seconds
Started Apr 21 03:56:12 PM PDT 24
Finished Apr 21 03:59:35 PM PDT 24
Peak memory 240032 kb
Host smart-5d38ad35-0182-4b40-925e-f133b70859aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709562521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.1709562521 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.3629226374
Short name T945
Test name
Test status
Simulation time 33738484952 ps
CPU time 289.55 seconds
Started Apr 21 03:56:15 PM PDT 24
Finished Apr 21 04:01:05 PM PDT 24
Peak memory 257716 kb
Host smart-b00aed32-3659-4efc-aef7-daf2d313d8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629226374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.3629226374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.2042033408
Short name T883
Test name
Test status
Simulation time 1546642255 ps
CPU time 3.57 seconds
Started Apr 21 03:56:13 PM PDT 24
Finished Apr 21 03:56:17 PM PDT 24
Peak memory 218424 kb
Host smart-9fe767d5-32b2-4965-a1e7-b58543324682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042033408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.2042033408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.3479325407
Short name T877
Test name
Test status
Simulation time 110348569 ps
CPU time 1.52 seconds
Started Apr 21 03:56:14 PM PDT 24
Finished Apr 21 03:56:16 PM PDT 24
Peak memory 218468 kb
Host smart-29a2ff2b-ff94-4418-8900-a80c4e7ace78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479325407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.3479325407 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.3625234520
Short name T240
Test name
Test status
Simulation time 22933945438 ps
CPU time 418.72 seconds
Started Apr 21 03:56:00 PM PDT 24
Finished Apr 21 04:02:59 PM PDT 24
Peak memory 254188 kb
Host smart-5b920da2-99d8-4213-8ef9-f1188eab26f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625234520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.3625234520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.247045156
Short name T117
Test name
Test status
Simulation time 11640027333 ps
CPU time 358.17 seconds
Started Apr 21 03:56:03 PM PDT 24
Finished Apr 21 04:02:01 PM PDT 24
Peak memory 250112 kb
Host smart-c66253f0-8cdb-4595-8659-affe1c602fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247045156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.247045156 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.3680065608
Short name T523
Test name
Test status
Simulation time 2491627985 ps
CPU time 45.47 seconds
Started Apr 21 03:55:56 PM PDT 24
Finished Apr 21 03:56:42 PM PDT 24
Peak memory 226660 kb
Host smart-738bf8cd-bf8a-4445-84ee-327ee7bb1f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680065608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.3680065608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.1756719173
Short name T870
Test name
Test status
Simulation time 13318480568 ps
CPU time 77.02 seconds
Started Apr 21 03:56:19 PM PDT 24
Finished Apr 21 03:57:36 PM PDT 24
Peak memory 242624 kb
Host smart-5ab505da-30a4-4984-a53c-5f263cbb6d83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1756719173 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.1756719173 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_stress_all_with_rand_reset.1960488479
Short name T1057
Test name
Test status
Simulation time 168325819375 ps
CPU time 593.52 seconds
Started Apr 21 03:56:15 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 274716 kb
Host smart-4aecda16-eeaa-4064-85a0-7ad25d0b2143
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1960488479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all_with_rand_reset.1960488479 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.4204631590
Short name T432
Test name
Test status
Simulation time 1093315289 ps
CPU time 6.9 seconds
Started Apr 21 03:56:11 PM PDT 24
Finished Apr 21 03:56:18 PM PDT 24
Peak memory 226616 kb
Host smart-aa9555c7-7cd6-4f5e-bbc8-f1aff487382c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204631590 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.4204631590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.1261484049
Short name T467
Test name
Test status
Simulation time 260283244 ps
CPU time 6.84 seconds
Started Apr 21 03:56:13 PM PDT 24
Finished Apr 21 03:56:20 PM PDT 24
Peak memory 218596 kb
Host smart-0e55a135-dfd5-4d99-8ebb-349cf8c06f70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261484049 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.1261484049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1663918693
Short name T616
Test name
Test status
Simulation time 82938577785 ps
CPU time 1983.92 seconds
Started Apr 21 03:56:04 PM PDT 24
Finished Apr 21 04:29:08 PM PDT 24
Peak memory 389396 kb
Host smart-1e4f534c-6e69-45d6-a7d6-c9a2a91f7d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1663918693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1663918693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.2890715101
Short name T913
Test name
Test status
Simulation time 19930852154 ps
CPU time 1835.72 seconds
Started Apr 21 03:56:11 PM PDT 24
Finished Apr 21 04:26:47 PM PDT 24
Peak memory 384272 kb
Host smart-5f3ff30b-2a75-4417-9935-b1a8a44d11bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2890715101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2890715101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.2817228203
Short name T442
Test name
Test status
Simulation time 30516006782 ps
CPU time 1568.89 seconds
Started Apr 21 03:56:12 PM PDT 24
Finished Apr 21 04:22:21 PM PDT 24
Peak memory 344216 kb
Host smart-b43c52d7-9ec2-4d3d-ac9c-b230230b9c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2817228203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2817228203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.1317312520
Short name T884
Test name
Test status
Simulation time 38173982832 ps
CPU time 1271.28 seconds
Started Apr 21 03:56:11 PM PDT 24
Finished Apr 21 04:17:23 PM PDT 24
Peak memory 304112 kb
Host smart-eb6329b1-b7b1-47d3-b678-e66445b9066f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1317312520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.1317312520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.481640896
Short name T836
Test name
Test status
Simulation time 262534673112 ps
CPU time 6123.87 seconds
Started Apr 21 03:56:11 PM PDT 24
Finished Apr 21 05:38:16 PM PDT 24
Peak memory 667624 kb
Host smart-bd6cc97f-2d96-47e3-893d-413c46834825
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=481640896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.481640896 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.1613851280
Short name T544
Test name
Test status
Simulation time 1382021885819 ps
CPU time 5656.45 seconds
Started Apr 21 03:56:12 PM PDT 24
Finished Apr 21 05:30:30 PM PDT 24
Peak memory 566500 kb
Host smart-3141c5b7-fee5-4829-96e9-cbcb3c9253e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1613851280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1613851280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.1299216433
Short name T557
Test name
Test status
Simulation time 83895594 ps
CPU time 0.86 seconds
Started Apr 21 03:37:58 PM PDT 24
Finished Apr 21 03:38:00 PM PDT 24
Peak memory 218340 kb
Host smart-47d54b8e-6fa5-4e56-8581-0db1e940073f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299216433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1299216433 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2135987833
Short name T1003
Test name
Test status
Simulation time 9573164526 ps
CPU time 61.66 seconds
Started Apr 21 03:37:42 PM PDT 24
Finished Apr 21 03:38:44 PM PDT 24
Peak memory 228480 kb
Host smart-9244c1f3-dcf0-4aa5-ab29-81bc6fe87ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135987833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2135987833 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.170808567
Short name T220
Test name
Test status
Simulation time 87257477 ps
CPU time 5.86 seconds
Started Apr 21 03:37:38 PM PDT 24
Finished Apr 21 03:37:44 PM PDT 24
Peak memory 226604 kb
Host smart-df8286b0-7822-4f5b-8bd0-a1b5b6d30246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170808567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.170808567 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.1096595703
Short name T618
Test name
Test status
Simulation time 158143242995 ps
CPU time 1663.61 seconds
Started Apr 21 03:37:25 PM PDT 24
Finished Apr 21 04:05:09 PM PDT 24
Peak memory 243112 kb
Host smart-2925ea42-a8b9-44df-9bf8-2169b6689554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096595703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.1096595703 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.395003570
Short name T869
Test name
Test status
Simulation time 27069061 ps
CPU time 1.25 seconds
Started Apr 21 03:37:44 PM PDT 24
Finished Apr 21 03:37:45 PM PDT 24
Peak memory 218392 kb
Host smart-1d4dce5f-3bba-407f-8d91-e5449115bab6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=395003570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.395003570 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1007679987
Short name T762
Test name
Test status
Simulation time 34527329 ps
CPU time 1.28 seconds
Started Apr 21 03:37:48 PM PDT 24
Finished Apr 21 03:37:49 PM PDT 24
Peak memory 222012 kb
Host smart-84f70b3b-42a8-41e2-adbd-9fbc6f528d62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007679987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1007679987 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.1324898230
Short name T23
Test name
Test status
Simulation time 4113080727 ps
CPU time 24.92 seconds
Started Apr 21 03:37:49 PM PDT 24
Finished Apr 21 03:38:15 PM PDT 24
Peak memory 226672 kb
Host smart-a315feb8-f196-428f-9882-18f9df229bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324898230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.1324898230 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.400413948
Short name T715
Test name
Test status
Simulation time 24556553089 ps
CPU time 294.76 seconds
Started Apr 21 03:37:38 PM PDT 24
Finished Apr 21 03:42:33 PM PDT 24
Peak memory 248344 kb
Host smart-6459a34e-d7f0-41d4-8080-fd66321c709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400413948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.400413948 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.114426145
Short name T554
Test name
Test status
Simulation time 8766033605 ps
CPU time 55.82 seconds
Started Apr 21 03:37:39 PM PDT 24
Finished Apr 21 03:38:36 PM PDT 24
Peak memory 243020 kb
Host smart-a5353dd9-5c4b-4d31-81ca-1fec3e54faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114426145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.114426145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.3530793883
Short name T632
Test name
Test status
Simulation time 14935208257 ps
CPU time 6.93 seconds
Started Apr 21 03:37:40 PM PDT 24
Finished Apr 21 03:37:48 PM PDT 24
Peak memory 218548 kb
Host smart-41550749-6715-4834-a729-6dc8dcbf470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530793883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3530793883 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.4159739385
Short name T67
Test name
Test status
Simulation time 83000515 ps
CPU time 1.52 seconds
Started Apr 21 03:37:50 PM PDT 24
Finished Apr 21 03:37:51 PM PDT 24
Peak memory 218408 kb
Host smart-371dec1d-b19c-4f4a-80dd-8b2b079ea628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159739385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4159739385 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.1427717818
Short name T401
Test name
Test status
Simulation time 17129251737 ps
CPU time 166.72 seconds
Started Apr 21 03:37:15 PM PDT 24
Finished Apr 21 03:40:02 PM PDT 24
Peak memory 231200 kb
Host smart-4fbf9d3c-8c69-429d-9874-55117236e531
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427717818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.1427717818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3705999943
Short name T949
Test name
Test status
Simulation time 12769001228 ps
CPU time 177.27 seconds
Started Apr 21 03:37:39 PM PDT 24
Finished Apr 21 03:40:36 PM PDT 24
Peak memory 239296 kb
Host smart-61a6a2f5-752f-498a-bf8c-1d7ae3adf8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705999943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3705999943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.1761056318
Short name T744
Test name
Test status
Simulation time 1645105036 ps
CPU time 160.32 seconds
Started Apr 21 03:37:18 PM PDT 24
Finished Apr 21 03:39:59 PM PDT 24
Peak memory 236328 kb
Host smart-72a3eb3c-4a00-48d3-a1c0-6ace535c0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761056318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.1761056318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.989645359
Short name T758
Test name
Test status
Simulation time 25695580924 ps
CPU time 50.35 seconds
Started Apr 21 03:37:07 PM PDT 24
Finished Apr 21 03:37:58 PM PDT 24
Peak memory 226676 kb
Host smart-234c9777-3673-41db-b8b5-58f869bf8216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989645359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.989645359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.1238529032
Short name T998
Test name
Test status
Simulation time 27332319507 ps
CPU time 2163.41 seconds
Started Apr 21 03:37:53 PM PDT 24
Finished Apr 21 04:13:56 PM PDT 24
Peak memory 389040 kb
Host smart-cb323278-b56f-45fa-b0ef-403270892fb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1238529032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.1238529032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.2922986518
Short name T990
Test name
Test status
Simulation time 372918708 ps
CPU time 6.08 seconds
Started Apr 21 03:37:33 PM PDT 24
Finished Apr 21 03:37:39 PM PDT 24
Peak memory 226648 kb
Host smart-cbc4e407-dbfc-4c47-ad25-3fbf333fc994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922986518 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.2922986518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.2214898368
Short name T851
Test name
Test status
Simulation time 843654937 ps
CPU time 6.98 seconds
Started Apr 21 03:37:33 PM PDT 24
Finished Apr 21 03:37:40 PM PDT 24
Peak memory 218636 kb
Host smart-f5c580bb-d89a-4aac-8463-d04deb197df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214898368 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.2214898368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3270630605
Short name T478
Test name
Test status
Simulation time 46545055479 ps
CPU time 1961.53 seconds
Started Apr 21 03:37:25 PM PDT 24
Finished Apr 21 04:10:07 PM PDT 24
Peak memory 401676 kb
Host smart-36e0a996-7299-43d3-9a0a-fd67c363d3df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3270630605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3270630605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.4054195655
Short name T1075
Test name
Test status
Simulation time 30985219649 ps
CPU time 2079.88 seconds
Started Apr 21 03:37:25 PM PDT 24
Finished Apr 21 04:12:05 PM PDT 24
Peak memory 384144 kb
Host smart-2d3deca0-5140-43e6-b505-af24aefd9392
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4054195655 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.4054195655 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.2806062593
Short name T892
Test name
Test status
Simulation time 17763387513 ps
CPU time 1578.12 seconds
Started Apr 21 03:37:29 PM PDT 24
Finished Apr 21 04:03:48 PM PDT 24
Peak memory 333000 kb
Host smart-8d3c8cee-2768-4b1c-996b-ad4fa0f86d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2806062593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2806062593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.737397513
Short name T424
Test name
Test status
Simulation time 45872618487 ps
CPU time 1176.45 seconds
Started Apr 21 03:37:27 PM PDT 24
Finished Apr 21 03:57:03 PM PDT 24
Peak memory 293536 kb
Host smart-462049b8-23f9-4ec8-bea0-d2ced55b78a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=737397513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.737397513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.1373866166
Short name T321
Test name
Test status
Simulation time 254301355944 ps
CPU time 5636.45 seconds
Started Apr 21 03:37:26 PM PDT 24
Finished Apr 21 05:11:23 PM PDT 24
Peak memory 657896 kb
Host smart-8c1c5c35-9dfd-4b3a-8591-158b6c8cd016
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1373866166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1373866166 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.3906519123
Short name T641
Test name
Test status
Simulation time 956583862129 ps
CPU time 5185.01 seconds
Started Apr 21 03:37:31 PM PDT 24
Finished Apr 21 05:03:56 PM PDT 24
Peak memory 571944 kb
Host smart-af803207-55fa-4811-b8ef-b97c825b4509
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3906519123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.3906519123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.2919209387
Short name T785
Test name
Test status
Simulation time 13501321 ps
CPU time 0.86 seconds
Started Apr 21 03:38:34 PM PDT 24
Finished Apr 21 03:38:35 PM PDT 24
Peak memory 218336 kb
Host smart-b5459f29-ff8f-42a7-8d58-cfaed7679bc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919209387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.2919209387 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.4234093430
Short name T172
Test name
Test status
Simulation time 13880409016 ps
CPU time 346.86 seconds
Started Apr 21 03:38:18 PM PDT 24
Finished Apr 21 03:44:05 PM PDT 24
Peak memory 248340 kb
Host smart-1d131e80-29ae-4374-93dc-47c46afd0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234093430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.4234093430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.2185896765
Short name T260
Test name
Test status
Simulation time 29256060156 ps
CPU time 107.04 seconds
Started Apr 21 03:38:20 PM PDT 24
Finished Apr 21 03:40:07 PM PDT 24
Peak memory 233936 kb
Host smart-a3f74ca3-e3f3-471b-8204-fc42ac7e7a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185896765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2185896765 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.1149110920
Short name T933
Test name
Test status
Simulation time 94146645496 ps
CPU time 1266.34 seconds
Started Apr 21 03:38:20 PM PDT 24
Finished Apr 21 03:59:27 PM PDT 24
Peak memory 239784 kb
Host smart-00487972-a180-47b8-b846-570dad81a455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149110920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.1149110920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3320607376
Short name T665
Test name
Test status
Simulation time 153721924 ps
CPU time 1.34 seconds
Started Apr 21 03:38:27 PM PDT 24
Finished Apr 21 03:38:29 PM PDT 24
Peak memory 223396 kb
Host smart-cd1a3ad0-8e12-4c37-bf68-9e31680f00c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3320607376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3320607376 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1770786482
Short name T581
Test name
Test status
Simulation time 25563354 ps
CPU time 1.29 seconds
Started Apr 21 03:38:28 PM PDT 24
Finished Apr 21 03:38:29 PM PDT 24
Peak memory 222192 kb
Host smart-8031ee67-43fe-4374-8dc2-d707f361acf0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1770786482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1770786482 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.2778500080
Short name T377
Test name
Test status
Simulation time 3142705764 ps
CPU time 38.95 seconds
Started Apr 21 03:38:27 PM PDT 24
Finished Apr 21 03:39:07 PM PDT 24
Peak memory 226348 kb
Host smart-4e4b95f2-7175-4588-859a-0312c27cd5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778500080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2778500080 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.651613757
Short name T764
Test name
Test status
Simulation time 8737851474 ps
CPU time 162.46 seconds
Started Apr 21 03:38:19 PM PDT 24
Finished Apr 21 03:41:02 PM PDT 24
Peak memory 237716 kb
Host smart-8766c422-a3e7-49c7-9a91-ba07d0ec47eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651613757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.651613757 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_key_error.1230823626
Short name T113
Test name
Test status
Simulation time 1771532811 ps
CPU time 5.1 seconds
Started Apr 21 03:38:23 PM PDT 24
Finished Apr 21 03:38:28 PM PDT 24
Peak memory 218464 kb
Host smart-4a633bf2-4701-44e5-8a71-19ba417ddbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230823626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1230823626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3588614119
Short name T970
Test name
Test status
Simulation time 75183857 ps
CPU time 1.34 seconds
Started Apr 21 03:38:31 PM PDT 24
Finished Apr 21 03:38:32 PM PDT 24
Peak memory 218412 kb
Host smart-76ba6c14-1e12-4661-b0ed-5c5f3713b852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588614119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3588614119 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2476270153
Short name T980
Test name
Test status
Simulation time 84476036066 ps
CPU time 2214.81 seconds
Started Apr 21 03:38:06 PM PDT 24
Finished Apr 21 04:15:01 PM PDT 24
Peak memory 412876 kb
Host smart-a5e3dc0a-e932-49d2-a465-b51fed55474e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476270153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2476270153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1181883630
Short name T82
Test name
Test status
Simulation time 1805705149 ps
CPU time 11.32 seconds
Started Apr 21 03:38:21 PM PDT 24
Finished Apr 21 03:38:32 PM PDT 24
Peak memory 227892 kb
Host smart-096ef836-f6dd-4a62-924f-17fbe8258f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181883630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1181883630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3926591772
Short name T853
Test name
Test status
Simulation time 28807553895 ps
CPU time 492.46 seconds
Started Apr 21 03:38:06 PM PDT 24
Finished Apr 21 03:46:18 PM PDT 24
Peak memory 253840 kb
Host smart-36e9df1e-0cab-46f2-89b7-465b1380d507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926591772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3926591772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.2520705858
Short name T550
Test name
Test status
Simulation time 9227402832 ps
CPU time 56.81 seconds
Started Apr 21 03:37:58 PM PDT 24
Finished Apr 21 03:38:55 PM PDT 24
Peak memory 226644 kb
Host smart-9b135a8f-7cc8-4bc6-92a5-25231d804e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520705858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.2520705858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.3768771816
Short name T1011
Test name
Test status
Simulation time 357650356604 ps
CPU time 968.77 seconds
Started Apr 21 03:38:32 PM PDT 24
Finished Apr 21 03:54:41 PM PDT 24
Peak memory 325248 kb
Host smart-aae309f7-bb70-4dff-a006-435e67eab373
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3768771816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3768771816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.1508622310
Short name T131
Test name
Test status
Simulation time 36646975177 ps
CPU time 1745.71 seconds
Started Apr 21 03:38:34 PM PDT 24
Finished Apr 21 04:07:40 PM PDT 24
Peak memory 356276 kb
Host smart-e99458bf-2295-4064-b80d-e73334205ae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508622310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.1508622310 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3154038843
Short name T781
Test name
Test status
Simulation time 215694332 ps
CPU time 6.15 seconds
Started Apr 21 03:38:14 PM PDT 24
Finished Apr 21 03:38:20 PM PDT 24
Peak memory 218540 kb
Host smart-c4357aa8-8441-479d-9284-c2cf0f242a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154038843 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3154038843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3463441699
Short name T622
Test name
Test status
Simulation time 516553935 ps
CPU time 6.63 seconds
Started Apr 21 03:38:17 PM PDT 24
Finished Apr 21 03:38:24 PM PDT 24
Peak memory 219564 kb
Host smart-597a7cb9-ede4-4008-9d3d-8195ef906d54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463441699 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3463441699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.1989133153
Short name T1056
Test name
Test status
Simulation time 68091826081 ps
CPU time 2280.68 seconds
Started Apr 21 03:38:11 PM PDT 24
Finished Apr 21 04:16:12 PM PDT 24
Peak memory 395852 kb
Host smart-dab6be63-3659-4f0f-b79f-7e809b967239
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1989133153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.1989133153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.518641467
Short name T1061
Test name
Test status
Simulation time 76205121296 ps
CPU time 2129.6 seconds
Started Apr 21 03:38:12 PM PDT 24
Finished Apr 21 04:13:42 PM PDT 24
Peak memory 381472 kb
Host smart-d5e62077-8b3a-433a-9a9f-f1bf6024019c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=518641467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.518641467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.235778631
Short name T1068
Test name
Test status
Simulation time 30481302850 ps
CPU time 1579.48 seconds
Started Apr 21 03:38:14 PM PDT 24
Finished Apr 21 04:04:34 PM PDT 24
Peak memory 340868 kb
Host smart-ebd94938-1c7c-49ed-adc9-f0cb8d08d229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=235778631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.235778631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.3963100090
Short name T365
Test name
Test status
Simulation time 116962064395 ps
CPU time 1078.89 seconds
Started Apr 21 03:38:14 PM PDT 24
Finished Apr 21 03:56:14 PM PDT 24
Peak memory 300692 kb
Host smart-71f7e486-7566-4030-bbbe-de36ae5416f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3963100090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.3963100090 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.3806735854
Short name T957
Test name
Test status
Simulation time 366312274974 ps
CPU time 5641.46 seconds
Started Apr 21 03:38:16 PM PDT 24
Finished Apr 21 05:12:18 PM PDT 24
Peak memory 650784 kb
Host smart-c1eeb62d-7ce4-4eb7-bfd2-b739b934daf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3806735854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.3806735854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1043214626
Short name T490
Test name
Test status
Simulation time 321156183390 ps
CPU time 5044.12 seconds
Started Apr 21 03:38:16 PM PDT 24
Finished Apr 21 05:02:21 PM PDT 24
Peak memory 565316 kb
Host smart-251aa3c0-8e29-49eb-8771-add65ce067a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1043214626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1043214626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.2694730580
Short name T151
Test name
Test status
Simulation time 36411579 ps
CPU time 0.84 seconds
Started Apr 21 03:38:58 PM PDT 24
Finished Apr 21 03:38:59 PM PDT 24
Peak memory 218344 kb
Host smart-5ad7d374-f8b5-4bd0-bdaf-66d890c9be4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694730580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.2694730580 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.2049268931
Short name T439
Test name
Test status
Simulation time 159723123640 ps
CPU time 332.58 seconds
Started Apr 21 03:38:53 PM PDT 24
Finished Apr 21 03:44:26 PM PDT 24
Peak memory 247036 kb
Host smart-07f88e69-c908-4758-be90-9be58ad28cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049268931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.2049268931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1276719165
Short name T510
Test name
Test status
Simulation time 60055523748 ps
CPU time 345.43 seconds
Started Apr 21 03:38:53 PM PDT 24
Finished Apr 21 03:44:38 PM PDT 24
Peak memory 248032 kb
Host smart-86dcc969-2a1c-44f2-a255-2d07b66e353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276719165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1276719165 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.2739289573
Short name T404
Test name
Test status
Simulation time 28559468499 ps
CPU time 612.56 seconds
Started Apr 21 03:38:43 PM PDT 24
Finished Apr 21 03:48:56 PM PDT 24
Peak memory 232512 kb
Host smart-6bdbb4c6-cad9-4088-ac05-9a9da66dc5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739289573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.2739289573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.2685406473
Short name T839
Test name
Test status
Simulation time 37505466 ps
CPU time 1.07 seconds
Started Apr 21 03:38:56 PM PDT 24
Finished Apr 21 03:38:58 PM PDT 24
Peak memory 218412 kb
Host smart-76161e3a-2595-4083-aa27-2019ec9536a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2685406473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.2685406473 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1100641929
Short name T718
Test name
Test status
Simulation time 34676665 ps
CPU time 1.18 seconds
Started Apr 21 03:38:57 PM PDT 24
Finished Apr 21 03:38:59 PM PDT 24
Peak memory 221808 kb
Host smart-99dcae58-f65b-4452-9f47-f9d1871f0af9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1100641929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1100641929 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.1191171275
Short name T1030
Test name
Test status
Simulation time 6742912172 ps
CPU time 71.81 seconds
Started Apr 21 03:38:57 PM PDT 24
Finished Apr 21 03:40:09 PM PDT 24
Peak memory 220440 kb
Host smart-02afb2a0-e23d-48ff-8a61-fc3968d82353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191171275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1191171275 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.265138598
Short name T369
Test name
Test status
Simulation time 9389609656 ps
CPU time 341.35 seconds
Started Apr 21 03:38:55 PM PDT 24
Finished Apr 21 03:44:36 PM PDT 24
Peak memory 249800 kb
Host smart-d9ecd7be-050e-402d-9f0a-3afd34e517b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265138598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.265138598 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.1435916214
Short name T573
Test name
Test status
Simulation time 12261261422 ps
CPU time 343.82 seconds
Started Apr 21 03:38:54 PM PDT 24
Finished Apr 21 03:44:39 PM PDT 24
Peak memory 259436 kb
Host smart-816b9e6d-0423-49a3-a0a8-6a1a00563130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435916214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.1435916214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.4165471682
Short name T274
Test name
Test status
Simulation time 1096637610 ps
CPU time 3.56 seconds
Started Apr 21 03:38:55 PM PDT 24
Finished Apr 21 03:38:59 PM PDT 24
Peak memory 218444 kb
Host smart-f2b75a0f-2d8e-492f-8c5c-d288da1e5c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165471682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.4165471682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.2778168200
Short name T1049
Test name
Test status
Simulation time 121354396182 ps
CPU time 1687.13 seconds
Started Apr 21 03:38:40 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 341272 kb
Host smart-d5102981-48bb-446e-9219-1382ae1be1ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778168200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.2778168200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.1832198680
Short name T585
Test name
Test status
Simulation time 1328665948 ps
CPU time 3.55 seconds
Started Apr 21 03:38:55 PM PDT 24
Finished Apr 21 03:38:58 PM PDT 24
Peak memory 221040 kb
Host smart-c96ec90e-a925-4113-b2de-b77116f7aa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832198680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.1832198680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3409191865
Short name T888
Test name
Test status
Simulation time 20005132768 ps
CPU time 525.33 seconds
Started Apr 21 03:38:35 PM PDT 24
Finished Apr 21 03:47:20 PM PDT 24
Peak memory 255152 kb
Host smart-e9360594-aed6-405c-9f41-6a163e5b2701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409191865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3409191865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.1858122953
Short name T277
Test name
Test status
Simulation time 4597999651 ps
CPU time 24.99 seconds
Started Apr 21 03:38:35 PM PDT 24
Finished Apr 21 03:39:00 PM PDT 24
Peak memory 226652 kb
Host smart-9f5429ae-f537-487d-9e1b-89a68b640aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858122953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1858122953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.4074752796
Short name T720
Test name
Test status
Simulation time 805535187723 ps
CPU time 4360.52 seconds
Started Apr 21 03:39:00 PM PDT 24
Finished Apr 21 04:51:42 PM PDT 24
Peak memory 566404 kb
Host smart-87ab88f4-25b2-4ff0-9707-70f245ffa4ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4074752796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.4074752796 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.1439730996
Short name T1026
Test name
Test status
Simulation time 246222868 ps
CPU time 6.56 seconds
Started Apr 21 03:38:52 PM PDT 24
Finished Apr 21 03:38:58 PM PDT 24
Peak memory 219460 kb
Host smart-eca508ea-3d9e-40cc-a790-6f8a97d299c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439730996 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.1439730996 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1013298336
Short name T702
Test name
Test status
Simulation time 2388927471 ps
CPU time 7.52 seconds
Started Apr 21 03:38:52 PM PDT 24
Finished Apr 21 03:38:59 PM PDT 24
Peak memory 219588 kb
Host smart-66ccb312-ff78-43fc-832f-4ef7db3d7ff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013298336 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1013298336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.3669634083
Short name T449
Test name
Test status
Simulation time 83530995533 ps
CPU time 2033.98 seconds
Started Apr 21 03:38:45 PM PDT 24
Finished Apr 21 04:12:40 PM PDT 24
Peak memory 391756 kb
Host smart-c4f669a6-ee9f-4bb2-8fc1-293deb5c2fa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3669634083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.3669634083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3829798619
Short name T83
Test name
Test status
Simulation time 512149029472 ps
CPU time 2266.66 seconds
Started Apr 21 03:38:46 PM PDT 24
Finished Apr 21 04:16:33 PM PDT 24
Peak memory 385356 kb
Host smart-bfdd91da-835e-4337-8504-4902084eedd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3829798619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3829798619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2262743827
Short name T484
Test name
Test status
Simulation time 71261084905 ps
CPU time 1776.21 seconds
Started Apr 21 03:38:50 PM PDT 24
Finished Apr 21 04:08:27 PM PDT 24
Peak memory 340612 kb
Host smart-82a10605-4fe6-4c31-b998-028de9006482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2262743827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2262743827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.1823315724
Short name T381
Test name
Test status
Simulation time 54771644398 ps
CPU time 1405.95 seconds
Started Apr 21 03:38:50 PM PDT 24
Finished Apr 21 04:02:16 PM PDT 24
Peak memory 304940 kb
Host smart-df3caff9-9c18-458e-a75f-7c3444336829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1823315724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1823315724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.229016877
Short name T562
Test name
Test status
Simulation time 177691602154 ps
CPU time 5727.25 seconds
Started Apr 21 03:38:52 PM PDT 24
Finished Apr 21 05:14:20 PM PDT 24
Peak memory 664496 kb
Host smart-6436bee6-b85d-45c1-9336-c762ad081d82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=229016877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.229016877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.2129939651
Short name T310
Test name
Test status
Simulation time 94657423928 ps
CPU time 4388.33 seconds
Started Apr 21 03:38:57 PM PDT 24
Finished Apr 21 04:52:06 PM PDT 24
Peak memory 560188 kb
Host smart-ed4e5797-d26f-4b69-800a-c6ffec06aa11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2129939651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.2129939651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.2318631304
Short name T291
Test name
Test status
Simulation time 122784325 ps
CPU time 0.87 seconds
Started Apr 21 03:39:31 PM PDT 24
Finished Apr 21 03:39:32 PM PDT 24
Peak memory 218328 kb
Host smart-748fa822-198f-4935-ba85-e16456f6a935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318631304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2318631304 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.2302948586
Short name T1002
Test name
Test status
Simulation time 13778001821 ps
CPU time 93.99 seconds
Started Apr 21 03:39:27 PM PDT 24
Finished Apr 21 03:41:02 PM PDT 24
Peak memory 232428 kb
Host smart-3d722896-5d62-4d2f-ae5b-d2f73ece486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302948586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2302948586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1624865616
Short name T633
Test name
Test status
Simulation time 13560504640 ps
CPU time 155.79 seconds
Started Apr 21 03:39:28 PM PDT 24
Finished Apr 21 03:42:04 PM PDT 24
Peak memory 235120 kb
Host smart-8e121fa8-7592-437f-a2ba-d7a4365f96c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624865616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1624865616 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.3609931345
Short name T108
Test name
Test status
Simulation time 9671624988 ps
CPU time 838.24 seconds
Started Apr 21 03:39:08 PM PDT 24
Finished Apr 21 03:53:06 PM PDT 24
Peak memory 233748 kb
Host smart-59c05cc8-eea0-4213-b335-0c4ab6de161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609931345 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3609931345 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.3389565394
Short name T248
Test name
Test status
Simulation time 3297085518 ps
CPU time 29.05 seconds
Started Apr 21 03:39:30 PM PDT 24
Finished Apr 21 03:40:00 PM PDT 24
Peak memory 227108 kb
Host smart-c305295d-ffbf-4e40-8b6c-85ffa8c86c31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3389565394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.3389565394 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.44319827
Short name T887
Test name
Test status
Simulation time 3277911446 ps
CPU time 16.12 seconds
Started Apr 21 03:39:29 PM PDT 24
Finished Apr 21 03:39:46 PM PDT 24
Peak memory 234744 kb
Host smart-1142e172-1f84-417b-8be5-bf97a5d3f25d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=44319827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.44319827 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.1490916164
Short name T25
Test name
Test status
Simulation time 8951029434 ps
CPU time 46.51 seconds
Started Apr 21 03:39:30 PM PDT 24
Finished Apr 21 03:40:17 PM PDT 24
Peak memory 219204 kb
Host smart-a521974d-a822-4013-99e7-44a9812e97e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490916164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.1490916164 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2396912816
Short name T757
Test name
Test status
Simulation time 4342302115 ps
CPU time 239.92 seconds
Started Apr 21 03:39:28 PM PDT 24
Finished Apr 21 03:43:28 PM PDT 24
Peak memory 246512 kb
Host smart-7fc2c043-b791-44a5-b66e-01107b1c92d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396912816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2396912816 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.982668002
Short name T946
Test name
Test status
Simulation time 18483412668 ps
CPU time 470.66 seconds
Started Apr 21 03:39:28 PM PDT 24
Finished Apr 21 03:47:19 PM PDT 24
Peak memory 259508 kb
Host smart-7ce525eb-ce8f-43b3-9f1b-30e1a3b5e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982668002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.982668002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.4019810612
Short name T405
Test name
Test status
Simulation time 1030007761 ps
CPU time 3.28 seconds
Started Apr 21 03:39:30 PM PDT 24
Finished Apr 21 03:39:34 PM PDT 24
Peak memory 218444 kb
Host smart-529638f6-c173-4147-ae9d-5d048a1149b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019810612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.4019810612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.2334008882
Short name T121
Test name
Test status
Simulation time 31146120 ps
CPU time 1.18 seconds
Started Apr 21 03:39:30 PM PDT 24
Finished Apr 21 03:39:32 PM PDT 24
Peak memory 218464 kb
Host smart-e711f9da-22ec-46bf-9f47-5797b26da195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334008882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.2334008882 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.1467591252
Short name T792
Test name
Test status
Simulation time 111130510683 ps
CPU time 1444.85 seconds
Started Apr 21 03:39:08 PM PDT 24
Finished Apr 21 04:03:13 PM PDT 24
Peak memory 333408 kb
Host smart-e8574115-b20e-4240-9f18-a50444e77582
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467591252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.1467591252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.511642107
Short name T843
Test name
Test status
Simulation time 24364559876 ps
CPU time 410.95 seconds
Started Apr 21 03:39:31 PM PDT 24
Finished Apr 21 03:46:22 PM PDT 24
Peak memory 252604 kb
Host smart-7bb2095f-7d19-4fea-9970-b35a8fcae068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511642107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.511642107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.91882252
Short name T979
Test name
Test status
Simulation time 19967613637 ps
CPU time 269.45 seconds
Started Apr 21 03:39:03 PM PDT 24
Finished Apr 21 03:43:33 PM PDT 24
Peak memory 242924 kb
Host smart-90db86ce-ff23-4b20-af54-5343cdb01e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91882252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.91882252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3714206851
Short name T570
Test name
Test status
Simulation time 1759964800 ps
CPU time 64.89 seconds
Started Apr 21 03:39:02 PM PDT 24
Finished Apr 21 03:40:07 PM PDT 24
Peak memory 226616 kb
Host smart-76a8af1f-9769-4bb9-94fd-63a7ed348807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714206851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3714206851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.817757519
Short name T916
Test name
Test status
Simulation time 213682451804 ps
CPU time 1939.92 seconds
Started Apr 21 03:39:30 PM PDT 24
Finished Apr 21 04:11:51 PM PDT 24
Peak memory 406744 kb
Host smart-34318447-c80d-48ed-8159-b459425bd4c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=817757519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.817757519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.1083904590
Short name T493
Test name
Test status
Simulation time 511302732 ps
CPU time 6.95 seconds
Started Apr 21 03:39:26 PM PDT 24
Finished Apr 21 03:39:33 PM PDT 24
Peak memory 218536 kb
Host smart-0163df3a-326d-4c95-b7a2-837e98b2a8f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083904590 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.1083904590 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.51795264
Short name T993
Test name
Test status
Simulation time 415170895 ps
CPU time 5.55 seconds
Started Apr 21 03:39:33 PM PDT 24
Finished Apr 21 03:39:39 PM PDT 24
Peak memory 218524 kb
Host smart-fdaf096b-23c0-468e-b04c-b307f76d9e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51795264 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.kmac_test_vectors_kmac_xof.51795264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.1752310509
Short name T1010
Test name
Test status
Simulation time 439436185241 ps
CPU time 2548.74 seconds
Started Apr 21 03:39:07 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 395844 kb
Host smart-6ecde878-c128-423a-a0c8-5763c748c5ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1752310509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1752310509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.3803860548
Short name T589
Test name
Test status
Simulation time 21363469383 ps
CPU time 1728.69 seconds
Started Apr 21 03:39:11 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 388972 kb
Host smart-922279a3-a1d5-4cd1-a7dd-12f34a8ed80e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3803860548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.3803860548 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.3078606482
Short name T847
Test name
Test status
Simulation time 31173134415 ps
CPU time 1606.43 seconds
Started Apr 21 03:39:16 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 342116 kb
Host smart-67c29472-7d19-4e5d-80a9-6de9aa4cd683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3078606482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.3078606482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.370424952
Short name T534
Test name
Test status
Simulation time 12325451498 ps
CPU time 1244.82 seconds
Started Apr 21 03:39:16 PM PDT 24
Finished Apr 21 04:00:01 PM PDT 24
Peak memory 297136 kb
Host smart-010ae616-7263-4f86-b7dd-5a5f876855ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=370424952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.370424952 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.1607557130
Short name T671
Test name
Test status
Simulation time 184169956830 ps
CPU time 5641.51 seconds
Started Apr 21 03:39:21 PM PDT 24
Finished Apr 21 05:13:23 PM PDT 24
Peak memory 651772 kb
Host smart-e6050245-12f4-4766-b988-cb4d4339fbe1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1607557130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.1607557130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.3260348135
Short name T234
Test name
Test status
Simulation time 245486191132 ps
CPU time 4199.44 seconds
Started Apr 21 03:39:26 PM PDT 24
Finished Apr 21 04:49:26 PM PDT 24
Peak memory 569904 kb
Host smart-d0c9efd6-f2c1-4555-8c44-8815f6b60edb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3260348135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.3260348135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.1940665039
Short name T254
Test name
Test status
Simulation time 15617603 ps
CPU time 0.85 seconds
Started Apr 21 03:40:16 PM PDT 24
Finished Apr 21 03:40:17 PM PDT 24
Peak memory 218344 kb
Host smart-0fc9b35a-b6ca-446e-830a-0a800939ebf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940665039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.1940665039 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.677074084
Short name T1029
Test name
Test status
Simulation time 42926450181 ps
CPU time 330.39 seconds
Started Apr 21 03:40:00 PM PDT 24
Finished Apr 21 03:45:31 PM PDT 24
Peak memory 248084 kb
Host smart-19d2a901-8d1f-46b6-9043-6c7e5305219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677074084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.677074084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.2987410339
Short name T776
Test name
Test status
Simulation time 176878956993 ps
CPU time 268.81 seconds
Started Apr 21 03:40:03 PM PDT 24
Finished Apr 21 03:44:32 PM PDT 24
Peak memory 243088 kb
Host smart-68d71443-92bc-4a9d-a0b4-1d22621d61a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987410339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2987410339 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.451976870
Short name T997
Test name
Test status
Simulation time 11988446652 ps
CPU time 688.15 seconds
Started Apr 21 03:39:34 PM PDT 24
Finished Apr 21 03:51:02 PM PDT 24
Peak memory 234116 kb
Host smart-5b9e4662-933e-41b1-a7b3-e1087324e62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451976870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.451976870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.3398128936
Short name T1047
Test name
Test status
Simulation time 675542328 ps
CPU time 15.92 seconds
Started Apr 21 03:40:03 PM PDT 24
Finished Apr 21 03:40:19 PM PDT 24
Peak memory 220272 kb
Host smart-56272e1c-5360-4dfa-a024-6049012f2c1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3398128936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3398128936 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2942342458
Short name T601
Test name
Test status
Simulation time 62141498 ps
CPU time 1.02 seconds
Started Apr 21 03:40:04 PM PDT 24
Finished Apr 21 03:40:06 PM PDT 24
Peak memory 221600 kb
Host smart-cf8da9cf-05fa-4f72-a8de-1f4b5213d692
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2942342458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2942342458 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.2648589794
Short name T382
Test name
Test status
Simulation time 2770539099 ps
CPU time 10.44 seconds
Started Apr 21 03:40:08 PM PDT 24
Finished Apr 21 03:40:19 PM PDT 24
Peak memory 218624 kb
Host smart-caabc9ea-60ec-40d2-8aa1-47628c2e96d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648589794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.2648589794 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_error.3220609926
Short name T118
Test name
Test status
Simulation time 6238838788 ps
CPU time 192.34 seconds
Started Apr 21 03:40:02 PM PDT 24
Finished Apr 21 03:43:15 PM PDT 24
Peak memory 243076 kb
Host smart-ab6af732-d005-4e78-9ada-7210f0a470cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220609926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3220609926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.2980158062
Short name T16
Test name
Test status
Simulation time 789112358 ps
CPU time 4.56 seconds
Started Apr 21 03:40:04 PM PDT 24
Finished Apr 21 03:40:09 PM PDT 24
Peak memory 218452 kb
Host smart-9bc407bb-7e10-41dc-a200-1b34a60a87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980158062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2980158062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.3314314657
Short name T775
Test name
Test status
Simulation time 73103533 ps
CPU time 1.59 seconds
Started Apr 21 03:40:12 PM PDT 24
Finished Apr 21 03:40:14 PM PDT 24
Peak memory 218440 kb
Host smart-31bbdd2f-634d-4229-abdd-14046212ecd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314314657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3314314657 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.3093091201
Short name T551
Test name
Test status
Simulation time 47567575035 ps
CPU time 1641.32 seconds
Started Apr 21 03:39:34 PM PDT 24
Finished Apr 21 04:06:56 PM PDT 24
Peak memory 360232 kb
Host smart-0a6a3149-36d9-4270-bd61-c87bddaa3733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093091201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.3093091201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.1170898235
Short name T392
Test name
Test status
Simulation time 545511663 ps
CPU time 41.37 seconds
Started Apr 21 03:40:03 PM PDT 24
Finished Apr 21 03:40:45 PM PDT 24
Peak memory 226696 kb
Host smart-55ad5e14-db31-43fd-a7dd-e3e7e9c0148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170898235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1170898235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.1155628527
Short name T219
Test name
Test status
Simulation time 6987473136 ps
CPU time 242.77 seconds
Started Apr 21 03:39:34 PM PDT 24
Finished Apr 21 03:43:37 PM PDT 24
Peak memory 240640 kb
Host smart-5c5a9c8e-7fa8-4dee-bed1-363e674fb321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155628527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1155628527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.985374772
Short name T1053
Test name
Test status
Simulation time 293962133 ps
CPU time 12.18 seconds
Started Apr 21 03:39:31 PM PDT 24
Finished Apr 21 03:39:44 PM PDT 24
Peak memory 226172 kb
Host smart-7072dc89-eb5e-432b-bc49-c296299deaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985374772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.985374772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.74304149
Short name T856
Test name
Test status
Simulation time 4513072580 ps
CPU time 256.63 seconds
Started Apr 21 03:40:18 PM PDT 24
Finished Apr 21 03:44:35 PM PDT 24
Peak memory 276068 kb
Host smart-97bbf5d6-49c2-4a5a-9875-0fa13790e354
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=74304149 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.74304149 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3949494492
Short name T531
Test name
Test status
Simulation time 478094408 ps
CPU time 6.52 seconds
Started Apr 21 03:39:52 PM PDT 24
Finished Apr 21 03:39:59 PM PDT 24
Peak memory 226608 kb
Host smart-e4645cc5-7667-41d7-8b98-efa82de0232e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949494492 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3949494492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3440479814
Short name T747
Test name
Test status
Simulation time 1471584049 ps
CPU time 7.17 seconds
Started Apr 21 03:39:55 PM PDT 24
Finished Apr 21 03:40:02 PM PDT 24
Peak memory 218560 kb
Host smart-e9a59fec-824e-4e8a-aa20-f852cea1e056
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440479814 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3440479814 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.1471521545
Short name T796
Test name
Test status
Simulation time 22764915232 ps
CPU time 1931.85 seconds
Started Apr 21 03:39:37 PM PDT 24
Finished Apr 21 04:11:49 PM PDT 24
Peak memory 395636 kb
Host smart-0b05d9be-2934-4bd0-a32b-879e0b38458b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1471521545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1471521545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2832634460
Short name T968
Test name
Test status
Simulation time 18773830079 ps
CPU time 1810.55 seconds
Started Apr 21 03:39:43 PM PDT 24
Finished Apr 21 04:09:54 PM PDT 24
Peak memory 374000 kb
Host smart-a2dbebf6-b225-488f-b6fb-aa3f4b2af359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2832634460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2832634460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.639110447
Short name T921
Test name
Test status
Simulation time 29965316602 ps
CPU time 1605.81 seconds
Started Apr 21 03:39:41 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 340192 kb
Host smart-28ac2ef5-4eb1-4ffc-a5ee-87f3b647dad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=639110447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.639110447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.3750487198
Short name T412
Test name
Test status
Simulation time 85144050925 ps
CPU time 1219.02 seconds
Started Apr 21 03:39:42 PM PDT 24
Finished Apr 21 04:00:02 PM PDT 24
Peak memory 299496 kb
Host smart-473a330b-10d2-446f-82a6-21a5b1ce6a47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3750487198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.3750487198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.411029050
Short name T496
Test name
Test status
Simulation time 232746084136 ps
CPU time 4946.17 seconds
Started Apr 21 03:39:43 PM PDT 24
Finished Apr 21 05:02:10 PM PDT 24
Peak memory 673644 kb
Host smart-5e814bdc-76f6-49ca-a7a3-b24b75bb8162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=411029050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.411029050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3104607601
Short name T696
Test name
Test status
Simulation time 222175367257 ps
CPU time 4349.68 seconds
Started Apr 21 03:39:51 PM PDT 24
Finished Apr 21 04:52:21 PM PDT 24
Peak memory 589420 kb
Host smart-fc08460f-4983-4c96-a34a-10b0ce34c77e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3104607601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3104607601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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