Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100169899	1			T1	225561		T2	1863		T3	254
all_values[1]	100169899	1			T1	225561		T2	1863		T3	254
all_values[2]	100169899	1			T1	225561		T2	1863		T3	254

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

522919

1

T1

15

T2

16

T3

8

auto[1]

299986778

1

T1

676668

T2

5573

T3

754

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298982580

1

T1

674916

T2

4818

T3

720

auto[1]

1527117

1

T1

1767

T2

771

T3

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	154336	1			T2	14		T3	6		T10	1
all_values[0]	auto[0]	auto[1]	1861	1			T2	2		T3	2		T10	2
all_values[0]	auto[1]	auto[0]	99506524	1			T1	224972		T2	1592		T3	234
all_values[0]	auto[1]	auto[1]	507178	1			T1	589		T2	255		T3	12
all_values[1]	auto[0]	auto[0]	198607	1			T1	2		T4	242		T10	4
all_values[1]	auto[0]	auto[1]	1527	1			T1	1		T4	1		T10	3
all_values[1]	auto[1]	auto[0]	99462253	1			T1	224970		T2	1606		T3	240
all_values[1]	auto[1]	auto[1]	507512	1			T1	588		T2	257		T3	14
all_values[2]	auto[0]	auto[0]	165093	1			T1	8		T4	242		T10	1
all_values[2]	auto[0]	auto[1]	1495	1			T1	4		T4	1		T10	2
all_values[2]	auto[1]	auto[0]	99495767	1			T1	224964		T2	1606		T3	240
all_values[2]	auto[1]	auto[1]	507544	1			T1	585		T2	257		T3	14