Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335790 |
1 |
|
|
T1 |
780 |
|
T2 |
352 |
|
T3 |
2 |
auto[1] |
356444 |
1 |
|
|
T3 |
16 |
|
T4 |
2 |
|
T12 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173785 |
1 |
|
|
T1 |
196 |
|
T2 |
94 |
|
T3 |
2 |
lower_val |
170316 |
1 |
|
|
T1 |
196 |
|
T2 |
84 |
|
T3 |
5 |
zero_val |
1737 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
255860 |
1 |
|
|
T1 |
422 |
|
T2 |
170 |
|
T3 |
6 |
lower_val |
257284 |
1 |
|
|
T1 |
358 |
|
T2 |
182 |
|
T3 |
6 |
zero_val |
179090 |
1 |
|
|
T3 |
6 |
|
T12 |
402 |
|
T22 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42128 |
1 |
|
|
T1 |
111 |
|
T2 |
48 |
|
T4 |
1 |
higher_val |
higher_val |
auto[1] |
22432 |
1 |
|
|
T3 |
2 |
|
T12 |
37 |
|
T44 |
45 |
higher_val |
lower_val |
auto[0] |
42044 |
1 |
|
|
T1 |
85 |
|
T2 |
46 |
|
T5 |
3 |
higher_val |
lower_val |
auto[1] |
22199 |
1 |
|
|
T4 |
1 |
|
T12 |
44 |
|
T44 |
36 |
higher_val |
zero_val |
auto[0] |
94 |
1 |
|
|
T31 |
1 |
|
T32 |
2 |
|
T110 |
1 |
higher_val |
zero_val |
auto[1] |
44888 |
1 |
|
|
T12 |
99 |
|
T44 |
111 |
|
T7 |
21 |
lower_val |
higher_val |
auto[0] |
40990 |
1 |
|
|
T1 |
104 |
|
T2 |
39 |
|
T5 |
3 |
lower_val |
higher_val |
auto[1] |
21733 |
1 |
|
|
T12 |
43 |
|
T44 |
33 |
|
T7 |
8 |
lower_val |
lower_val |
auto[0] |
41700 |
1 |
|
|
T1 |
92 |
|
T2 |
45 |
|
T5 |
3 |
lower_val |
lower_val |
auto[1] |
21955 |
1 |
|
|
T3 |
2 |
|
T12 |
39 |
|
T44 |
43 |
lower_val |
zero_val |
auto[0] |
81 |
1 |
|
|
T44 |
1 |
|
T148 |
1 |
|
T31 |
1 |
lower_val |
zero_val |
auto[1] |
43857 |
1 |
|
|
T3 |
3 |
|
T12 |
104 |
|
T44 |
99 |
zero_val |
higher_val |
auto[0] |
539 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
120 |
1 |
|
|
T12 |
1 |
|
T35 |
2 |
|
T47 |
1 |
zero_val |
lower_val |
auto[0] |
508 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T10 |
1 |
zero_val |
lower_val |
auto[1] |
118 |
1 |
|
|
T31 |
3 |
|
T32 |
3 |
|
T33 |
1 |
zero_val |
zero_val |
auto[0] |
267 |
1 |
|
|
T22 |
1 |
|
T44 |
1 |
|
T7 |
1 |
zero_val |
zero_val |
auto[1] |
185 |
1 |
|
|
T12 |
1 |
|
T47 |
1 |
|
T95 |
1 |