Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100169899	1			T1	225561		T2	1863		T3	254
all_pins[1]	100169899	1			T1	225561		T2	1863		T3	254
all_pins[2]	100169899	1			T1	225561		T2	1863		T3	254

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299679516	1			T1	676094		T2	5334		T3	750
values[0x1]	830181	1			T1	589		T2	255		T3	12
transitions[0x0=>0x1]	827953	1			T1	589		T2	255		T3	12
transitions[0x1=>0x0]	827979	1			T1	589		T2	255		T3	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99662721	1			T1	224972		T2	1608		T3	242
all_pins[0]	values[0x1]	507178	1			T1	589		T2	255		T3	12
all_pins[0]	transitions[0x0=>0x1]	507162	1			T1	589		T2	255		T3	12
all_pins[0]	transitions[0x1=>0x0]	5343	1			T5	2		T7	30		T8	31
all_pins[1]	values[0x0]	100164540	1			T1	225561		T2	1863		T3	254
all_pins[1]	values[0x1]	5359	1			T5	2		T7	30		T8	31
all_pins[1]	transitions[0x0=>0x1]	5038	1			T5	2		T7	30		T8	31
all_pins[1]	transitions[0x1=>0x0]	317323	1			T14	761		T31	7187		T32	7338
all_pins[2]	values[0x0]	99852255	1			T1	225561		T2	1863		T3	254
all_pins[2]	values[0x1]	317644	1			T14	761		T31	7187		T32	7346
all_pins[2]	transitions[0x0=>0x1]	315753	1			T14	761		T31	7135		T32	7295
all_pins[2]	transitions[0x1=>0x0]	505313	1			T1	589		T2	255		T3	12