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 LINE       67
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T59,T89
1	1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T128,T129,T130

 LINE       86
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T15,T16,T17
0	1	0	Covered	T128,T129,T130
1	0	0	Covered	T15,T16,T17

 LINE       136
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[1024:1535]}) ? 2'b0 : ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2))
             ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       136
 SUB-EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]}) ? 2'b1 : 2'd2)
                 ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T128,T129,T130
0	1	0	Covered	T32,T59,T89
1	0	0	Covered	T32,T59,T89

 LINE       667
 EXPRESSION (cfg_shadowed_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T1,T2,T3

 LINE       1291
 EXPRESSION (entropy_period_we & cfg_regwen_qs)
             --------1--------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       1378
 EXPRESSION (entropy_refresh_threshold_shadowed_we & cfg_regwen_qs)
             ------------------1------------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T1,T2,T3

 LINE       1443
 EXPRESSION (key_share0_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1467
 EXPRESSION (key_share0_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1491
 EXPRESSION (key_share0_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1515
 EXPRESSION (key_share0_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1539
 EXPRESSION (key_share0_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1563
 EXPRESSION (key_share0_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1587
 EXPRESSION (key_share0_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1611
 EXPRESSION (key_share0_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1635
 EXPRESSION (key_share0_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1659
 EXPRESSION (key_share0_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1683
 EXPRESSION (key_share0_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1707
 EXPRESSION (key_share0_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1731
 EXPRESSION (key_share0_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1755
 EXPRESSION (key_share0_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1779
 EXPRESSION (key_share0_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1803
 EXPRESSION (key_share0_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1827
 EXPRESSION (key_share1_0_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1851
 EXPRESSION (key_share1_1_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1875
 EXPRESSION (key_share1_2_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1899
 EXPRESSION (key_share1_3_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1923
 EXPRESSION (key_share1_4_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1947
 EXPRESSION (key_share1_5_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1971
 EXPRESSION (key_share1_6_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       1995
 EXPRESSION (key_share1_7_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2019
 EXPRESSION (key_share1_8_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2043
 EXPRESSION (key_share1_9_we & cfg_regwen_qs)
             -------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2067
 EXPRESSION (key_share1_10_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2091
 EXPRESSION (key_share1_11_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2115
 EXPRESSION (key_share1_12_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2139
 EXPRESSION (key_share1_13_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2163
 EXPRESSION (key_share1_14_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2187
 EXPRESSION (key_share1_15_we & cfg_regwen_qs)
             --------1-------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2207
 EXPRESSION (key_len_we & cfg_regwen_qs)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T1,T2,T3

 LINE       2239
 EXPRESSION (prefix_0_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2271
 EXPRESSION (prefix_1_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2303
 EXPRESSION (prefix_2_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2335
 EXPRESSION (prefix_3_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2367
 EXPRESSION (prefix_4_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2399
 EXPRESSION (prefix_5_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2431
 EXPRESSION (prefix_6_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2463
 EXPRESSION (prefix_7_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2495
 EXPRESSION (prefix_8_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2527
 EXPRESSION (prefix_9_we & cfg_regwen_qs)
             -----1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2559
 EXPRESSION (prefix_10_we & cfg_regwen_qs)
             ------1-----   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T28
1	1	Covered	T2,T3,T4

 LINE       2619
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2620
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2621
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

 LINE       2622
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

 LINE       2623
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_REGWEN_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2624
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CFG_SHADOWED_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2625
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_CMD_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2626
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2627
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_PERIOD_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2628
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_HASH_CNT_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T6

 LINE       2629
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_REFRESH_THRESHOLD_SHADOWED_OFFSET)
            -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2630
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ENTROPY_SEED_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2631
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2632
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2633
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2634
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2635
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2636
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2637
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2638
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2639
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2640
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2641
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2642
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2643
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2644
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2645
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2646
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE0_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2647
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_0_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2648
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_1_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2649
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_2_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2650
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_3_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2651
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_4_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2652
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_5_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2653
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_6_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2654
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_7_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2655
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_8_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2656
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_9_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2657
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_10_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2658
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_11_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2659
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_12_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2660
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_13_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2661
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_14_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2662
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_SHARE1_15_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2663
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_KEY_LEN_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2664
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_0_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2665
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_1_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2666
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_2_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2667
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_3_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2668
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_4_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2669
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_5_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2670
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_6_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2671
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_7_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2672
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_8_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2673
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_9_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2674
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_PREFIX_10_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       2675
 EXPRESSION (reg_addr == kmac_reg_pkg::KMAC_ERR_CODE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T6,T12

 LINE       2678
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       2678
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       2682
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T32,T59,T89

 LINE       2682
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0011 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b0011 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1111 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1111 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1111 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1111 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1111 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1111 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1111 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1111 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1111 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1111 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1111 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1111 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b1111 & (~reg_be))))) | 
     44  (addr_hit[43] & ((|(4'b1111 & (~reg_be))))) | 
     45  (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | 
     46  (addr_hit[45] & ((|(4'b1111 & (~reg_be))))) | 
     47  (addr_hit[46] & ((|(4'b1111 & (~reg_be))))) | 
     48  (addr_hit[47] & ((|(4'b1111 & (~reg_be))))) | 
     49  (addr_hit[48] & ((|(4'b1111 & (~reg_be))))) | 
     50  (addr_hit[49] & ((|(4'b1111 & (~reg_be))))) | 
     51  (addr_hit[50] & ((|(4'b1111 & (~reg_be))))) | 
     52  (addr_hit[51] & ((|(4'b1111 & (~reg_be))))) | 
     53  (addr_hit[52] & ((|(4'b1111 & (~reg_be))))) | 
     54  (addr_hit[53] & ((|(4'b1111 & (~reg_be))))) | 
     55  (addr_hit[54] & ((|(4'b1111 & (~reg_be))))) | 
     56  (addr_hit[55] & ((|(4'b1111 & (~reg_be))))) | 
     57  (addr_hit[56] & ((|(4'b1111 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T2,T3
57 (addr_hit[56] & ((\|(4'...	Covered	T9,T6,T12
56 (addr_hit[55] & ((\|(4'...	Covered	T3,T6,T12
55 (addr_hit[54] & ((\|(4'...	Covered	T12,T43,T23
54 (addr_hit[53] & ((\|(4'...	Covered	T6,T12,T43
53 (addr_hit[52] & ((\|(4'...	Covered	T3,T6,T12
52 (addr_hit[51] & ((\|(4'...	Covered	T3,T6,T12
51 (addr_hit[50] & ((\|(4'...	Covered	T3,T6,T12
50 (addr_hit[49] & ((\|(4'...	Covered	T3,T6,T12
49 (addr_hit[48] & ((\|(4'...	Covered	T3,T6,T12
48 (addr_hit[47] & ((\|(4'...	Covered	T3,T6,T12
47 (addr_hit[46] & ((\|(4'...	Covered	T3,T6,T12
46 (addr_hit[45] & ((\|(4'...	Covered	T3,T6,T12
45 (addr_hit[44] & ((\|(4'...	Covered	T3,T12,T43
44 (addr_hit[43] & ((\|(4'...	Covered	T6,T12,T43
43 (addr_hit[42] & ((\|(4'...	Covered	T3,T6,T12
42 (addr_hit[41] & ((\|(4'...	Covered	T3,T6,T12
41 (addr_hit[40] & ((\|(4'...	Covered	T3,T6,T12
40 (addr_hit[39] & ((\|(4'...	Covered	T3,T6,T12
39 (addr_hit[38] & ((\|(4'...	Covered	T3,T6,T12
38 (addr_hit[37] & ((\|(4'...	Covered	T3,T6,T12
37 (addr_hit[36] & ((\|(4'...	Covered	T12,T43,T23
36 (addr_hit[35] & ((\|(4'...	Covered	T3,T6,T12
35 (addr_hit[34] & ((\|(4'...	Covered	T3,T6,T12
34 (addr_hit[33] & ((\|(4'...	Covered	T3,T6,T12
33 (addr_hit[32] & ((\|(4'...	Covered	T3,T6,T12
32 (addr_hit[31] & ((\|(4'...	Covered	T3,T6,T12
31 (addr_hit[30] & ((\|(4'...	Covered	T12,T43,T23
30 (addr_hit[29] & ((\|(4'...	Covered	T3,T6,T12
29 (addr_hit[28] & ((\|(4'...	Covered	T6,T12,T43
28 (addr_hit[27] & ((\|(4'...	Covered	T3,T6,T12
27 (addr_hit[26] & ((\|(4'...	Covered	T3,T6,T12
26 (addr_hit[25] & ((\|(4'...	Covered	T3,T6,T12
25 (addr_hit[24] & ((\|(4'...	Covered	T3,T6,T12
24 (addr_hit[23] & ((\|(4'...	Covered	T3,T6,T12
23 (addr_hit[22] & ((\|(4'...	Covered	T3,T6,T12
22 (addr_hit[21] & ((\|(4'...	Covered	T3,T6,T12
21 (addr_hit[20] & ((\|(4'...	Covered	T6,T12,T43
20 (addr_hit[19] & ((\|(4'...	Covered	T6,T12,T43
19 (addr_hit[18] & ((\|(4'...	Covered	T3,T6,T12
18 (addr_hit[17] & ((\|(4'...	Covered	T6,T12,T43
17 (addr_hit[16] & ((\|(4'...	Covered	T6,T12,T43
16 (addr_hit[15] & ((\|(4'...	Covered	T3,T6,T12
15 (addr_hit[14] & ((\|(4'...	Covered	T3,T6,T12
14 (addr_hit[13] & ((\|(4'...	Covered	T6,T12,T43
13 (addr_hit[12] & ((\|(4'...	Covered	T3,T6,T12
12 (addr_hit[11] & ((\|(4'...	Covered	T3,T6,T12
11 (addr_hit[10] & ((\|(4'...	Covered	T6,T12,T43
10 (addr_hit[9] & ((\|(4'b...	Covered	T2,T4,T6
9 (addr_hit[8] & ((\|(4'b...	Covered	T6,T12,T43
8 (addr_hit[7] & ((\|(4'b...	Covered	T1,T2,T3
7 (addr_hit[6] & ((\|(4'b...	Covered	T6,T12,T43
6 (addr_hit[5] & ((\|(4'b...	Covered	T3,T6,T12
5 (addr_hit[4] & ((\|(4'b...	Covered	T2,T4,T6
4 (addr_hit[3] & ((\|(4'b...	Covered	T3,T6,T12
3 (addr_hit[2] & ((\|(4'b...	Covered	T12,T43,T23
2 (addr_hit[1] & ((\|(4'b...	Covered	T3,T12,T43
1 (addr_hit[0] & ((\|(4'b...	Covered	T1,T2,T3

 LINE       2682
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2682
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T12
1	1	Covered	T12,T43,T23

 LINE       2682
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T12
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T6

 LINE       2682
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       2682
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T2,T4,T6

 LINE       2682
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T6,T12,T43

 LINE       2682
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12

 LINE       2682
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T6,T12