Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98173783	1			T1	563564		T2	287		T3	216059
all_values[1]	98173783	1			T1	563564		T2	287		T3	216059
all_values[2]	98173783	1			T1	563564		T2	287		T3	216059

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

538604

1

T1

10

T3

3

T12

3

auto[1]

293982745

1

T1

169068

T2

861

T3

648174

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293008644

1

T1

168024

T2

822

T3

646545

auto[1]

1512705

1

T1

10449

T2

39

T3

1632

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	217292	1			T4	373		T5	1		T13	6
all_values[0]	auto[0]	auto[1]	2222	1			T4	4		T5	2		T13	6
all_values[0]	auto[1]	auto[0]	97452256	1			T1	560081		T2	274		T3	215515
all_values[0]	auto[1]	auto[1]	502013	1			T1	3483		T2	13		T3	544
all_values[1]	auto[0]	auto[0]	142731	1			T1	4		T3	2		T5	4
all_values[1]	auto[0]	auto[1]	1537	1			T1	3		T3	1		T5	3
all_values[1]	auto[1]	auto[0]	97526817	1			T1	560077		T2	274		T3	215513
all_values[1]	auto[1]	auto[1]	502698	1			T1	3480		T2	13		T3	543
all_values[2]	auto[0]	auto[0]	173247	1			T1	2		T12	2		T4	567
all_values[2]	auto[0]	auto[1]	1575	1			T1	1		T12	1		T4	5
all_values[2]	auto[1]	auto[0]	97496301	1			T1	560079		T2	274		T3	215515
all_values[2]	auto[1]	auto[1]	502660	1			T1	3482		T2	13		T3	544