Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
370016 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
2 |
auto[1] |
315532 |
1 |
|
|
T1 |
4672 |
|
T3 |
746 |
|
T5 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171264 |
1 |
|
|
T1 |
1189 |
|
T3 |
176 |
|
T12 |
142 |
lower_val |
170711 |
1 |
|
|
T1 |
1200 |
|
T2 |
4 |
|
T3 |
172 |
zero_val |
1870 |
1 |
|
|
T1 |
9 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263896 |
1 |
|
|
T1 |
1170 |
|
T2 |
4 |
|
T3 |
174 |
lower_val |
263136 |
1 |
|
|
T1 |
1176 |
|
T2 |
14 |
|
T3 |
166 |
zero_val |
158516 |
1 |
|
|
T1 |
2328 |
|
T3 |
408 |
|
T5 |
376 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45975 |
1 |
|
|
T12 |
73 |
|
T4 |
38 |
|
T7 |
37 |
higher_val |
higher_val |
auto[1] |
19893 |
1 |
|
|
T1 |
316 |
|
T3 |
50 |
|
T5 |
53 |
higher_val |
lower_val |
auto[0] |
46034 |
1 |
|
|
T1 |
1 |
|
T12 |
69 |
|
T4 |
38 |
higher_val |
lower_val |
auto[1] |
19658 |
1 |
|
|
T1 |
295 |
|
T3 |
33 |
|
T5 |
48 |
higher_val |
zero_val |
auto[0] |
84 |
1 |
|
|
T5 |
1 |
|
T9 |
1 |
|
T182 |
1 |
higher_val |
zero_val |
auto[1] |
39620 |
1 |
|
|
T1 |
577 |
|
T3 |
93 |
|
T5 |
86 |
lower_val |
higher_val |
auto[0] |
46247 |
1 |
|
|
T2 |
2 |
|
T12 |
110 |
|
T4 |
49 |
lower_val |
higher_val |
auto[1] |
19764 |
1 |
|
|
T1 |
290 |
|
T3 |
26 |
|
T5 |
47 |
lower_val |
lower_val |
auto[0] |
45833 |
1 |
|
|
T2 |
2 |
|
T12 |
111 |
|
T4 |
39 |
lower_val |
lower_val |
auto[1] |
19552 |
1 |
|
|
T1 |
282 |
|
T3 |
41 |
|
T5 |
42 |
lower_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T39 |
1 |
|
T72 |
1 |
|
T73 |
1 |
lower_val |
zero_val |
auto[1] |
39227 |
1 |
|
|
T1 |
628 |
|
T3 |
105 |
|
T5 |
97 |
zero_val |
higher_val |
auto[0] |
572 |
1 |
|
|
T4 |
1 |
|
T7 |
1 |
|
T36 |
6 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T1 |
4 |
|
T39 |
2 |
|
T183 |
4 |
zero_val |
lower_val |
auto[0] |
560 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
159 |
1 |
|
|
T1 |
1 |
|
T49 |
1 |
|
T183 |
4 |
zero_val |
zero_val |
auto[0] |
243 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T39 |
1 |
zero_val |
zero_val |
auto[1] |
198 |
1 |
|
|
T1 |
3 |
|
T49 |
1 |
|
T39 |
1 |