Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98173783	1			T1	563564		T2	287		T3	216059
all_pins[1]	98173783	1			T1	563564		T2	287		T3	216059
all_pins[2]	98173783	1			T1	563564		T2	287		T3	216059

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	293709539	1			T1	168720		T2	848		T3	647633
values[0x1]	811810	1			T1	3483		T2	13		T3	544
transitions[0x0=>0x1]	809587	1			T1	3483		T2	13		T3	544
transitions[0x1=>0x0]	809606	1			T1	3483		T2	13		T3	544

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97671770	1			T1	560081		T2	274		T3	215515
all_pins[0]	values[0x1]	502013	1			T1	3483		T2	13		T3	544
all_pins[0]	transitions[0x0=>0x1]	502004	1			T1	3483		T2	13		T3	544
all_pins[0]	transitions[0x1=>0x0]	5082	1			T7	28		T10	35		T48	32
all_pins[1]	values[0x0]	98168692	1			T1	563564		T2	287		T3	216059
all_pins[1]	values[0x1]	5091	1			T7	28		T10	35		T48	32
all_pins[1]	transitions[0x0=>0x1]	4743	1			T7	28		T48	32		T50	18
all_pins[1]	transitions[0x1=>0x0]	304358	1			T10	17083		T15	826		T62	415
all_pins[2]	values[0x0]	97869077	1			T1	563564		T2	287		T3	216059
all_pins[2]	values[0x1]	304706	1			T10	17118		T15	826		T62	415
all_pins[2]	transitions[0x0=>0x1]	302840	1			T10	17013		T15	826		T62	415
all_pins[2]	transitions[0x1=>0x0]	500166	1			T1	3483		T2	13		T3	544