Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10619421 |
1 |
|
|
T1 |
27235 |
|
T2 |
96 |
|
T3 |
2992 |
auto[1] |
10619366 |
1 |
|
|
T1 |
27235 |
|
T2 |
96 |
|
T3 |
2992 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21003477 |
1 |
|
|
T1 |
52796 |
|
T2 |
192 |
|
T3 |
5984 |
triple_byte_access |
78062 |
1 |
|
|
T1 |
558 |
|
T4 |
60 |
|
T7 |
46 |
halfword_access |
78788 |
1 |
|
|
T1 |
558 |
|
T4 |
54 |
|
T7 |
38 |
byte_access |
78460 |
1 |
|
|
T1 |
558 |
|
T4 |
54 |
|
T7 |
44 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10501766 |
1 |
|
|
T1 |
26398 |
|
T2 |
96 |
|
T3 |
2992 |
auto[0] |
triple_byte_access |
39031 |
1 |
|
|
T1 |
279 |
|
T4 |
30 |
|
T7 |
23 |
auto[0] |
halfword_access |
39394 |
1 |
|
|
T1 |
279 |
|
T4 |
27 |
|
T7 |
19 |
auto[0] |
byte_access |
39230 |
1 |
|
|
T1 |
279 |
|
T4 |
27 |
|
T7 |
22 |
auto[1] |
word_access |
10501711 |
1 |
|
|
T1 |
26398 |
|
T2 |
96 |
|
T3 |
2992 |
auto[1] |
triple_byte_access |
39031 |
1 |
|
|
T1 |
279 |
|
T4 |
30 |
|
T7 |
23 |
auto[1] |
halfword_access |
39394 |
1 |
|
|
T1 |
279 |
|
T4 |
27 |
|
T7 |
19 |
auto[1] |
byte_access |
39230 |
1 |
|
|
T1 |
279 |
|
T4 |
27 |
|
T7 |
22 |