Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.86 98.10 92.71 99.89 94.55 95.97 98.89 97.89


Total test records in report: 1241
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T1051 /workspace/coverage/default/26.kmac_stress_all.3676952417 Apr 25 04:05:13 PM PDT 24 Apr 25 04:13:07 PM PDT 24 5521945757 ps
T1052 /workspace/coverage/default/36.kmac_app.3751679648 Apr 25 04:08:19 PM PDT 24 Apr 25 04:15:01 PM PDT 24 73757162552 ps
T1053 /workspace/coverage/default/31.kmac_test_vectors_kmac.3614682175 Apr 25 04:06:38 PM PDT 24 Apr 25 04:06:44 PM PDT 24 421208216 ps
T1054 /workspace/coverage/default/37.kmac_sideload.747280912 Apr 25 04:08:39 PM PDT 24 Apr 25 04:10:50 PM PDT 24 1505569066 ps
T1055 /workspace/coverage/default/34.kmac_key_error.4271709970 Apr 25 04:07:35 PM PDT 24 Apr 25 04:07:39 PM PDT 24 1624410824 ps
T1056 /workspace/coverage/default/16.kmac_lc_escalation.2076331771 Apr 25 04:02:02 PM PDT 24 Apr 25 04:02:04 PM PDT 24 45893895 ps
T1057 /workspace/coverage/default/2.kmac_test_vectors_shake_128.4186163493 Apr 25 03:55:42 PM PDT 24 Apr 25 05:26:59 PM PDT 24 198503519870 ps
T1058 /workspace/coverage/default/43.kmac_smoke.1302289488 Apr 25 04:10:43 PM PDT 24 Apr 25 04:11:37 PM PDT 24 13017368268 ps
T1059 /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2737295189 Apr 25 04:12:05 PM PDT 24 Apr 25 04:50:14 PM PDT 24 129727890090 ps
T1060 /workspace/coverage/default/34.kmac_test_vectors_kmac.1974735232 Apr 25 04:07:34 PM PDT 24 Apr 25 04:07:41 PM PDT 24 275608071 ps
T1061 /workspace/coverage/default/34.kmac_long_msg_and_output.2204712230 Apr 25 04:07:24 PM PDT 24 Apr 25 04:50:42 PM PDT 24 297371287363 ps
T1062 /workspace/coverage/default/14.kmac_alert_test.3529596522 Apr 25 04:01:19 PM PDT 24 Apr 25 04:01:21 PM PDT 24 24109641 ps
T1063 /workspace/coverage/default/37.kmac_lc_escalation.402656625 Apr 25 04:08:53 PM PDT 24 Apr 25 04:08:55 PM PDT 24 81978586 ps
T1064 /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1425237454 Apr 25 04:08:20 PM PDT 24 Apr 25 04:41:11 PM PDT 24 39600218130 ps
T1065 /workspace/coverage/default/11.kmac_sideload.2147765545 Apr 25 04:00:00 PM PDT 24 Apr 25 04:05:09 PM PDT 24 13329220992 ps
T1066 /workspace/coverage/default/45.kmac_error.3739757325 Apr 25 04:11:37 PM PDT 24 Apr 25 04:12:17 PM PDT 24 2634741009 ps
T1067 /workspace/coverage/default/29.kmac_burst_write.3840823614 Apr 25 04:05:56 PM PDT 24 Apr 25 04:27:09 PM PDT 24 118978450746 ps
T1068 /workspace/coverage/default/28.kmac_smoke.1192635278 Apr 25 04:05:32 PM PDT 24 Apr 25 04:05:38 PM PDT 24 824670839 ps
T1069 /workspace/coverage/default/25.kmac_alert_test.1022299759 Apr 25 04:04:58 PM PDT 24 Apr 25 04:04:59 PM PDT 24 39405473 ps
T1070 /workspace/coverage/default/15.kmac_entropy_refresh.3957796767 Apr 25 04:01:41 PM PDT 24 Apr 25 04:03:21 PM PDT 24 4128294499 ps
T1071 /workspace/coverage/default/4.kmac_test_vectors_shake_256.1143814352 Apr 25 03:56:47 PM PDT 24 Apr 25 05:15:47 PM PDT 24 372956697908 ps
T1072 /workspace/coverage/default/10.kmac_alert_test.3142899006 Apr 25 03:59:51 PM PDT 24 Apr 25 03:59:52 PM PDT 24 25288636 ps
T1073 /workspace/coverage/default/18.kmac_burst_write.1469937369 Apr 25 04:02:34 PM PDT 24 Apr 25 04:09:56 PM PDT 24 52951718247 ps
T1074 /workspace/coverage/default/43.kmac_entropy_refresh.1715114684 Apr 25 04:10:56 PM PDT 24 Apr 25 04:15:17 PM PDT 24 14152850956 ps
T1075 /workspace/coverage/default/17.kmac_burst_write.2176311869 Apr 25 04:02:14 PM PDT 24 Apr 25 04:11:47 PM PDT 24 44025985418 ps
T1076 /workspace/coverage/default/29.kmac_test_vectors_shake_256.2969351045 Apr 25 04:06:09 PM PDT 24 Apr 25 05:25:58 PM PDT 24 218420918388 ps
T1077 /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.681032078 Apr 25 04:10:00 PM PDT 24 Apr 25 04:10:07 PM PDT 24 175275900 ps
T124 /workspace/coverage/cover_reg_top/7.kmac_intr_test.1973625627 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:23 PM PDT 24 25791906 ps
T151 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2845960474 Apr 25 12:52:07 PM PDT 24 Apr 25 12:52:13 PM PDT 24 123881488 ps
T125 /workspace/coverage/cover_reg_top/27.kmac_intr_test.941823204 Apr 25 12:52:38 PM PDT 24 Apr 25 12:52:41 PM PDT 24 129282889 ps
T180 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.157341913 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:44 PM PDT 24 23383569 ps
T88 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1873376750 Apr 25 12:52:44 PM PDT 24 Apr 25 12:52:48 PM PDT 24 142854681 ps
T181 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3457598873 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:20 PM PDT 24 32361514 ps
T126 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1605949950 Apr 25 12:52:30 PM PDT 24 Apr 25 12:52:33 PM PDT 24 31517623 ps
T121 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2891746823 Apr 25 12:52:30 PM PDT 24 Apr 25 12:52:34 PM PDT 24 114521539 ps
T152 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.896113342 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:16 PM PDT 24 22707680 ps
T1078 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3040954393 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:19 PM PDT 24 189814790 ps
T122 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3878529842 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:35 PM PDT 24 497041860 ps
T162 /workspace/coverage/cover_reg_top/21.kmac_intr_test.507047983 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:42 PM PDT 24 14841179 ps
T157 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3184466791 Apr 25 12:52:46 PM PDT 24 Apr 25 12:52:48 PM PDT 24 15298036 ps
T158 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2126765846 Apr 25 12:52:44 PM PDT 24 Apr 25 12:52:47 PM PDT 24 24765285 ps
T1079 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3520007638 Apr 25 12:52:36 PM PDT 24 Apr 25 12:52:39 PM PDT 24 82365245 ps
T153 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.649447327 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:26 PM PDT 24 99830409 ps
T166 /workspace/coverage/cover_reg_top/18.kmac_intr_test.865745952 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:39 PM PDT 24 19516463 ps
T89 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1444470672 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:19 PM PDT 24 64816413 ps
T90 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3705776509 Apr 25 12:52:20 PM PDT 24 Apr 25 12:52:24 PM PDT 24 185075238 ps
T1080 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1191953750 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:32 PM PDT 24 171452465 ps
T1081 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.177311841 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:22 PM PDT 24 77832163 ps
T1082 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3107986580 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:24 PM PDT 24 46013769 ps
T1083 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2350039239 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:29 PM PDT 24 47513535 ps
T144 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3572194180 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:16 PM PDT 24 50422927 ps
T91 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3565962318 Apr 25 12:52:10 PM PDT 24 Apr 25 12:52:14 PM PDT 24 76631515 ps
T1084 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2009052018 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:20 PM PDT 24 41935871 ps
T154 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.775791474 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:17 PM PDT 24 35406102 ps
T1085 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3644531712 Apr 25 12:52:31 PM PDT 24 Apr 25 12:52:34 PM PDT 24 77146773 ps
T1086 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1350055865 Apr 25 12:52:18 PM PDT 24 Apr 25 12:52:21 PM PDT 24 76315129 ps
T165 /workspace/coverage/cover_reg_top/25.kmac_intr_test.3962774930 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:42 PM PDT 24 34204036 ps
T1087 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3701838230 Apr 25 12:52:17 PM PDT 24 Apr 25 12:52:20 PM PDT 24 17865082 ps
T163 /workspace/coverage/cover_reg_top/17.kmac_intr_test.1837760725 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:37 PM PDT 24 18259399 ps
T1088 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4095383944 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:30 PM PDT 24 50465969 ps
T1089 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3038585446 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 46190933 ps
T1090 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2885030825 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:44 PM PDT 24 20290247 ps
T164 /workspace/coverage/cover_reg_top/3.kmac_intr_test.1694566582 Apr 25 12:52:11 PM PDT 24 Apr 25 12:52:15 PM PDT 24 45802090 ps
T1091 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3039452967 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:45 PM PDT 24 94388342 ps
T94 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3360162395 Apr 25 12:52:38 PM PDT 24 Apr 25 12:52:43 PM PDT 24 157018519 ps
T92 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1457497533 Apr 25 12:52:45 PM PDT 24 Apr 25 12:52:48 PM PDT 24 438285276 ps
T1092 /workspace/coverage/cover_reg_top/4.kmac_intr_test.1508373878 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:30 PM PDT 24 38621966 ps
T1093 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1604076088 Apr 25 12:52:17 PM PDT 24 Apr 25 12:52:21 PM PDT 24 45032840 ps
T93 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1618394311 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 63089633 ps
T1094 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.657552911 Apr 25 12:52:11 PM PDT 24 Apr 25 12:52:22 PM PDT 24 576992790 ps
T1095 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2512768417 Apr 25 12:52:51 PM PDT 24 Apr 25 12:52:55 PM PDT 24 129319030 ps
T1096 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.476684883 Apr 25 12:52:11 PM PDT 24 Apr 25 12:52:22 PM PDT 24 138730815 ps
T1097 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3940234464 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:24 PM PDT 24 88257418 ps
T145 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.725871905 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:25 PM PDT 24 31205276 ps
T1098 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1893943783 Apr 25 12:52:18 PM PDT 24 Apr 25 12:52:23 PM PDT 24 46739366 ps
T1099 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2315740674 Apr 25 12:52:08 PM PDT 24 Apr 25 12:52:16 PM PDT 24 367876986 ps
T99 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3923661798 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:23 PM PDT 24 51435422 ps
T1100 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.716647571 Apr 25 12:52:05 PM PDT 24 Apr 25 12:52:09 PM PDT 24 223086356 ps
T1101 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1941528616 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:29 PM PDT 24 180428752 ps
T146 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1878969136 Apr 25 12:52:14 PM PDT 24 Apr 25 12:52:18 PM PDT 24 139735072 ps
T1102 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.262380098 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:33 PM PDT 24 214776901 ps
T97 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1928536241 Apr 25 12:52:55 PM PDT 24 Apr 25 12:52:58 PM PDT 24 96803535 ps
T1103 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.933903390 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:35 PM PDT 24 67760029 ps
T155 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.434267424 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:31 PM PDT 24 57798262 ps
T1104 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.906407974 Apr 25 12:52:33 PM PDT 24 Apr 25 12:52:38 PM PDT 24 499226929 ps
T1105 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3489940748 Apr 25 12:52:24 PM PDT 24 Apr 25 12:52:26 PM PDT 24 37695077 ps
T1106 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3750463740 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:20 PM PDT 24 51467055 ps
T1107 /workspace/coverage/cover_reg_top/6.kmac_intr_test.3215582991 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:31 PM PDT 24 15272256 ps
T1108 /workspace/coverage/cover_reg_top/10.kmac_intr_test.4137848214 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:42 PM PDT 24 13058017 ps
T1109 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2598336250 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:29 PM PDT 24 96440396 ps
T1110 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2293335674 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:27 PM PDT 24 17745685 ps
T1111 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.826152056 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:23 PM PDT 24 231491338 ps
T1112 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3303727086 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:38 PM PDT 24 26348053 ps
T1113 /workspace/coverage/cover_reg_top/37.kmac_intr_test.744194475 Apr 25 12:52:45 PM PDT 24 Apr 25 12:52:48 PM PDT 24 31354144 ps
T1114 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2254381382 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:31 PM PDT 24 263364629 ps
T1115 /workspace/coverage/cover_reg_top/48.kmac_intr_test.153000775 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:43 PM PDT 24 90028658 ps
T159 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1014975312 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:32 PM PDT 24 380932117 ps
T1116 /workspace/coverage/cover_reg_top/36.kmac_intr_test.857885504 Apr 25 12:52:42 PM PDT 24 Apr 25 12:52:45 PM PDT 24 42752316 ps
T1117 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.790322497 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:21 PM PDT 24 31296844 ps
T156 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3389488502 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:21 PM PDT 24 284733967 ps
T160 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3449003689 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:20 PM PDT 24 200866707 ps
T1118 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1800182457 Apr 25 12:52:46 PM PDT 24 Apr 25 12:52:50 PM PDT 24 286536582 ps
T1119 /workspace/coverage/cover_reg_top/16.kmac_intr_test.290003338 Apr 25 12:52:41 PM PDT 24 Apr 25 12:52:44 PM PDT 24 62004908 ps
T1120 /workspace/coverage/cover_reg_top/42.kmac_intr_test.753302661 Apr 25 12:52:43 PM PDT 24 Apr 25 12:52:45 PM PDT 24 50372999 ps
T1121 /workspace/coverage/cover_reg_top/15.kmac_intr_test.3410846879 Apr 25 12:52:32 PM PDT 24 Apr 25 12:52:35 PM PDT 24 21609189 ps
T1122 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2142720234 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:29 PM PDT 24 14898266 ps
T1123 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1176116266 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:44 PM PDT 24 451060330 ps
T1124 /workspace/coverage/cover_reg_top/11.kmac_intr_test.2960600176 Apr 25 12:52:30 PM PDT 24 Apr 25 12:52:33 PM PDT 24 16542592 ps
T1125 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2223710499 Apr 25 12:52:10 PM PDT 24 Apr 25 12:52:13 PM PDT 24 43518576 ps
T95 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1466428897 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:35 PM PDT 24 133285280 ps
T1126 /workspace/coverage/cover_reg_top/9.kmac_intr_test.3944930101 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:25 PM PDT 24 105137830 ps
T1127 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.45115328 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:19 PM PDT 24 629460720 ps
T123 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.811085107 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:19 PM PDT 24 263542760 ps
T96 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1762150059 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:32 PM PDT 24 56646356 ps
T1128 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3713600912 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:33 PM PDT 24 120867946 ps
T1129 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1605316943 Apr 25 12:52:36 PM PDT 24 Apr 25 12:52:38 PM PDT 24 44461119 ps
T1130 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.169698211 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:20 PM PDT 24 28046319 ps
T1131 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.830063191 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:17 PM PDT 24 33141212 ps
T1132 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2958477584 Apr 25 12:52:31 PM PDT 24 Apr 25 12:52:36 PM PDT 24 757668646 ps
T1133 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2055067931 Apr 25 12:52:09 PM PDT 24 Apr 25 12:52:12 PM PDT 24 51972047 ps
T1134 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2010049905 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 278958644 ps
T1135 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1598420666 Apr 25 12:52:11 PM PDT 24 Apr 25 12:52:15 PM PDT 24 23051594 ps
T98 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1428736172 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:34 PM PDT 24 125493825 ps
T1136 /workspace/coverage/cover_reg_top/28.kmac_intr_test.1421898994 Apr 25 12:52:42 PM PDT 24 Apr 25 12:52:45 PM PDT 24 56422603 ps
T100 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3641209893 Apr 25 12:52:11 PM PDT 24 Apr 25 12:52:16 PM PDT 24 34565275 ps
T1137 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2711686950 Apr 25 12:52:18 PM PDT 24 Apr 25 12:52:23 PM PDT 24 126678417 ps
T172 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3198789470 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:32 PM PDT 24 233981453 ps
T1138 /workspace/coverage/cover_reg_top/5.kmac_intr_test.2333691182 Apr 25 12:52:30 PM PDT 24 Apr 25 12:52:33 PM PDT 24 54934019 ps
T1139 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4272080333 Apr 25 12:52:34 PM PDT 24 Apr 25 12:52:37 PM PDT 24 49869990 ps
T1140 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1072575530 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:32 PM PDT 24 93324894 ps
T175 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.522573953 Apr 25 12:52:33 PM PDT 24 Apr 25 12:52:39 PM PDT 24 101952834 ps
T1141 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1515998189 Apr 25 12:52:34 PM PDT 24 Apr 25 12:52:36 PM PDT 24 78820773 ps
T1142 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2804161576 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:26 PM PDT 24 379468560 ps
T1143 /workspace/coverage/cover_reg_top/32.kmac_intr_test.788998442 Apr 25 12:52:48 PM PDT 24 Apr 25 12:52:51 PM PDT 24 13999608 ps
T1144 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4091853483 Apr 25 12:52:24 PM PDT 24 Apr 25 12:52:27 PM PDT 24 86633825 ps
T1145 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3028076824 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:22 PM PDT 24 57699305 ps
T1146 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2985753226 Apr 25 12:52:36 PM PDT 24 Apr 25 12:52:39 PM PDT 24 15743842 ps
T1147 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1371321484 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:43 PM PDT 24 47220392 ps
T1148 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1920701565 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:20 PM PDT 24 115809109 ps
T1149 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2163033422 Apr 25 12:52:56 PM PDT 24 Apr 25 12:52:58 PM PDT 24 114109804 ps
T1150 /workspace/coverage/cover_reg_top/38.kmac_intr_test.3408661239 Apr 25 12:52:42 PM PDT 24 Apr 25 12:52:45 PM PDT 24 14814574 ps
T1151 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4080663778 Apr 25 12:52:46 PM PDT 24 Apr 25 12:52:49 PM PDT 24 41489574 ps
T176 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2331495899 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:23 PM PDT 24 740673347 ps
T1152 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1524953300 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:33 PM PDT 24 75527243 ps
T1153 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.295210324 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:44 PM PDT 24 58378042 ps
T1154 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1167558630 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:24 PM PDT 24 1162553918 ps
T1155 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1083361359 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:31 PM PDT 24 111184541 ps
T1156 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3960313319 Apr 25 12:52:09 PM PDT 24 Apr 25 12:52:20 PM PDT 24 397808771 ps
T1157 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4042813707 Apr 25 12:52:24 PM PDT 24 Apr 25 12:52:29 PM PDT 24 268969853 ps
T1158 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1880375822 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:23 PM PDT 24 54352125 ps
T1159 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.323213505 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:34 PM PDT 24 362007478 ps
T173 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3710026378 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:42 PM PDT 24 378012625 ps
T1160 /workspace/coverage/cover_reg_top/0.kmac_intr_test.2945943535 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:17 PM PDT 24 15388615 ps
T1161 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1302574474 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:18 PM PDT 24 59886782 ps
T1162 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2459304227 Apr 25 12:52:45 PM PDT 24 Apr 25 12:52:49 PM PDT 24 68323468 ps
T1163 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.958317153 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:34 PM PDT 24 1177762566 ps
T127 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3025899325 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:33 PM PDT 24 197676478 ps
T1164 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2780174839 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:24 PM PDT 24 50442563 ps
T1165 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.847554896 Apr 25 12:52:14 PM PDT 24 Apr 25 12:52:18 PM PDT 24 28651238 ps
T1166 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.868975640 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:35 PM PDT 24 186188567 ps
T147 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.861153412 Apr 25 12:52:31 PM PDT 24 Apr 25 12:52:35 PM PDT 24 60681076 ps
T1167 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2377342098 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 70822028 ps
T1168 /workspace/coverage/cover_reg_top/49.kmac_intr_test.3873875267 Apr 25 12:52:44 PM PDT 24 Apr 25 12:52:47 PM PDT 24 43552371 ps
T1169 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2182982631 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:18 PM PDT 24 179180724 ps
T1170 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2039442559 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:28 PM PDT 24 43192231 ps
T1171 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3140103851 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:17 PM PDT 24 26070629 ps
T1172 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1487847688 Apr 25 12:52:36 PM PDT 24 Apr 25 12:52:41 PM PDT 24 374471827 ps
T1173 /workspace/coverage/cover_reg_top/8.kmac_intr_test.867534045 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:16 PM PDT 24 40705444 ps
T1174 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1041898942 Apr 25 12:52:10 PM PDT 24 Apr 25 12:52:13 PM PDT 24 35051503 ps
T1175 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1549299155 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:20 PM PDT 24 58640643 ps
T1176 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.75177872 Apr 25 12:52:15 PM PDT 24 Apr 25 12:52:19 PM PDT 24 101254913 ps
T1177 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.907903984 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:17 PM PDT 24 236687139 ps
T1178 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4080112568 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:43 PM PDT 24 161948821 ps
T1179 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.581882485 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:28 PM PDT 24 100420109 ps
T1180 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.488838757 Apr 25 12:52:40 PM PDT 24 Apr 25 12:53:03 PM PDT 24 1461387555 ps
T1181 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2935185037 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:30 PM PDT 24 211365930 ps
T1182 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.691358135 Apr 25 12:52:32 PM PDT 24 Apr 25 12:52:35 PM PDT 24 17967717 ps
T1183 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3813954332 Apr 25 12:52:14 PM PDT 24 Apr 25 12:52:19 PM PDT 24 83492989 ps
T174 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.607789226 Apr 25 12:52:18 PM PDT 24 Apr 25 12:52:26 PM PDT 24 884543088 ps
T1184 /workspace/coverage/cover_reg_top/31.kmac_intr_test.1960303718 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:39 PM PDT 24 52061945 ps
T1185 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.739982154 Apr 25 12:52:42 PM PDT 24 Apr 25 12:52:47 PM PDT 24 244645126 ps
T1186 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4172912671 Apr 25 12:52:14 PM PDT 24 Apr 25 12:52:18 PM PDT 24 62917811 ps
T1187 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1400842191 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:31 PM PDT 24 1941454098 ps
T177 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.258676020 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:46 PM PDT 24 162807389 ps
T1188 /workspace/coverage/cover_reg_top/39.kmac_intr_test.3120805018 Apr 25 12:52:45 PM PDT 24 Apr 25 12:52:48 PM PDT 24 38586015 ps
T148 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3284855323 Apr 25 12:52:07 PM PDT 24 Apr 25 12:52:12 PM PDT 24 41961703 ps
T1189 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1105276111 Apr 25 12:52:22 PM PDT 24 Apr 25 12:52:24 PM PDT 24 74514122 ps
T1190 /workspace/coverage/cover_reg_top/33.kmac_intr_test.3232176041 Apr 25 12:52:45 PM PDT 24 Apr 25 12:52:47 PM PDT 24 87165595 ps
T1191 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2644055928 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:17 PM PDT 24 72202438 ps
T1192 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1365778072 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:23 PM PDT 24 186076776 ps
T1193 /workspace/coverage/cover_reg_top/23.kmac_intr_test.3145826176 Apr 25 12:52:39 PM PDT 24 Apr 25 12:52:42 PM PDT 24 47209315 ps
T1194 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1628181411 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:27 PM PDT 24 154947795 ps
T1195 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2853856073 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:30 PM PDT 24 32113731 ps
T1196 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3318722053 Apr 25 12:52:41 PM PDT 24 Apr 25 12:52:46 PM PDT 24 213070589 ps
T1197 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.307739891 Apr 25 12:52:28 PM PDT 24 Apr 25 12:52:31 PM PDT 24 34669639 ps
T1198 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3247800107 Apr 25 12:52:34 PM PDT 24 Apr 25 12:52:39 PM PDT 24 108658659 ps
T1199 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2927745090 Apr 25 12:52:43 PM PDT 24 Apr 25 12:52:45 PM PDT 24 16615348 ps
T1200 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1202055499 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:41 PM PDT 24 400477306 ps
T1201 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1449765426 Apr 25 12:52:24 PM PDT 24 Apr 25 12:52:32 PM PDT 24 26270708 ps
T1202 /workspace/coverage/cover_reg_top/43.kmac_intr_test.550336395 Apr 25 12:52:47 PM PDT 24 Apr 25 12:52:50 PM PDT 24 20428432 ps
T1203 /workspace/coverage/cover_reg_top/26.kmac_intr_test.4039852077 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:43 PM PDT 24 37621597 ps
T1204 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3749661637 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:20 PM PDT 24 80799937 ps
T1205 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.198920022 Apr 25 12:52:32 PM PDT 24 Apr 25 12:52:34 PM PDT 24 41980953 ps
T1206 /workspace/coverage/cover_reg_top/1.kmac_intr_test.2841489497 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:32 PM PDT 24 89329967 ps
T1207 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.776882391 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:27 PM PDT 24 321027211 ps
T1208 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4212278773 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:18 PM PDT 24 140214226 ps
T1209 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1859099113 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:33 PM PDT 24 255796792 ps
T1210 /workspace/coverage/cover_reg_top/22.kmac_intr_test.1418033867 Apr 25 12:52:49 PM PDT 24 Apr 25 12:52:51 PM PDT 24 27003729 ps
T1211 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1668537715 Apr 25 12:52:21 PM PDT 24 Apr 25 12:52:25 PM PDT 24 194808780 ps
T1212 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2827355913 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:27 PM PDT 24 20553990 ps
T1213 /workspace/coverage/cover_reg_top/13.kmac_intr_test.4015969591 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:28 PM PDT 24 14297701 ps
T179 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.199852362 Apr 25 12:52:26 PM PDT 24 Apr 25 12:52:30 PM PDT 24 139059389 ps
T1214 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2706624031 Apr 25 12:52:13 PM PDT 24 Apr 25 12:52:21 PM PDT 24 495871372 ps
T1215 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1280245184 Apr 25 12:52:33 PM PDT 24 Apr 25 12:52:35 PM PDT 24 17003894 ps
T1216 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1649270015 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:17 PM PDT 24 104540250 ps
T1217 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3107047640 Apr 25 12:52:16 PM PDT 24 Apr 25 12:52:21 PM PDT 24 180562208 ps
T1218 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1699175397 Apr 25 12:52:27 PM PDT 24 Apr 25 12:52:32 PM PDT 24 244788759 ps
T178 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3423205420 Apr 25 12:52:08 PM PDT 24 Apr 25 12:52:13 PM PDT 24 105507541 ps
T1219 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.580359516 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:28 PM PDT 24 109569918 ps
T1220 /workspace/coverage/cover_reg_top/40.kmac_intr_test.2220062288 Apr 25 12:52:46 PM PDT 24 Apr 25 12:52:49 PM PDT 24 42581387 ps
T1221 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3762582804 Apr 25 12:52:17 PM PDT 24 Apr 25 12:52:25 PM PDT 24 1258790060 ps
T1222 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2913755700 Apr 25 12:52:36 PM PDT 24 Apr 25 12:52:39 PM PDT 24 134802037 ps
T1223 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.96581202 Apr 25 12:52:24 PM PDT 24 Apr 25 12:52:27 PM PDT 24 269206836 ps
T1224 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3698976046 Apr 25 12:52:07 PM PDT 24 Apr 25 12:52:13 PM PDT 24 106923112 ps
T1225 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.592852073 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:43 PM PDT 24 52648384 ps
T1226 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4191802757 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:45 PM PDT 24 88019340 ps
T1227 /workspace/coverage/cover_reg_top/14.kmac_intr_test.262935507 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:39 PM PDT 24 35748306 ps
T1228 /workspace/coverage/cover_reg_top/35.kmac_intr_test.3673998163 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:37 PM PDT 24 18851406 ps
T1229 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2328233839 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:29 PM PDT 24 323028421 ps
T1230 /workspace/coverage/cover_reg_top/20.kmac_intr_test.3083773692 Apr 25 12:52:44 PM PDT 24 Apr 25 12:52:47 PM PDT 24 13712059 ps
T1231 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3426426438 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:38 PM PDT 24 162832334 ps
T1232 /workspace/coverage/cover_reg_top/29.kmac_intr_test.2386913392 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 18338414 ps
T1233 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2420821220 Apr 25 12:52:35 PM PDT 24 Apr 25 12:52:37 PM PDT 24 52276570 ps
T1234 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.213204791 Apr 25 12:52:23 PM PDT 24 Apr 25 12:52:28 PM PDT 24 118752036 ps
T1235 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2891128794 Apr 25 12:52:06 PM PDT 24 Apr 25 12:52:11 PM PDT 24 57035118 ps
T1236 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1139291306 Apr 25 12:52:19 PM PDT 24 Apr 25 12:52:40 PM PDT 24 3836065576 ps
T1237 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3145884852 Apr 25 12:52:25 PM PDT 24 Apr 25 12:52:29 PM PDT 24 35157631 ps
T1238 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.64290966 Apr 25 12:52:12 PM PDT 24 Apr 25 12:52:17 PM PDT 24 63057083 ps
T1239 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1917105963 Apr 25 12:52:29 PM PDT 24 Apr 25 12:52:33 PM PDT 24 71848124 ps
T1240 /workspace/coverage/cover_reg_top/46.kmac_intr_test.2779857425 Apr 25 12:52:40 PM PDT 24 Apr 25 12:52:43 PM PDT 24 43024826 ps
T1241 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2575404891 Apr 25 12:52:37 PM PDT 24 Apr 25 12:52:40 PM PDT 24 98896141 ps

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.804436430
Short name T7
Test name
Test status
Simulation time 5138035943 ps
CPU time 264.2 seconds
Started Apr 25 03:59:17 PM PDT 24
Finished Apr 25 04:03:42 PM PDT 24
Peak memory 245056 kb
Host smart-56dbd771-e208-415e-b281-83a2df266723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804436430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.804436430 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.3878529842
Short name T122
Test name
Test status
Simulation time 497041860 ps
CPU time 5.03 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 215968 kb
Host smart-04fe3294-dcb1-4716-8de9-81e5ce5657ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878529842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.3878
529842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.3629276043
Short name T18
Test name
Test status
Simulation time 63094198028 ps
CPU time 131.11 seconds
Started Apr 25 03:56:00 PM PDT 24
Finished Apr 25 03:58:12 PM PDT 24
Peak memory 294036 kb
Host smart-572e89fd-aa3e-4f6c-8b8f-83b5b2811f87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629276043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.3629276043 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/12.kmac_stress_all_with_rand_reset.3169317298
Short name T44
Test name
Test status
Simulation time 355980086836 ps
CPU time 1161.74 seconds
Started Apr 25 04:00:31 PM PDT 24
Finished Apr 25 04:19:53 PM PDT 24
Peak memory 290120 kb
Host smart-882ed70e-2d63-4731-9d95-682ba55160a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169317298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.3169317298 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.3442947465
Short name T1
Test name
Test status
Simulation time 1357849854959 ps
CPU time 5646.63 seconds
Started Apr 25 03:59:11 PM PDT 24
Finished Apr 25 05:33:19 PM PDT 24
Peak memory 651776 kb
Host smart-f8ec69ea-fac9-4352-8bcb-1971274ed012
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3442947465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.3442947465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.3869594175
Short name T32
Test name
Test status
Simulation time 45773548 ps
CPU time 1.53 seconds
Started Apr 25 04:11:32 PM PDT 24
Finished Apr 25 04:11:34 PM PDT 24
Peak memory 218196 kb
Host smart-2bbf44f4-68f5-4116-ab3c-7a99c17ff07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869594175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.3869594175 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_error.974136050
Short name T62
Test name
Test status
Simulation time 65996630642 ps
CPU time 460.61 seconds
Started Apr 25 04:10:53 PM PDT 24
Finished Apr 25 04:18:35 PM PDT 24
Peak memory 259120 kb
Host smart-4f51c929-5dbd-439f-85c4-ccd5659e6b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974136050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.974136050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1466428897
Short name T95
Test name
Test status
Simulation time 133285280 ps
CPU time 3.16 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 218980 kb
Host smart-526409b0-8523-41ed-88f7-96bf84c4b5ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466428897 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma
c_shadow_reg_errors_with_csr_rw.1466428897 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.444124339
Short name T1050
Test name
Test status
Simulation time 65062282 ps
CPU time 1.51 seconds
Started Apr 25 04:02:46 PM PDT 24
Finished Apr 25 04:02:48 PM PDT 24
Peak memory 226228 kb
Host smart-b8f3471a-e37d-4a39-9a84-95f178af11a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444124339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.444124339 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_key_error.2468529575
Short name T60
Test name
Test status
Simulation time 1110855630 ps
CPU time 6.93 seconds
Started Apr 25 03:56:57 PM PDT 24
Finished Apr 25 03:57:05 PM PDT 24
Peak memory 218100 kb
Host smart-33c46ee0-e361-40cd-bc47-4b375f204c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468529575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2468529575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.2067645499
Short name T57
Test name
Test status
Simulation time 3059468061 ps
CPU time 33.43 seconds
Started Apr 25 03:59:00 PM PDT 24
Finished Apr 25 03:59:35 PM PDT 24
Peak memory 218364 kb
Host smart-a3c30789-6f24-4bd4-8b26-d1b906a33463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067645499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.2067645499 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.491478035
Short name T75
Test name
Test status
Simulation time 49503224 ps
CPU time 1.32 seconds
Started Apr 25 03:58:30 PM PDT 24
Finished Apr 25 03:58:32 PM PDT 24
Peak memory 222740 kb
Host smart-11848f18-3c4c-4ab1-8c25-3bced9d65cf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=491478035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.491478035 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.1694566582
Short name T164
Test name
Test status
Simulation time 45802090 ps
CPU time 0.8 seconds
Started Apr 25 12:52:11 PM PDT 24
Finished Apr 25 12:52:15 PM PDT 24
Peak memory 216004 kb
Host smart-4acdad0f-9223-4790-88f2-26aaa78cacaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694566582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1694566582 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.3527886957
Short name T68
Test name
Test status
Simulation time 17009349070 ps
CPU time 45.76 seconds
Started Apr 25 04:04:27 PM PDT 24
Finished Apr 25 04:05:14 PM PDT 24
Peak memory 236844 kb
Host smart-d4e463b7-9433-422e-910e-bc2a7c41e561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527886957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.3527886957 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.682201339
Short name T37
Test name
Test status
Simulation time 1972078669 ps
CPU time 15.95 seconds
Started Apr 25 04:08:26 PM PDT 24
Finished Apr 25 04:08:43 PM PDT 24
Peak memory 229924 kb
Host smart-1536e31c-2bba-4165-ab3b-c44de2b3d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682201339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.682201339 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_stress_all.1358676662
Short name T72
Test name
Test status
Simulation time 9803548064 ps
CPU time 341.5 seconds
Started Apr 25 04:10:44 PM PDT 24
Finished Apr 25 04:16:26 PM PDT 24
Peak memory 273388 kb
Host smart-d7a85543-dc0b-436c-a756-ef0a99761858
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1358676662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1358676662 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.163698457
Short name T276
Test name
Test status
Simulation time 20745669 ps
CPU time 1.04 seconds
Started Apr 25 03:59:47 PM PDT 24
Finished Apr 25 03:59:49 PM PDT 24
Peak memory 218036 kb
Host smart-6db0cccc-ce90-430d-be20-fd02bb2b758f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=163698457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.163698457 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.1540428215
Short name T961
Test name
Test status
Simulation time 116368268 ps
CPU time 1.28 seconds
Started Apr 25 04:03:24 PM PDT 24
Finished Apr 25 04:03:26 PM PDT 24
Peak memory 218112 kb
Host smart-701bd154-87f7-44b0-985b-d18619863a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540428215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1540428215 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1878969136
Short name T146
Test name
Test status
Simulation time 139735072 ps
CPU time 1.4 seconds
Started Apr 25 12:52:14 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 216096 kb
Host smart-930d2475-1ad4-4113-94b7-c2623c9a4495
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878969136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.1878969136 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.3086628975
Short name T71
Test name
Test status
Simulation time 132752609 ps
CPU time 1.26 seconds
Started Apr 25 03:55:26 PM PDT 24
Finished Apr 25 03:55:28 PM PDT 24
Peak memory 218212 kb
Host smart-86aa376a-b5d7-4e70-a379-2fccf94500e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086628975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3086628975 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.84168079
Short name T30
Test name
Test status
Simulation time 865612262 ps
CPU time 47.36 seconds
Started Apr 25 04:04:51 PM PDT 24
Finished Apr 25 04:05:39 PM PDT 24
Peak memory 236124 kb
Host smart-9ca00dbc-e1ba-465e-bb39-a98ccc0d1155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84168079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.84168079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.1457497533
Short name T92
Test name
Test status
Simulation time 438285276 ps
CPU time 1.3 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 216476 kb
Host smart-f9dff18b-dd8a-436b-82d9-c22917d5798b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457497533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.1457497533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.kmac_alert_test.2471626712
Short name T311
Test name
Test status
Simulation time 53978308 ps
CPU time 0.88 seconds
Started Apr 25 04:02:07 PM PDT 24
Finished Apr 25 04:02:09 PM PDT 24
Peak memory 217888 kb
Host smart-0aba2cac-ec00-45aa-9a8e-da2d96bd50cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471626712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.2471626712 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_error.1697419020
Short name T15
Test name
Test status
Simulation time 21326962025 ps
CPU time 488 seconds
Started Apr 25 04:06:55 PM PDT 24
Finished Apr 25 04:15:04 PM PDT 24
Peak memory 255944 kb
Host smart-3f8b49fb-6c64-402b-8884-315aeeb30635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697419020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.1697419020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.3025899325
Short name T127
Test name
Test status
Simulation time 197676478 ps
CPU time 4.55 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 216140 kb
Host smart-19b79ce5-68b1-474a-85d4-acef3a2758cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025899325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.30258
99325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.507047983
Short name T162
Test name
Test status
Simulation time 14841179 ps
CPU time 0.77 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 215932 kb
Host smart-3100f595-5fa3-44b4-9a91-b48c5e9002fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507047983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.507047983 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.258676020
Short name T177
Test name
Test status
Simulation time 162807389 ps
CPU time 4.41 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:46 PM PDT 24
Peak memory 216104 kb
Host smart-5288b208-8e7e-476a-91fc-2581935f64c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258676020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.25867
6020 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.254259990
Short name T207
Test name
Test status
Simulation time 53843896491 ps
CPU time 3901.8 seconds
Started Apr 25 04:02:01 PM PDT 24
Finished Apr 25 05:07:05 PM PDT 24
Peak memory 572364 kb
Host smart-f7b936b1-b2f0-4349-91ce-d398335e8ed0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=254259990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.254259990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.1444470672
Short name T89
Test name
Test status
Simulation time 64816413 ps
CPU time 1.2 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 217408 kb
Host smart-d2670966-457a-4710-b689-ad891b0f078a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444470672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.1444470672 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.kmac_sideload.266119470
Short name T9
Test name
Test status
Simulation time 6605500223 ps
CPU time 153.06 seconds
Started Apr 25 03:55:48 PM PDT 24
Finished Apr 25 03:58:21 PM PDT 24
Peak memory 234688 kb
Host smart-961d9293-1573-441a-8c0d-52a87f93f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266119470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.266119470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.441375975
Short name T81
Test name
Test status
Simulation time 19015611910 ps
CPU time 131.42 seconds
Started Apr 25 04:04:42 PM PDT 24
Finished Apr 25 04:06:54 PM PDT 24
Peak memory 235760 kb
Host smart-7d971fc6-750a-4483-ae7c-004a6cda7258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441375975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.441375975 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2891746823
Short name T121
Test name
Test status
Simulation time 114521539 ps
CPU time 2.71 seconds
Started Apr 25 12:52:30 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 216160 kb
Host smart-014cdb55-6783-4cd4-a6d3-7261ae402b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891746823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2891
746823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.199852362
Short name T179
Test name
Test status
Simulation time 139059389 ps
CPU time 2.81 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:30 PM PDT 24
Peak memory 216044 kb
Host smart-6d8ca417-4c00-4ec5-be7f-4bc697127cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199852362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.199852
362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_mubi.1387093583
Short name T46
Test name
Test status
Simulation time 15083735459 ps
CPU time 92.1 seconds
Started Apr 25 03:55:20 PM PDT 24
Finished Apr 25 03:56:53 PM PDT 24
Peak memory 231436 kb
Host smart-f0400e4b-8ad6-4dfc-946f-63cf489238ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387093583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.1387093583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/16.kmac_key_error.3806876120
Short name T58
Test name
Test status
Simulation time 4921227715 ps
CPU time 6.38 seconds
Started Apr 25 04:02:03 PM PDT 24
Finished Apr 25 04:02:10 PM PDT 24
Peak memory 218184 kb
Host smart-99754e1d-e085-45c1-a031-1e0faa805d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806876120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.3806876120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_sideload.2777926766
Short name T196
Test name
Test status
Simulation time 89602850046 ps
CPU time 463.05 seconds
Started Apr 25 04:00:16 PM PDT 24
Finished Apr 25 04:08:00 PM PDT 24
Peak memory 251740 kb
Host smart-6161a792-191b-4e46-a041-efca7d481624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777926766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2777926766 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.2315740674
Short name T1099
Test name
Test status
Simulation time 367876986 ps
CPU time 4.53 seconds
Started Apr 25 12:52:08 PM PDT 24
Finished Apr 25 12:52:16 PM PDT 24
Peak memory 216104 kb
Host smart-2727ebdf-abea-472d-8c38-2beebef7d5ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315740674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.2315740
674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.657552911
Short name T1094
Test name
Test status
Simulation time 576992790 ps
CPU time 8.16 seconds
Started Apr 25 12:52:11 PM PDT 24
Finished Apr 25 12:52:22 PM PDT 24
Peak memory 216148 kb
Host smart-6e6aa041-008a-45fb-bfa1-72890e57cf2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657552911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.65755291
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.2780174839
Short name T1164
Test name
Test status
Simulation time 50442563 ps
CPU time 1.03 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 215920 kb
Host smart-168ffcda-0e7c-40b2-a0b3-f98e597d4635
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780174839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.2780174
839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.716647571
Short name T1100
Test name
Test status
Simulation time 223086356 ps
CPU time 1.52 seconds
Started Apr 25 12:52:05 PM PDT 24
Finished Apr 25 12:52:09 PM PDT 24
Peak memory 217452 kb
Host smart-6b5f4a35-dee0-4fe1-8649-8ca13940c4f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716647571 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.716647571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.847554896
Short name T1165
Test name
Test status
Simulation time 28651238 ps
CPU time 0.93 seconds
Started Apr 25 12:52:14 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 215888 kb
Host smart-2b499cab-2e56-4138-8223-c04caaad594f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847554896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.847554896 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.2945943535
Short name T1160
Test name
Test status
Simulation time 15388615 ps
CPU time 0.82 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 215844 kb
Host smart-2a91369c-7eec-4cfd-91cf-648ef0515aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945943535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2945943535 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.3701838230
Short name T1087
Test name
Test status
Simulation time 17865082 ps
CPU time 0.74 seconds
Started Apr 25 12:52:17 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 215912 kb
Host smart-d89dd03d-4342-4902-9436-e8794fd5d271
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701838230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3701838230
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3940234464
Short name T1097
Test name
Test status
Simulation time 88257418 ps
CPU time 1.45 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 216068 kb
Host smart-c52935ff-2fa4-4c99-af84-77ee8a7e5399
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940234464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr
_outstanding.3940234464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.64290966
Short name T1238
Test name
Test status
Simulation time 63057083 ps
CPU time 1.77 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 218468 kb
Host smart-301eac34-9a53-4b6a-a035-9592c4c88a3e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64290966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_s
hadow_reg_errors_with_csr_rw.64290966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.3698976046
Short name T1224
Test name
Test status
Simulation time 106923112 ps
CPU time 3.15 seconds
Started Apr 25 12:52:07 PM PDT 24
Finished Apr 25 12:52:13 PM PDT 24
Peak memory 216268 kb
Host smart-f3e5df2f-fe1e-4a3c-88e2-3dd26ffc0437
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698976046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.3698976046 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.4042813707
Short name T1157
Test name
Test status
Simulation time 268969853 ps
CPU time 3 seconds
Started Apr 25 12:52:24 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 216028 kb
Host smart-372d9bbd-30c9-4ea8-8cb2-db32d2ba4609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042813707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.40428
13707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.3960313319
Short name T1156
Test name
Test status
Simulation time 397808771 ps
CPU time 9.11 seconds
Started Apr 25 12:52:09 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216088 kb
Host smart-2fb64185-3715-4226-be39-56660fd36561
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960313319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.3960313
319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.958317153
Short name T1163
Test name
Test status
Simulation time 1177762566 ps
CPU time 15.96 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 216136 kb
Host smart-0b07306b-6df5-4b1c-b6f3-a42d53f051ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958317153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.95831715
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.2644055928
Short name T1191
Test name
Test status
Simulation time 72202438 ps
CPU time 1.05 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 216012 kb
Host smart-b4fcc81f-7033-409b-bf68-ed8d6ad69e2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644055928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.2644055
928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1302574474
Short name T1161
Test name
Test status
Simulation time 59886782 ps
CPU time 1.83 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 221068 kb
Host smart-0929ee2c-c1a6-46ed-af56-a54ad9f9be6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302574474 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1302574474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.2055067931
Short name T1133
Test name
Test status
Simulation time 51972047 ps
CPU time 1.07 seconds
Started Apr 25 12:52:09 PM PDT 24
Finished Apr 25 12:52:12 PM PDT 24
Peak memory 216096 kb
Host smart-fcdb8ad9-d0b2-48dc-af82-653e24050672
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055067931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.2055067931 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.2841489497
Short name T1206
Test name
Test status
Simulation time 89329967 ps
CPU time 0.79 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 215920 kb
Host smart-2fa9127f-2e6d-46a7-82c0-620a801b70fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841489497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2841489497 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.725871905
Short name T145
Test name
Test status
Simulation time 31205276 ps
CPU time 1.14 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:25 PM PDT 24
Peak memory 216180 kb
Host smart-796aea7c-c9a6-4b66-a6be-49db95b7d7ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725871905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partial
_access.725871905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.790322497
Short name T1117
Test name
Test status
Simulation time 31296844 ps
CPU time 0.72 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 215848 kb
Host smart-149b8534-7c3e-4cfd-b00c-12682b26d05d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790322497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.790322497 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2845960474
Short name T151
Test name
Test status
Simulation time 123881488 ps
CPU time 2.63 seconds
Started Apr 25 12:52:07 PM PDT 24
Finished Apr 25 12:52:13 PM PDT 24
Peak memory 216080 kb
Host smart-d9e1a828-2836-4498-afa9-8fb3429f284d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845960474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2845960474 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.2891128794
Short name T1235
Test name
Test status
Simulation time 57035118 ps
CPU time 1.17 seconds
Started Apr 25 12:52:06 PM PDT 24
Finished Apr 25 12:52:11 PM PDT 24
Peak memory 216352 kb
Host smart-9ba6409e-b231-4aad-9256-d95d7c1ac136
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891128794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.2891128794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3565962318
Short name T91
Test name
Test status
Simulation time 76631515 ps
CPU time 2.05 seconds
Started Apr 25 12:52:10 PM PDT 24
Finished Apr 25 12:52:14 PM PDT 24
Peak memory 218232 kb
Host smart-b1e4ce32-fc79-4210-b2f7-0d97289f1918
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565962318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3565962318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.776882391
Short name T1207
Test name
Test status
Simulation time 321027211 ps
CPU time 3.21 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 216228 kb
Host smart-d9b73ae9-4929-4d3b-a36f-7adfd482d094
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776882391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.776882391 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.811085107
Short name T123
Test name
Test status
Simulation time 263542760 ps
CPU time 2.45 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 216092 kb
Host smart-0579ff0b-c7fd-4290-985b-ac685e46ecab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811085107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.811085
107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3389488502
Short name T156
Test name
Test status
Simulation time 284733967 ps
CPU time 2.31 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 221756 kb
Host smart-27e002d7-533a-46f5-b16e-08c85b471b90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389488502 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3389488502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.1604076088
Short name T1093
Test name
Test status
Simulation time 45032840 ps
CPU time 1.17 seconds
Started Apr 25 12:52:17 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 216156 kb
Host smart-c824e0cb-0fd3-47c5-8209-ffb5e3406f10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604076088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1604076088 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.4137848214
Short name T1108
Test name
Test status
Simulation time 13058017 ps
CPU time 0.75 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 215888 kb
Host smart-3d9c2f96-7dc9-4c43-8157-2cea56e62412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137848214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.4137848214 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.3040954393
Short name T1078
Test name
Test status
Simulation time 189814790 ps
CPU time 2.55 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 216156 kb
Host smart-931f3709-16fc-402c-8af8-1552b9292435
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040954393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs
r_outstanding.3040954393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3028076824
Short name T1145
Test name
Test status
Simulation time 57699305 ps
CPU time 1.1 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:22 PM PDT 24
Peak memory 216336 kb
Host smart-ffbd5424-93c9-46b3-9e4b-b29cf300a353
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028076824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3028076824 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2598336250
Short name T1109
Test name
Test status
Simulation time 96440396 ps
CPU time 1.77 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 218764 kb
Host smart-94abffa1-4dd4-4449-ae9a-74ec7c9079c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598336250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2598336250 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.1859099113
Short name T1209
Test name
Test status
Simulation time 255796792 ps
CPU time 1.64 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 216276 kb
Host smart-d030a3b3-5fde-4f78-8f9c-a39b7b1e35eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859099113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.1859099113 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.96581202
Short name T1223
Test name
Test status
Simulation time 269206836 ps
CPU time 2.02 seconds
Started Apr 25 12:52:24 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 221064 kb
Host smart-c61c2649-7c55-41bf-8a36-9a25810a0fbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96581202 -assert nopostproc +UVM_TESTNAME=k
mac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.96581202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.580359516
Short name T1219
Test name
Test status
Simulation time 109569918 ps
CPU time 1.06 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:28 PM PDT 24
Peak memory 216140 kb
Host smart-fd859b4b-63f6-4484-abd3-cabbc1865080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580359516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.580359516 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.2960600176
Short name T1124
Test name
Test status
Simulation time 16542592 ps
CPU time 0.77 seconds
Started Apr 25 12:52:30 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 215856 kb
Host smart-55e2c964-fc0c-47f9-a302-d33d2963e5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960600176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.2960600176 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.1176116266
Short name T1123
Test name
Test status
Simulation time 451060330 ps
CPU time 2.68 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 216020 kb
Host smart-05f82b0e-9379-45d0-972a-48d44c824f6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176116266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_cs
r_outstanding.1176116266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.1762150059
Short name T96
Test name
Test status
Simulation time 56646356 ps
CPU time 1.07 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 216332 kb
Host smart-3dfb50b5-13ba-4f55-b580-3122a71df7aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762150059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.1762150059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.3705776509
Short name T90
Test name
Test status
Simulation time 185075238 ps
CPU time 2.74 seconds
Started Apr 25 12:52:20 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 220040 kb
Host smart-d6b80344-52f9-41c7-94f5-7ea77fca9e3b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705776509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.3705776509 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.1014975312
Short name T159
Test name
Test status
Simulation time 380932117 ps
CPU time 2.6 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 216136 kb
Host smart-812f0db9-fb0f-485a-a31b-4918284c69af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014975312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.1014975312 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3710026378
Short name T173
Test name
Test status
Simulation time 378012625 ps
CPU time 5.2 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 216132 kb
Host smart-b063604d-7076-4312-9df9-4c95d352ee1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710026378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3710
026378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.3426426438
Short name T1231
Test name
Test status
Simulation time 162832334 ps
CPU time 1.52 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:38 PM PDT 24
Peak memory 219096 kb
Host smart-602c997a-5890-4b5b-8cad-ca90b90f8ea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426426438 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.3426426438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.2293335674
Short name T1110
Test name
Test status
Simulation time 17745685 ps
CPU time 1.16 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 216168 kb
Host smart-4fda92bd-0108-4db1-87ae-e690d81b1237
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293335674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.2293335674 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1605949950
Short name T126
Test name
Test status
Simulation time 31517623 ps
CPU time 0.79 seconds
Started Apr 25 12:52:30 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 215820 kb
Host smart-9cb350f7-4c9b-4b04-aeb4-d3ccbd3510a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605949950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1605949950 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3107986580
Short name T1082
Test name
Test status
Simulation time 46013769 ps
CPU time 2.25 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 216028 kb
Host smart-b60c3f99-8c2f-43eb-9a97-14bfb71bc44a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107986580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3107986580 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.75177872
Short name T1176
Test name
Test status
Simulation time 101254913 ps
CPU time 1.02 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 216192 kb
Host smart-607796a9-7b1c-4495-bd36-55c8ee52343f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75177872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_e
rrors.75177872 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1668537715
Short name T1211
Test name
Test status
Simulation time 194808780 ps
CPU time 2.48 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:25 PM PDT 24
Peak memory 219824 kb
Host smart-73105054-6f71-4f0c-9d40-7e8243eb19e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668537715 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.1668537715 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.295210324
Short name T1153
Test name
Test status
Simulation time 58378042 ps
CPU time 1.94 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 216224 kb
Host smart-f9982323-228f-4268-a7ff-9f2d36f1f50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295210324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.295210324 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2254381382
Short name T1114
Test name
Test status
Simulation time 263364629 ps
CPU time 2.49 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 220588 kb
Host smart-cae48955-1e36-4ccb-bfda-1444abfe5017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254381382 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2254381382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.198920022
Short name T1205
Test name
Test status
Simulation time 41980953 ps
CPU time 0.93 seconds
Started Apr 25 12:52:32 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 215828 kb
Host smart-aaccf50d-26e4-4797-8ea2-db862905dbe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198920022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.198920022 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.4015969591
Short name T1213
Test name
Test status
Simulation time 14297701 ps
CPU time 0.82 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:28 PM PDT 24
Peak memory 215884 kb
Host smart-301938e9-0b89-4179-8a58-8023db0c10bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015969591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.4015969591 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.3750463740
Short name T1106
Test name
Test status
Simulation time 51467055 ps
CPU time 1.61 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216008 kb
Host smart-3823a308-a9c5-4579-85aa-02bc2e50c674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750463740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs
r_outstanding.3750463740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3489940748
Short name T1105
Test name
Test status
Simulation time 37695077 ps
CPU time 1.08 seconds
Started Apr 25 12:52:24 PM PDT 24
Finished Apr 25 12:52:26 PM PDT 24
Peak memory 216480 kb
Host smart-604e53e7-f3c3-4775-adb2-faba13cd3c75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489940748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3489940748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3360162395
Short name T94
Test name
Test status
Simulation time 157018519 ps
CPU time 2.16 seconds
Started Apr 25 12:52:38 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 219584 kb
Host smart-060c4138-223d-455c-b9cb-dae5717c4700
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360162395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.3360162395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.1893943783
Short name T1098
Test name
Test status
Simulation time 46739366 ps
CPU time 2.41 seconds
Started Apr 25 12:52:18 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216292 kb
Host smart-e0e474cb-4ea5-454e-b132-e948f5e57f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893943783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.1893943783 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3198789470
Short name T172
Test name
Test status
Simulation time 233981453 ps
CPU time 4.7 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 216004 kb
Host smart-56e78f22-c7db-4f61-b1fd-f48d42a75e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198789470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3198
789470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2913755700
Short name T1222
Test name
Test status
Simulation time 134802037 ps
CPU time 1.46 seconds
Started Apr 25 12:52:36 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 218488 kb
Host smart-27248492-c490-49fd-8c89-4de24d1f2e38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913755700 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2913755700 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2142720234
Short name T1122
Test name
Test status
Simulation time 14898266 ps
CPU time 0.94 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 215828 kb
Host smart-56a3cb2d-0b03-4865-a9be-85bad675cd7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142720234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2142720234 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.262935507
Short name T1227
Test name
Test status
Simulation time 35748306 ps
CPU time 0.77 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 215964 kb
Host smart-76071f0d-4191-43fc-b33b-7a1cea300f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262935507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.262935507 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.1628181411
Short name T1194
Test name
Test status
Simulation time 154947795 ps
CPU time 1.49 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 216120 kb
Host smart-53698c69-a5c8-4f47-9352-3ff8693a57bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628181411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.1628181411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.2827355913
Short name T1212
Test name
Test status
Simulation time 20553990 ps
CPU time 0.99 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 216240 kb
Host smart-4bea32a6-18c1-4758-a92e-0478023ada3a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827355913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.2827355913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.1699175397
Short name T1218
Test name
Test status
Simulation time 244788759 ps
CPU time 3.32 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 216124 kb
Host smart-c31f5497-3c2e-4164-b489-c536a7893a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699175397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1699175397 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.1487847688
Short name T1172
Test name
Test status
Simulation time 374471827 ps
CPU time 2.9 seconds
Started Apr 25 12:52:36 PM PDT 24
Finished Apr 25 12:52:41 PM PDT 24
Peak memory 216168 kb
Host smart-7a97cfe8-aa6b-4273-9032-837c748d66fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487847688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.1487
847688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.4080112568
Short name T1178
Test name
Test status
Simulation time 161948821 ps
CPU time 1.58 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 219196 kb
Host smart-b283e5c7-017c-4a68-8ea7-735db3bb030c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080112568 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.4080112568 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.2420821220
Short name T1233
Test name
Test status
Simulation time 52276570 ps
CPU time 0.91 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:37 PM PDT 24
Peak memory 215848 kb
Host smart-a9ed9d64-f1b4-4f3a-8dc9-25418f4b07b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420821220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2420821220 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.3410846879
Short name T1121
Test name
Test status
Simulation time 21609189 ps
CPU time 0.83 seconds
Started Apr 25 12:52:32 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 215812 kb
Host smart-be93f422-487f-4d68-a5ea-5e0b0ddda79d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410846879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.3410846879 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.3318722053
Short name T1196
Test name
Test status
Simulation time 213070589 ps
CPU time 2.33 seconds
Started Apr 25 12:52:41 PM PDT 24
Finished Apr 25 12:52:46 PM PDT 24
Peak memory 216064 kb
Host smart-bbc1715c-3783-4ea1-936a-7d4736675eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318722053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.3318722053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.1618394311
Short name T93
Test name
Test status
Simulation time 63089633 ps
CPU time 1.02 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 216456 kb
Host smart-da9e063b-0bfc-4bce-b18e-033dc8f4f9b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618394311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.1618394311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2459304227
Short name T1162
Test name
Test status
Simulation time 68323468 ps
CPU time 2.44 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:49 PM PDT 24
Peak memory 219880 kb
Host smart-8efe07e0-5d32-4b4b-ac40-08e14646e620
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459304227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2459304227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.1941528616
Short name T1101
Test name
Test status
Simulation time 180428752 ps
CPU time 2.89 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 216176 kb
Host smart-615439d3-718a-483f-a525-edc042f0d8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941528616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.1941528616 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1202055499
Short name T1200
Test name
Test status
Simulation time 400477306 ps
CPU time 2.85 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:41 PM PDT 24
Peak memory 216060 kb
Host smart-30b6440a-7e03-438b-b1e1-8f5f0ca59a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202055499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1202
055499 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2885030825
Short name T1090
Test name
Test status
Simulation time 20290247 ps
CPU time 1.41 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 217116 kb
Host smart-a85d4d5a-ee60-4747-bdb2-a49cbeb3c503
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885030825 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2885030825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.2350039239
Short name T1083
Test name
Test status
Simulation time 47513535 ps
CPU time 1.08 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 216080 kb
Host smart-35a9fa88-492d-4c6b-adf0-158951a52b44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350039239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.2350039239 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.290003338
Short name T1119
Test name
Test status
Simulation time 62004908 ps
CPU time 0.81 seconds
Started Apr 25 12:52:41 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 215932 kb
Host smart-abd2ba86-e89a-4d96-97ac-8351d698b4f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290003338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.290003338 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.3520007638
Short name T1079
Test name
Test status
Simulation time 82365245 ps
CPU time 1.39 seconds
Started Apr 25 12:52:36 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 216008 kb
Host smart-74b62fdd-04d4-4188-be72-42be3560d545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520007638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs
r_outstanding.3520007638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.2010049905
Short name T1134
Test name
Test status
Simulation time 278958644 ps
CPU time 1.03 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 216156 kb
Host smart-23d92aaa-8b8a-40c1-ac73-7526fb359f76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010049905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.2010049905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2575404891
Short name T1241
Test name
Test status
Simulation time 98896141 ps
CPU time 1.51 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 216424 kb
Host smart-8d474b43-3f6a-4f5b-a3c9-09d489d2dfab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575404891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.2575404891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.1800182457
Short name T1118
Test name
Test status
Simulation time 286536582 ps
CPU time 2.37 seconds
Started Apr 25 12:52:46 PM PDT 24
Finished Apr 25 12:52:50 PM PDT 24
Peak memory 216244 kb
Host smart-f7fdbf47-631a-4873-81ec-c37cd3842551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800182457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.1800182457 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.739982154
Short name T1185
Test name
Test status
Simulation time 244645126 ps
CPU time 2.34 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 220852 kb
Host smart-3fa955d0-b375-4ff0-826c-dc56816cb84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739982154 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.739982154 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.592852073
Short name T1225
Test name
Test status
Simulation time 52648384 ps
CPU time 0.95 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 215972 kb
Host smart-42f5188c-f967-4759-920e-99fa33deb003
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592852073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.592852073 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.1837760725
Short name T163
Test name
Test status
Simulation time 18259399 ps
CPU time 0.8 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:37 PM PDT 24
Peak memory 215948 kb
Host smart-fa69dce6-6e7c-4b0e-8e36-e5367b8b8b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837760725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.1837760725 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3303727086
Short name T1112
Test name
Test status
Simulation time 26348053 ps
CPU time 1.44 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:38 PM PDT 24
Peak memory 216152 kb
Host smart-66b8b7c7-ca4a-4fc3-a759-db3dd7be8c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303727086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3303727086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.691358135
Short name T1182
Test name
Test status
Simulation time 17967717 ps
CPU time 0.84 seconds
Started Apr 25 12:52:32 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 215872 kb
Host smart-7a566ed7-125e-41f6-97a7-7dea857a00f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691358135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_
errors.691358135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.2377342098
Short name T1167
Test name
Test status
Simulation time 70822028 ps
CPU time 1.94 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 218776 kb
Host smart-d85ab6d1-4951-4423-ad39-5d03a7bdef70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377342098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kma
c_shadow_reg_errors_with_csr_rw.2377342098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.2512768417
Short name T1095
Test name
Test status
Simulation time 129319030 ps
CPU time 2.98 seconds
Started Apr 25 12:52:51 PM PDT 24
Finished Apr 25 12:52:55 PM PDT 24
Peak memory 216228 kb
Host smart-f222c437-f39a-41aa-bf4a-4075203487d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512768417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.2512768417 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3247800107
Short name T1198
Test name
Test status
Simulation time 108658659 ps
CPU time 2.81 seconds
Started Apr 25 12:52:34 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 216148 kb
Host smart-6e5fc414-09a9-44cd-96fe-a38f800ce67d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247800107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3247
800107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.157341913
Short name T180
Test name
Test status
Simulation time 23383569 ps
CPU time 1.65 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:44 PM PDT 24
Peak memory 218060 kb
Host smart-f017aecb-2bf0-4a60-af18-d6a78839b520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157341913 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.157341913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.1515998189
Short name T1141
Test name
Test status
Simulation time 78820773 ps
CPU time 0.95 seconds
Started Apr 25 12:52:34 PM PDT 24
Finished Apr 25 12:52:36 PM PDT 24
Peak memory 215932 kb
Host smart-936a8ce0-046f-409e-b498-13d4b2c85c62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515998189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1515998189 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.865745952
Short name T166
Test name
Test status
Simulation time 19516463 ps
CPU time 0.84 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 215916 kb
Host smart-ecf22d57-3511-42eb-9d91-25dcb2ed354d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865745952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.865745952 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2935185037
Short name T1181
Test name
Test status
Simulation time 211365930 ps
CPU time 1.55 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:30 PM PDT 24
Peak memory 216084 kb
Host smart-a186af6c-0eb8-4d8c-8d88-885f09c2ebe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935185037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2935185037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4272080333
Short name T1139
Test name
Test status
Simulation time 49869990 ps
CPU time 1.14 seconds
Started Apr 25 12:52:34 PM PDT 24
Finished Apr 25 12:52:37 PM PDT 24
Peak memory 216424 kb
Host smart-8b60ae32-fdae-4987-bf5a-e53178d8186a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272080333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg
_errors.4272080333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1428736172
Short name T98
Test name
Test status
Simulation time 125493825 ps
CPU time 3.06 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 218888 kb
Host smart-c56a779f-5b2e-4cb6-b7b9-b84a61975f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428736172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.1428736172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.906407974
Short name T1104
Test name
Test status
Simulation time 499226929 ps
CPU time 3.57 seconds
Started Apr 25 12:52:33 PM PDT 24
Finished Apr 25 12:52:38 PM PDT 24
Peak memory 216224 kb
Host smart-537ce9ef-b6de-4fdc-8495-b20a87aa3922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906407974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.906407974 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.522573953
Short name T175
Test name
Test status
Simulation time 101952834 ps
CPU time 4.12 seconds
Started Apr 25 12:52:33 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 216096 kb
Host smart-f33b34c0-5761-4770-abce-ee27213073cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522573953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.52257
3953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.4080663778
Short name T1151
Test name
Test status
Simulation time 41489574 ps
CPU time 1.46 seconds
Started Apr 25 12:52:46 PM PDT 24
Finished Apr 25 12:52:49 PM PDT 24
Peak memory 217192 kb
Host smart-014227df-feb1-4a64-9424-e6834bc619a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080663778 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.4080663778 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.3038585446
Short name T1089
Test name
Test status
Simulation time 46190933 ps
CPU time 1.12 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 216136 kb
Host smart-672094fd-e28a-4d08-b88c-8e18dc70bba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038585446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.3038585446 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2927745090
Short name T1199
Test name
Test status
Simulation time 16615348 ps
CPU time 0.77 seconds
Started Apr 25 12:52:43 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 215928 kb
Host smart-48ffa08b-e89d-448e-a6b9-e36da8b6e39d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927745090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2927745090 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.3713600912
Short name T1128
Test name
Test status
Simulation time 120867946 ps
CPU time 2.42 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 216136 kb
Host smart-5d118024-2214-4f9f-bb46-df9d12ea5bfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713600912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs
r_outstanding.3713600912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.307739891
Short name T1197
Test name
Test status
Simulation time 34669639 ps
CPU time 1.19 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 216376 kb
Host smart-ffa1665a-e3a3-4fc7-8758-de3f3a0841fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307739891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_
errors.307739891 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.1873376750
Short name T88
Test name
Test status
Simulation time 142854681 ps
CPU time 2.72 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 219164 kb
Host smart-473fcdd1-7221-4bb1-9287-451c9695a5a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873376750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma
c_shadow_reg_errors_with_csr_rw.1873376750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.2958477584
Short name T1132
Test name
Test status
Simulation time 757668646 ps
CPU time 2.86 seconds
Started Apr 25 12:52:31 PM PDT 24
Finished Apr 25 12:52:36 PM PDT 24
Peak memory 216148 kb
Host smart-0d6acea4-8eea-4bb2-9b3e-03711f14d187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958477584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.2958477584 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.4191802757
Short name T1226
Test name
Test status
Simulation time 88019340 ps
CPU time 2.51 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 216156 kb
Host smart-5e93bb0f-13fe-4e63-a015-55980f98bc8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191802757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.4191
802757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.2706624031
Short name T1214
Test name
Test status
Simulation time 495871372 ps
CPU time 5.17 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 216104 kb
Host smart-c65ba9cf-a1fc-4d37-83b7-d95a603a6983
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706624031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.2706624
031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.1400842191
Short name T1187
Test name
Test status
Simulation time 1941454098 ps
CPU time 9.96 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 216092 kb
Host smart-233dff8d-aa4f-4093-92dd-f3d19692f4ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400842191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.1400842
191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.830063191
Short name T1131
Test name
Test status
Simulation time 33141212 ps
CPU time 1.17 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 216104 kb
Host smart-3e72d3f8-df2f-436a-8d45-6bd96a833725
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830063191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.83006319
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.933903390
Short name T1103
Test name
Test status
Simulation time 67760029 ps
CPU time 2.3 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 219424 kb
Host smart-e308385a-1123-46f1-888d-56200cb115c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933903390 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.933903390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.1041898942
Short name T1174
Test name
Test status
Simulation time 35051503 ps
CPU time 1.12 seconds
Started Apr 25 12:52:10 PM PDT 24
Finished Apr 25 12:52:13 PM PDT 24
Peak memory 216160 kb
Host smart-ded4dc76-a3fd-4868-8ad3-deb8c64ce3f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041898942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.1041898942 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2223710499
Short name T1125
Test name
Test status
Simulation time 43518576 ps
CPU time 0.76 seconds
Started Apr 25 12:52:10 PM PDT 24
Finished Apr 25 12:52:13 PM PDT 24
Peak memory 215824 kb
Host smart-74f676c6-914b-4b39-af7c-2c47bc483aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223710499 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2223710499 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3284855323
Short name T148
Test name
Test status
Simulation time 41961703 ps
CPU time 1.47 seconds
Started Apr 25 12:52:07 PM PDT 24
Finished Apr 25 12:52:12 PM PDT 24
Peak memory 216164 kb
Host smart-715d2f8f-a59a-48b1-b590-b8d1ecafc28d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284855323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia
l_access.3284855323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.1083361359
Short name T1155
Test name
Test status
Simulation time 111184541 ps
CPU time 0.73 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 215916 kb
Host smart-90557988-1547-4424-baea-380c20170d71
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083361359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1083361359
+enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.2039442559
Short name T1170
Test name
Test status
Simulation time 43192231 ps
CPU time 1.41 seconds
Started Apr 25 12:52:26 PM PDT 24
Finished Apr 25 12:52:28 PM PDT 24
Peak memory 216124 kb
Host smart-3838ab74-5173-47ba-9692-0a1cdf3dc3e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039442559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.2039442559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.1649270015
Short name T1216
Test name
Test status
Simulation time 104540250 ps
CPU time 1.25 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 217384 kb
Host smart-eddb80d0-951d-470c-9b32-170523a9e856
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649270015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_
errors.1649270015 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3641209893
Short name T100
Test name
Test status
Simulation time 34565275 ps
CPU time 1.57 seconds
Started Apr 25 12:52:11 PM PDT 24
Finished Apr 25 12:52:16 PM PDT 24
Peak memory 216504 kb
Host smart-c86cafe0-d406-448b-9d5f-9f87039a244e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641209893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3641209893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.1167558630
Short name T1154
Test name
Test status
Simulation time 1162553918 ps
CPU time 2.63 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 216256 kb
Host smart-f5971186-519c-4e26-9f51-ac47fe4ad9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167558630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.1167558630 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3423205420
Short name T178
Test name
Test status
Simulation time 105507541 ps
CPU time 2.55 seconds
Started Apr 25 12:52:08 PM PDT 24
Finished Apr 25 12:52:13 PM PDT 24
Peak memory 216104 kb
Host smart-9dcb5a1e-eaeb-4d35-a81c-45f71a54453f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423205420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.34232
05420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.3083773692
Short name T1230
Test name
Test status
Simulation time 13712059 ps
CPU time 0.87 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 215920 kb
Host smart-9a1b6648-fa84-4ef6-815e-cdccf1d68dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083773692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.3083773692 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.1418033867
Short name T1210
Test name
Test status
Simulation time 27003729 ps
CPU time 0.76 seconds
Started Apr 25 12:52:49 PM PDT 24
Finished Apr 25 12:52:51 PM PDT 24
Peak memory 215920 kb
Host smart-5f132a4f-7e79-479a-8baa-e5f2ca4e450a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418033867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1418033867 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.3145826176
Short name T1193
Test name
Test status
Simulation time 47209315 ps
CPU time 0.82 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 215924 kb
Host smart-121e1ee2-65e5-4179-b932-2651ecef92c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145826176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.3145826176 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2163033422
Short name T1149
Test name
Test status
Simulation time 114109804 ps
CPU time 0.78 seconds
Started Apr 25 12:52:56 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 215988 kb
Host smart-16de5785-a355-4977-b38e-e64469dc84be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163033422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2163033422 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.3962774930
Short name T165
Test name
Test status
Simulation time 34204036 ps
CPU time 0.76 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:42 PM PDT 24
Peak memory 215884 kb
Host smart-781a7b2b-93b7-408e-979d-6694981464df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962774930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3962774930 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.4039852077
Short name T1203
Test name
Test status
Simulation time 37621597 ps
CPU time 0.78 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 215888 kb
Host smart-de560c12-0513-4e1f-987a-fa8b16da01cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039852077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.4039852077 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.941823204
Short name T125
Test name
Test status
Simulation time 129282889 ps
CPU time 0.8 seconds
Started Apr 25 12:52:38 PM PDT 24
Finished Apr 25 12:52:41 PM PDT 24
Peak memory 215952 kb
Host smart-8c4d435e-6a34-4db2-8db6-b6f4fbe72bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941823204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.941823204 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.1421898994
Short name T1136
Test name
Test status
Simulation time 56422603 ps
CPU time 0.85 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 215892 kb
Host smart-0e9ec362-6add-48f4-b7c8-7c8edb641a5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421898994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.1421898994 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.2386913392
Short name T1232
Test name
Test status
Simulation time 18338414 ps
CPU time 0.78 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 215860 kb
Host smart-2c4be744-d520-4560-ae26-20729f524ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386913392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.2386913392 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3762582804
Short name T1221
Test name
Test status
Simulation time 1258790060 ps
CPU time 5.62 seconds
Started Apr 25 12:52:17 PM PDT 24
Finished Apr 25 12:52:25 PM PDT 24
Peak memory 216088 kb
Host smart-05751c19-41a4-4976-9424-4835ff9b4122
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762582804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3762582
804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.1139291306
Short name T1236
Test name
Test status
Simulation time 3836065576 ps
CPU time 18.93 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:40 PM PDT 24
Peak memory 216168 kb
Host smart-4ed106ea-299e-4123-a338-1dbb28484feb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139291306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.1139291
306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4172912671
Short name T1186
Test name
Test status
Simulation time 62917811 ps
CPU time 1.06 seconds
Started Apr 25 12:52:14 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 216084 kb
Host smart-c17b07a5-6037-4f1a-98fe-3efb3b5d13d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172912671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4172912
671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.3145884852
Short name T1237
Test name
Test status
Simulation time 35157631 ps
CPU time 2.43 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 220980 kb
Host smart-a567538b-912c-46d5-a1e2-9f674aba90fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145884852 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.3145884852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.775791474
Short name T154
Test name
Test status
Simulation time 35406102 ps
CPU time 0.99 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 215856 kb
Host smart-a09e0d10-bf5c-44bd-a65f-f10a235cd009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775791474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.775791474 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.861153412
Short name T147
Test name
Test status
Simulation time 60681076 ps
CPU time 1.27 seconds
Started Apr 25 12:52:31 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 216180 kb
Host smart-037261d6-c6ff-4988-a3b9-1754a38b42c7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861153412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partial
_access.861153412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.1598420666
Short name T1135
Test name
Test status
Simulation time 23051594 ps
CPU time 0.74 seconds
Started Apr 25 12:52:11 PM PDT 24
Finished Apr 25 12:52:15 PM PDT 24
Peak memory 215888 kb
Host smart-2b5613d6-0fec-4c0f-a0a6-3071ba2beafa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598420666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1598420666
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1920701565
Short name T1148
Test name
Test status
Simulation time 115809109 ps
CPU time 1.64 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216120 kb
Host smart-7427d70c-1676-4cc9-a997-5221d2e35ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920701565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1920701565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.169698211
Short name T1130
Test name
Test status
Simulation time 28046319 ps
CPU time 1.2 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 217472 kb
Host smart-61ade8dd-0de2-47d9-b3fb-c3164c6c6f88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169698211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_e
rrors.169698211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.581882485
Short name T1179
Test name
Test status
Simulation time 100420109 ps
CPU time 1.74 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:28 PM PDT 24
Peak memory 219632 kb
Host smart-63e48819-32a3-4d3f-a5f6-ceab6153563d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581882485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_
shadow_reg_errors_with_csr_rw.581882485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1365778072
Short name T1192
Test name
Test status
Simulation time 186076776 ps
CPU time 1.6 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216200 kb
Host smart-60530a4a-d83d-464b-8bc6-05718d3752cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365778072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1365778072 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.868975640
Short name T1166
Test name
Test status
Simulation time 186188567 ps
CPU time 4.33 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 215984 kb
Host smart-5a5ba8d7-0c25-4154-80bb-13c0439b2786
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868975640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.868975
640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3184466791
Short name T157
Test name
Test status
Simulation time 15298036 ps
CPU time 0.78 seconds
Started Apr 25 12:52:46 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 215888 kb
Host smart-28ee2d13-abb4-45da-a699-82b9e39db4b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184466791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3184466791 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.1960303718
Short name T1184
Test name
Test status
Simulation time 52061945 ps
CPU time 0.82 seconds
Started Apr 25 12:52:37 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 215816 kb
Host smart-d0bba80c-adbc-41cc-98c8-7fad668e577f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960303718 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.1960303718 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.788998442
Short name T1143
Test name
Test status
Simulation time 13999608 ps
CPU time 0.78 seconds
Started Apr 25 12:52:48 PM PDT 24
Finished Apr 25 12:52:51 PM PDT 24
Peak memory 215960 kb
Host smart-786ae92e-99d6-4204-a9a7-43ba38aa3dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788998442 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.788998442 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.3232176041
Short name T1190
Test name
Test status
Simulation time 87165595 ps
CPU time 0.81 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 215944 kb
Host smart-559e3531-1f00-4f71-a8e2-41cc4baa3f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232176041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.3232176041 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1371321484
Short name T1147
Test name
Test status
Simulation time 47220392 ps
CPU time 0.8 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 215856 kb
Host smart-2b7f1f53-9328-40c8-a2de-0622475d4e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371321484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1371321484 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.3673998163
Short name T1228
Test name
Test status
Simulation time 18851406 ps
CPU time 0.8 seconds
Started Apr 25 12:52:35 PM PDT 24
Finished Apr 25 12:52:37 PM PDT 24
Peak memory 215904 kb
Host smart-30234196-cc49-4688-badb-2aa9f1bdb25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673998163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.3673998163 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.857885504
Short name T1116
Test name
Test status
Simulation time 42752316 ps
CPU time 0.79 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 215928 kb
Host smart-018fe040-3bc9-41c0-8b45-62690a7f9e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857885504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.857885504 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.744194475
Short name T1113
Test name
Test status
Simulation time 31354144 ps
CPU time 0.82 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 215940 kb
Host smart-244eddbd-b6e9-47e9-9399-2871c42ac037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744194475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.744194475 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.3408661239
Short name T1150
Test name
Test status
Simulation time 14814574 ps
CPU time 0.78 seconds
Started Apr 25 12:52:42 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 216004 kb
Host smart-458db1d7-acf8-4173-9e18-dce30a72e598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408661239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.3408661239 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.3120805018
Short name T1188
Test name
Test status
Simulation time 38586015 ps
CPU time 0.8 seconds
Started Apr 25 12:52:45 PM PDT 24
Finished Apr 25 12:52:48 PM PDT 24
Peak memory 215920 kb
Host smart-01d8e08b-1bef-4c42-9b65-53f5f7b4ba58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120805018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.3120805018 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.476684883
Short name T1096
Test name
Test status
Simulation time 138730815 ps
CPU time 7.79 seconds
Started Apr 25 12:52:11 PM PDT 24
Finished Apr 25 12:52:22 PM PDT 24
Peak memory 216128 kb
Host smart-b692095b-26ed-4d6e-8da2-204cf704f081
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476684883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.47668488
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.488838757
Short name T1180
Test name
Test status
Simulation time 1461387555 ps
CPU time 21.1 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:53:03 PM PDT 24
Peak memory 216088 kb
Host smart-0c9fc444-5fc9-471b-bd20-6eb4e7685feb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488838757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.48883875
7 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.177311841
Short name T1081
Test name
Test status
Simulation time 77832163 ps
CPU time 0.92 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:22 PM PDT 24
Peak memory 215852 kb
Host smart-d26be1c0-3348-4035-bbda-e38fed2b15c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177311841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.17731184
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2009052018
Short name T1084
Test name
Test status
Simulation time 41935871 ps
CPU time 1.56 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 217592 kb
Host smart-43927b07-b412-4639-8410-b22f77476c65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009052018 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2009052018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.896113342
Short name T152
Test name
Test status
Simulation time 22707680 ps
CPU time 0.94 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:16 PM PDT 24
Peak memory 215976 kb
Host smart-1ca78093-ee13-43e3-a9ad-99b4056361b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896113342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.896113342 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.1508373878
Short name T1092
Test name
Test status
Simulation time 38621966 ps
CPU time 0.76 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:30 PM PDT 24
Peak memory 215828 kb
Host smart-ba3bb880-2649-4b80-b2b9-3b15f481771c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508373878 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.1508373878 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.3572194180
Short name T144
Test name
Test status
Simulation time 50422927 ps
CPU time 1.19 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:16 PM PDT 24
Peak memory 216120 kb
Host smart-693dc1dd-338b-4f13-816f-85d678e221fb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572194180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.3572194180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.1449765426
Short name T1201
Test name
Test status
Simulation time 26270708 ps
CPU time 0.82 seconds
Started Apr 25 12:52:24 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 215848 kb
Host smart-5771ffcc-8b1a-400a-becd-ac6c09043fb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449765426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.1449765426
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1072575530
Short name T1140
Test name
Test status
Simulation time 93324894 ps
CPU time 2.67 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 216136 kb
Host smart-e2b4e30d-7a87-4f89-8517-696cfaf082a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072575530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1072575530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.907903984
Short name T1177
Test name
Test status
Simulation time 236687139 ps
CPU time 1 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 216240 kb
Host smart-e642668c-6715-4a64-be30-a724857a6d4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907903984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_e
rrors.907903984 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.826152056
Short name T1111
Test name
Test status
Simulation time 231491338 ps
CPU time 2 seconds
Started Apr 25 12:52:19 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216204 kb
Host smart-fb7d068e-07c6-43e8-ac2c-e36e2c36e902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826152056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.826152056 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.2220062288
Short name T1220
Test name
Test status
Simulation time 42581387 ps
CPU time 0.81 seconds
Started Apr 25 12:52:46 PM PDT 24
Finished Apr 25 12:52:49 PM PDT 24
Peak memory 215900 kb
Host smart-23026fc1-5989-4605-9c3c-cbabf4d73a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220062288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2220062288 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2985753226
Short name T1146
Test name
Test status
Simulation time 15743842 ps
CPU time 0.87 seconds
Started Apr 25 12:52:36 PM PDT 24
Finished Apr 25 12:52:39 PM PDT 24
Peak memory 215656 kb
Host smart-6fef80ac-3101-4fd3-b7cc-a5fa75acb99b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985753226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2985753226 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.753302661
Short name T1120
Test name
Test status
Simulation time 50372999 ps
CPU time 0.78 seconds
Started Apr 25 12:52:43 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 215928 kb
Host smart-290d6a9c-5b41-4b5e-88fb-ccb36ced8981
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753302661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.753302661 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.550336395
Short name T1202
Test name
Test status
Simulation time 20428432 ps
CPU time 0.83 seconds
Started Apr 25 12:52:47 PM PDT 24
Finished Apr 25 12:52:50 PM PDT 24
Peak memory 215880 kb
Host smart-36f163bd-7d9a-40bf-a5cf-0df0ebe2b474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550336395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.550336395 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1280245184
Short name T1215
Test name
Test status
Simulation time 17003894 ps
CPU time 0.79 seconds
Started Apr 25 12:52:33 PM PDT 24
Finished Apr 25 12:52:35 PM PDT 24
Peak memory 215856 kb
Host smart-a699a1d0-19c8-4f90-b420-127c27d78bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280245184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1280245184 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2126765846
Short name T158
Test name
Test status
Simulation time 24765285 ps
CPU time 0.8 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 215868 kb
Host smart-a244d327-0345-482f-a4f5-6c13ca86cca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126765846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2126765846 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.2779857425
Short name T1240
Test name
Test status
Simulation time 43024826 ps
CPU time 0.81 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 215820 kb
Host smart-430736bc-d7f9-4252-b953-6c5b08767912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779857425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.2779857425 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1605316943
Short name T1129
Test name
Test status
Simulation time 44461119 ps
CPU time 0.82 seconds
Started Apr 25 12:52:36 PM PDT 24
Finished Apr 25 12:52:38 PM PDT 24
Peak memory 215868 kb
Host smart-ad5a7cd9-6b6d-4d5f-b34f-0a2602633306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605316943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1605316943 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.153000775
Short name T1115
Test name
Test status
Simulation time 90028658 ps
CPU time 0.79 seconds
Started Apr 25 12:52:39 PM PDT 24
Finished Apr 25 12:52:43 PM PDT 24
Peak memory 215940 kb
Host smart-801b760a-4d7f-41cc-ae93-069c3a5deec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153000775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.153000775 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.3873875267
Short name T1168
Test name
Test status
Simulation time 43552371 ps
CPU time 0.85 seconds
Started Apr 25 12:52:44 PM PDT 24
Finished Apr 25 12:52:47 PM PDT 24
Peak memory 215964 kb
Host smart-8696011b-0c4b-40c3-8ddb-cc859c553e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873875267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3873875267 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.4091853483
Short name T1144
Test name
Test status
Simulation time 86633825 ps
CPU time 1.68 seconds
Started Apr 25 12:52:24 PM PDT 24
Finished Apr 25 12:52:27 PM PDT 24
Peak memory 220200 kb
Host smart-66d1debf-b53a-4619-8976-4d5bb951907b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091853483 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.4091853483 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.4095383944
Short name T1088
Test name
Test status
Simulation time 50465969 ps
CPU time 1.12 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:30 PM PDT 24
Peak memory 216004 kb
Host smart-21ec5b38-000c-41b8-a8dd-161c6b04f621
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095383944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.4095383944 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.2333691182
Short name T1138
Test name
Test status
Simulation time 54934019 ps
CPU time 0.82 seconds
Started Apr 25 12:52:30 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 215928 kb
Host smart-9a57054a-71a0-43fa-bc31-d964be50a41e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333691182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2333691182 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2711686950
Short name T1137
Test name
Test status
Simulation time 126678417 ps
CPU time 2.17 seconds
Started Apr 25 12:52:18 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216076 kb
Host smart-188bf5d1-7442-4f6d-bb1a-00485d3ec47c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711686950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.2711686950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1928536241
Short name T97
Test name
Test status
Simulation time 96803535 ps
CPU time 1.36 seconds
Started Apr 25 12:52:55 PM PDT 24
Finished Apr 25 12:52:58 PM PDT 24
Peak memory 216388 kb
Host smart-01ed7adb-b843-4549-9029-eee71fb7e177
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928536241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1928536241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.323213505
Short name T1159
Test name
Test status
Simulation time 362007478 ps
CPU time 2.63 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 216112 kb
Host smart-bcf7d8b6-2040-42de-9ab3-19e186b8efe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323213505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_
shadow_reg_errors_with_csr_rw.323213505 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.45115328
Short name T1127
Test name
Test status
Simulation time 629460720 ps
CPU time 3.75 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 216164 kb
Host smart-078c13d2-4366-4daf-8abc-d14a8c4f628e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45115328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.45115328 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.4212278773
Short name T1208
Test name
Test status
Simulation time 140214226 ps
CPU time 2.8 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 216016 kb
Host smart-249be8f2-08fa-4f81-ad05-402ff2726e2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212278773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.42122
78773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3749661637
Short name T1204
Test name
Test status
Simulation time 80799937 ps
CPU time 1.71 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 219600 kb
Host smart-9e879808-f4f3-4c01-89ec-bd85282a0ad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749661637 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3749661637 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.649447327
Short name T153
Test name
Test status
Simulation time 99830409 ps
CPU time 0.98 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:26 PM PDT 24
Peak memory 215828 kb
Host smart-6f8f46ec-d75c-4aca-9a29-f58839ec64eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649447327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.649447327 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.3215582991
Short name T1107
Test name
Test status
Simulation time 15272256 ps
CPU time 0.77 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 215848 kb
Host smart-3a1b641e-1a32-46c1-a461-cfaf05724ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215582991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3215582991 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.1880375822
Short name T1158
Test name
Test status
Simulation time 54352125 ps
CPU time 2.14 seconds
Started Apr 25 12:52:13 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216076 kb
Host smart-282628c3-3213-4363-9330-604f69feaa46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880375822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr
_outstanding.1880375822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.3140103851
Short name T1171
Test name
Test status
Simulation time 26070629 ps
CPU time 0.98 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:17 PM PDT 24
Peak memory 216224 kb
Host smart-68d1343b-7cd8-4a9e-9595-b1f98eb72a35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140103851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_
errors.3140103851 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3813954332
Short name T1183
Test name
Test status
Simulation time 83492989 ps
CPU time 1.51 seconds
Started Apr 25 12:52:14 PM PDT 24
Finished Apr 25 12:52:19 PM PDT 24
Peak memory 216104 kb
Host smart-1945ff7f-5035-429d-b239-8887ffff478a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813954332 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.3813954332 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.2804161576
Short name T1142
Test name
Test status
Simulation time 379468560 ps
CPU time 1.81 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:26 PM PDT 24
Peak memory 216124 kb
Host smart-f5ceb74d-b780-4a6d-a761-b5b779e42bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804161576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.2804161576 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.1524953300
Short name T1152
Test name
Test status
Simulation time 75527243 ps
CPU time 2.39 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 216036 kb
Host smart-1a3b892e-8251-45b4-b2c8-66d3957afe14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524953300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.15249
53300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.2328233839
Short name T1229
Test name
Test status
Simulation time 323028421 ps
CPU time 2.48 seconds
Started Apr 25 12:52:25 PM PDT 24
Finished Apr 25 12:52:29 PM PDT 24
Peak memory 220976 kb
Host smart-f83cf662-7247-493c-b5a3-d8bf8186af87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328233839 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.2328233839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1105276111
Short name T1189
Test name
Test status
Simulation time 74514122 ps
CPU time 0.98 seconds
Started Apr 25 12:52:22 PM PDT 24
Finished Apr 25 12:52:24 PM PDT 24
Peak memory 215900 kb
Host smart-cd2e590c-b0a8-48cc-b895-8a0939655b3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105276111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1105276111 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.1973625627
Short name T124
Test name
Test status
Simulation time 25791906 ps
CPU time 0.8 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 215856 kb
Host smart-1225a2fa-ac4f-46a0-851b-94b00fcda6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973625627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.1973625627 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.2182982631
Short name T1169
Test name
Test status
Simulation time 179180724 ps
CPU time 1.61 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:18 PM PDT 24
Peak memory 216044 kb
Host smart-59e53bb2-dc72-496c-b9c3-4159146b5acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182982631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr
_outstanding.2182982631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.3923661798
Short name T99
Test name
Test status
Simulation time 51435422 ps
CPU time 0.99 seconds
Started Apr 25 12:52:21 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216212 kb
Host smart-d4fc6998-d7cd-4813-a3cc-2b213a84cef9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923661798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.3923661798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.1549299155
Short name T1175
Test name
Test status
Simulation time 58640643 ps
CPU time 1.87 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216396 kb
Host smart-c472da86-3655-45c3-a946-c3ed40db607e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549299155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.1549299155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.213204791
Short name T1234
Test name
Test status
Simulation time 118752036 ps
CPU time 2.81 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:28 PM PDT 24
Peak memory 216192 kb
Host smart-0cfddff4-878b-4168-9a8e-38e19be89e9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213204791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.213204791 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.2331495899
Short name T176
Test name
Test status
Simulation time 740673347 ps
CPU time 4.82 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:23 PM PDT 24
Peak memory 216060 kb
Host smart-84aefb62-b693-4625-8e52-2ebfbf8c106a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331495899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.23314
95899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.1191953750
Short name T1080
Test name
Test status
Simulation time 171452465 ps
CPU time 1.89 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:32 PM PDT 24
Peak memory 220768 kb
Host smart-ad911287-fa8e-4837-b789-2fc1e821cb7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191953750 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.1191953750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.3457598873
Short name T181
Test name
Test status
Simulation time 32361514 ps
CPU time 1.1 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216064 kb
Host smart-199a0329-88e4-4e87-90a3-32e9fcc40b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457598873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3457598873 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.867534045
Short name T1173
Test name
Test status
Simulation time 40705444 ps
CPU time 0.78 seconds
Started Apr 25 12:52:12 PM PDT 24
Finished Apr 25 12:52:16 PM PDT 24
Peak memory 215900 kb
Host smart-cbe2d742-d833-46c3-9112-26dc8c4a0de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867534045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.867534045 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.3039452967
Short name T1091
Test name
Test status
Simulation time 94388342 ps
CPU time 2.55 seconds
Started Apr 25 12:52:40 PM PDT 24
Finished Apr 25 12:52:45 PM PDT 24
Peak memory 216028 kb
Host smart-80ee66e4-97b7-45d2-b714-e5d81ba030e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039452967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.3039452967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.1350055865
Short name T1086
Test name
Test status
Simulation time 76315129 ps
CPU time 0.94 seconds
Started Apr 25 12:52:18 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 215980 kb
Host smart-1719bdc2-26c4-4604-8bb2-e3c9b403b8c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350055865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_
errors.1350055865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3107047640
Short name T1217
Test name
Test status
Simulation time 180562208 ps
CPU time 2.44 seconds
Started Apr 25 12:52:16 PM PDT 24
Finished Apr 25 12:52:21 PM PDT 24
Peak memory 216408 kb
Host smart-bb03cfd3-6b82-4e15-98e8-1f3632e8f98c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107047640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3107047640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.262380098
Short name T1102
Test name
Test status
Simulation time 214776901 ps
CPU time 3.42 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 216208 kb
Host smart-492763fd-af5c-48ab-907f-1dccce166757
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262380098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.262380098 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2853856073
Short name T1195
Test name
Test status
Simulation time 32113731 ps
CPU time 1.56 seconds
Started Apr 25 12:52:27 PM PDT 24
Finished Apr 25 12:52:30 PM PDT 24
Peak memory 220136 kb
Host smart-fe87285a-17f5-4b04-8b6c-01e81c2c8269
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853856073 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2853856073 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.434267424
Short name T155
Test name
Test status
Simulation time 57798262 ps
CPU time 1.14 seconds
Started Apr 25 12:52:28 PM PDT 24
Finished Apr 25 12:52:31 PM PDT 24
Peak memory 216064 kb
Host smart-4daac4f6-9858-4805-9d75-a8ae36d2cf66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434267424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.434267424 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.3944930101
Short name T1126
Test name
Test status
Simulation time 105137830 ps
CPU time 0.89 seconds
Started Apr 25 12:52:23 PM PDT 24
Finished Apr 25 12:52:25 PM PDT 24
Peak memory 215964 kb
Host smart-fa8b418f-e132-42f8-a5d6-3f4eec70c635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944930101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3944930101 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3449003689
Short name T160
Test name
Test status
Simulation time 200866707 ps
CPU time 1.67 seconds
Started Apr 25 12:52:15 PM PDT 24
Finished Apr 25 12:52:20 PM PDT 24
Peak memory 216068 kb
Host smart-929c6aa0-e264-46b3-9bd5-ab09c6f6c046
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449003689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.3449003689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.1917105963
Short name T1239
Test name
Test status
Simulation time 71848124 ps
CPU time 1.89 seconds
Started Apr 25 12:52:29 PM PDT 24
Finished Apr 25 12:52:33 PM PDT 24
Peak memory 217532 kb
Host smart-03d184fb-3c49-489e-869c-15f4d53ff1b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917105963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.1917105963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.3644531712
Short name T1085
Test name
Test status
Simulation time 77146773 ps
CPU time 1.52 seconds
Started Apr 25 12:52:31 PM PDT 24
Finished Apr 25 12:52:34 PM PDT 24
Peak memory 216276 kb
Host smart-9dda8964-04a3-4840-9a86-4d5ad1ce1c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644531712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3644531712 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.607789226
Short name T174
Test name
Test status
Simulation time 884543088 ps
CPU time 5.12 seconds
Started Apr 25 12:52:18 PM PDT 24
Finished Apr 25 12:52:26 PM PDT 24
Peak memory 216160 kb
Host smart-71d773d6-b336-4353-a316-a005feabd3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607789226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.607789
226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_alert_test.4173994663
Short name T706
Test name
Test status
Simulation time 20138559 ps
CPU time 0.96 seconds
Started Apr 25 03:55:28 PM PDT 24
Finished Apr 25 03:55:30 PM PDT 24
Peak memory 217852 kb
Host smart-349e5845-33a6-4edd-9574-ca50727ef494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173994663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.4173994663 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/default/0.kmac_app.683185854
Short name T596
Test name
Test status
Simulation time 51570587818 ps
CPU time 280.52 seconds
Started Apr 25 03:55:14 PM PDT 24
Finished Apr 25 03:59:55 PM PDT 24
Peak memory 245328 kb
Host smart-fdaf774d-d11c-4073-88b2-6c951774853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683185854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.683185854 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.514125158
Short name T627
Test name
Test status
Simulation time 27695991918 ps
CPU time 391.03 seconds
Started Apr 25 03:55:13 PM PDT 24
Finished Apr 25 04:01:44 PM PDT 24
Peak memory 250236 kb
Host smart-9f91ad4e-f42c-4c63-8168-f828029ad1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514125158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.514125158 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.4290476565
Short name T356
Test name
Test status
Simulation time 34507738956 ps
CPU time 943.18 seconds
Started Apr 25 03:55:12 PM PDT 24
Finished Apr 25 04:10:56 PM PDT 24
Peak memory 235144 kb
Host smart-118dd67e-85f5-4700-9eda-149edcc8fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290476565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.4290476565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.2455775892
Short name T113
Test name
Test status
Simulation time 132088338 ps
CPU time 2.49 seconds
Started Apr 25 03:55:21 PM PDT 24
Finished Apr 25 03:55:24 PM PDT 24
Peak memory 226076 kb
Host smart-34dcdef1-02ba-46cc-81ec-9f6ddd8c420a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2455775892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2455775892 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1430785192
Short name T534
Test name
Test status
Simulation time 22357808 ps
CPU time 1 seconds
Started Apr 25 03:55:23 PM PDT 24
Finished Apr 25 03:55:25 PM PDT 24
Peak memory 220080 kb
Host smart-61c1be9f-2b22-46bf-ad41-5f8446ade4ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1430785192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1430785192 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.3136907548
Short name T355
Test name
Test status
Simulation time 3826070749 ps
CPU time 46.95 seconds
Started Apr 25 03:55:48 PM PDT 24
Finished Apr 25 03:56:36 PM PDT 24
Peak memory 219296 kb
Host smart-d69f6e03-a123-4df7-bc00-a090d7764201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136907548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3136907548 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.4228320667
Short name T4
Test name
Test status
Simulation time 114592431500 ps
CPU time 352.18 seconds
Started Apr 25 03:55:29 PM PDT 24
Finished Apr 25 04:01:22 PM PDT 24
Peak memory 246972 kb
Host smart-43e34b91-16eb-4646-ab9c-1758340e3abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228320667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4228320667 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.3466854333
Short name T936
Test name
Test status
Simulation time 108941126 ps
CPU time 3.32 seconds
Started Apr 25 03:55:22 PM PDT 24
Finished Apr 25 03:55:26 PM PDT 24
Peak memory 226288 kb
Host smart-8b0a7fc8-14ae-405a-9aba-3ce47c2437dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466854333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3466854333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.2309330164
Short name T944
Test name
Test status
Simulation time 1235358668 ps
CPU time 7.58 seconds
Started Apr 25 03:55:23 PM PDT 24
Finished Apr 25 03:55:31 PM PDT 24
Peak memory 218100 kb
Host smart-cae3ed42-3a65-409c-8b32-0ec41a733ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309330164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.2309330164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.1288962311
Short name T924
Test name
Test status
Simulation time 2195634100 ps
CPU time 255.61 seconds
Started Apr 25 03:55:13 PM PDT 24
Finished Apr 25 03:59:30 PM PDT 24
Peak memory 240936 kb
Host smart-547f2ef0-1bab-4a78-ae6d-957f4e08a800
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288962311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an
d_output.1288962311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.1896872046
Short name T19
Test name
Test status
Simulation time 28699958781 ps
CPU time 54.73 seconds
Started Apr 25 03:55:28 PM PDT 24
Finished Apr 25 03:56:23 PM PDT 24
Peak memory 264988 kb
Host smart-d1370cff-be2a-43a1-82a8-80bcb0da6d27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896872046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.1896872046 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/0.kmac_sideload.110580966
Short name T948
Test name
Test status
Simulation time 41584570273 ps
CPU time 241.2 seconds
Started Apr 25 03:55:10 PM PDT 24
Finished Apr 25 03:59:12 PM PDT 24
Peak memory 240968 kb
Host smart-af99eacd-0109-4203-86ff-24812dd237fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110580966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.110580966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2210712116
Short name T888
Test name
Test status
Simulation time 3210391482 ps
CPU time 60.23 seconds
Started Apr 25 03:55:09 PM PDT 24
Finished Apr 25 03:56:10 PM PDT 24
Peak memory 226292 kb
Host smart-ce630218-5e4c-499e-96ef-823d5436c29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210712116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2210712116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.1667706377
Short name T722
Test name
Test status
Simulation time 12700979160 ps
CPU time 338.94 seconds
Started Apr 25 03:55:26 PM PDT 24
Finished Apr 25 04:01:06 PM PDT 24
Peak memory 279368 kb
Host smart-63af8e68-2d7d-4761-bfa8-15f84a64449d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1667706377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.1667706377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_stress_all_with_rand_reset.2839406818
Short name T87
Test name
Test status
Simulation time 179171209481 ps
CPU time 1915.23 seconds
Started Apr 25 03:55:31 PM PDT 24
Finished Apr 25 04:27:27 PM PDT 24
Peak memory 377508 kb
Host smart-79896dc5-3709-40d4-8118-81ee6c7746c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839406818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.2839406818 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.2119089055
Short name T974
Test name
Test status
Simulation time 211373251 ps
CPU time 6.69 seconds
Started Apr 25 03:55:15 PM PDT 24
Finished Apr 25 03:55:23 PM PDT 24
Peak memory 218156 kb
Host smart-d8e1ec15-abe0-4488-8356-30fc794fea62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119089055 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.2119089055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.1814543780
Short name T699
Test name
Test status
Simulation time 4062823195 ps
CPU time 7.25 seconds
Started Apr 25 03:55:21 PM PDT 24
Finished Apr 25 03:55:28 PM PDT 24
Peak memory 218340 kb
Host smart-31551fa2-2f58-440f-b195-8f1af6b87821
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814543780 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.kmac_test_vectors_kmac_xof.1814543780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.260962446
Short name T1037
Test name
Test status
Simulation time 394043829189 ps
CPU time 2503.17 seconds
Started Apr 25 03:55:09 PM PDT 24
Finished Apr 25 04:36:53 PM PDT 24
Peak memory 398724 kb
Host smart-be72c72a-dfff-404c-ae93-fd84122ee264
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=260962446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.260962446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2753996620
Short name T293
Test name
Test status
Simulation time 308009509031 ps
CPU time 2031.1 seconds
Started Apr 25 03:55:18 PM PDT 24
Finished Apr 25 04:29:10 PM PDT 24
Peak memory 385064 kb
Host smart-a70b1714-0ade-4545-b55c-c7693d0ea129
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2753996620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2753996620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.848151068
Short name T271
Test name
Test status
Simulation time 41733865948 ps
CPU time 1517.77 seconds
Started Apr 25 03:55:09 PM PDT 24
Finished Apr 25 04:20:27 PM PDT 24
Peak memory 338744 kb
Host smart-a7f78e0d-974c-4983-a388-9dfc3bce8f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=848151068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.848151068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.3813452273
Short name T930
Test name
Test status
Simulation time 49021049790 ps
CPU time 1371.68 seconds
Started Apr 25 03:55:09 PM PDT 24
Finished Apr 25 04:18:02 PM PDT 24
Peak memory 297428 kb
Host smart-ce8be9c2-09a1-456b-a0f5-46bc544608b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3813452273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3813452273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.110099226
Short name T689
Test name
Test status
Simulation time 1127358627877 ps
CPU time 5743.85 seconds
Started Apr 25 03:55:14 PM PDT 24
Finished Apr 25 05:30:59 PM PDT 24
Peak memory 654108 kb
Host smart-4b034218-072f-4ae6-9f7c-5e3962ae4f4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=110099226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.110099226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.3149636517
Short name T537
Test name
Test status
Simulation time 1931783006161 ps
CPU time 5387.44 seconds
Started Apr 25 03:55:13 PM PDT 24
Finished Apr 25 05:25:02 PM PDT 24
Peak memory 583112 kb
Host smart-30cb3225-7070-44d8-9dea-b73f1bc62a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3149636517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.3149636517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.4213558614
Short name T552
Test name
Test status
Simulation time 68576637 ps
CPU time 0.82 seconds
Started Apr 25 03:55:38 PM PDT 24
Finished Apr 25 03:55:40 PM PDT 24
Peak memory 217876 kb
Host smart-1cd4fd1b-f48f-40cc-940e-361c164959ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213558614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.4213558614 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.1976108069
Short name T376
Test name
Test status
Simulation time 753573568 ps
CPU time 11.64 seconds
Started Apr 25 03:55:30 PM PDT 24
Finished Apr 25 03:55:43 PM PDT 24
Peak memory 220104 kb
Host smart-6a97ea93-e55c-429b-942a-ce3024b0223d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976108069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.1976108069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.3825987520
Short name T229
Test name
Test status
Simulation time 28507458157 ps
CPU time 225.33 seconds
Started Apr 25 03:55:30 PM PDT 24
Finished Apr 25 03:59:16 PM PDT 24
Peak memory 244888 kb
Host smart-28696594-29c2-4726-aeda-d69a8f5a9fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825987520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.3825987520 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1459738750
Short name T415
Test name
Test status
Simulation time 15989842952 ps
CPU time 1379.84 seconds
Started Apr 25 03:55:25 PM PDT 24
Finished Apr 25 04:18:26 PM PDT 24
Peak memory 238028 kb
Host smart-844fb4ae-79dd-4a8d-ac26-449df712432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459738750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1459738750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.3204849336
Short name T928
Test name
Test status
Simulation time 71885987 ps
CPU time 1.38 seconds
Started Apr 25 03:55:32 PM PDT 24
Finished Apr 25 03:55:34 PM PDT 24
Peak memory 222712 kb
Host smart-081d0d1d-03b0-47e7-ad53-9e7a00975231
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3204849336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.3204849336 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1504939791
Short name T403
Test name
Test status
Simulation time 5960364254 ps
CPU time 36.08 seconds
Started Apr 25 03:55:35 PM PDT 24
Finished Apr 25 03:56:12 PM PDT 24
Peak memory 234296 kb
Host smart-46640d48-6561-441d-a608-c5ae0b34e7dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504939791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1504939791 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.3469975786
Short name T257
Test name
Test status
Simulation time 8296282316 ps
CPU time 18.49 seconds
Started Apr 25 03:55:48 PM PDT 24
Finished Apr 25 03:56:08 PM PDT 24
Peak memory 218288 kb
Host smart-7a70b5a0-fbef-40da-b261-7da08a8789dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469975786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.3469975786 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.276959483
Short name T686
Test name
Test status
Simulation time 12997756659 ps
CPU time 187.01 seconds
Started Apr 25 03:55:31 PM PDT 24
Finished Apr 25 03:58:39 PM PDT 24
Peak memory 239912 kb
Host smart-10b29f52-9ffb-48a1-82de-907595221967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276959483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.276959483 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.882863415
Short name T828
Test name
Test status
Simulation time 71435349228 ps
CPU time 401.28 seconds
Started Apr 25 03:55:32 PM PDT 24
Finished Apr 25 04:02:14 PM PDT 24
Peak memory 267336 kb
Host smart-487a2488-bdb5-4270-8803-48f025ab453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882863415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.882863415 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1736032146
Short name T704
Test name
Test status
Simulation time 425214294 ps
CPU time 1.34 seconds
Started Apr 25 03:55:34 PM PDT 24
Finished Apr 25 03:55:36 PM PDT 24
Peak memory 218040 kb
Host smart-0d811d05-9a64-49ad-a3ee-cbbcdd7de3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736032146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1736032146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.282296387
Short name T26
Test name
Test status
Simulation time 50301608 ps
CPU time 1.46 seconds
Started Apr 25 03:55:55 PM PDT 24
Finished Apr 25 03:55:57 PM PDT 24
Peak memory 218204 kb
Host smart-f458b4f1-cfda-4fa6-8cf4-f94e91eef2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282296387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.282296387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.2234931082
Short name T937
Test name
Test status
Simulation time 67981543154 ps
CPU time 1724.15 seconds
Started Apr 25 03:55:25 PM PDT 24
Finished Apr 25 04:24:11 PM PDT 24
Peak memory 348504 kb
Host smart-52972d11-64f9-498f-9df4-03b77f0ced29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234931082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.2234931082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.3602637909
Short name T927
Test name
Test status
Simulation time 1990001218 ps
CPU time 31.17 seconds
Started Apr 25 03:55:34 PM PDT 24
Finished Apr 25 03:56:06 PM PDT 24
Peak memory 226616 kb
Host smart-d2400541-27f6-40c9-b0a8-aedc37372dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602637909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3602637909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.4030595656
Short name T110
Test name
Test status
Simulation time 8939520671 ps
CPU time 91.8 seconds
Started Apr 25 03:55:42 PM PDT 24
Finished Apr 25 03:57:14 PM PDT 24
Peak memory 270652 kb
Host smart-95854822-53c2-499c-843e-60fb1defc6e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030595656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.4030595656 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/default/1.kmac_sideload.2902462455
Short name T629
Test name
Test status
Simulation time 54124150380 ps
CPU time 362.08 seconds
Started Apr 25 03:55:26 PM PDT 24
Finished Apr 25 04:01:28 PM PDT 24
Peak memory 248184 kb
Host smart-ba6a9da1-4738-4969-b799-45b29492dc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902462455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.2902462455 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.1345039859
Short name T185
Test name
Test status
Simulation time 40744944231 ps
CPU time 98.53 seconds
Started Apr 25 03:55:27 PM PDT 24
Finished Apr 25 03:57:06 PM PDT 24
Peak memory 222168 kb
Host smart-b5648ede-5737-4e56-9a64-9cd70b3543ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345039859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1345039859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2648783174
Short name T514
Test name
Test status
Simulation time 40351094645 ps
CPU time 1225.66 seconds
Started Apr 25 03:55:36 PM PDT 24
Finished Apr 25 04:16:02 PM PDT 24
Peak memory 370904 kb
Host smart-da6f2c60-0324-4509-be39-4d6ebeb1d383
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2648783174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2648783174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.2074128107
Short name T247
Test name
Test status
Simulation time 85007896 ps
CPU time 5.41 seconds
Started Apr 25 03:55:30 PM PDT 24
Finished Apr 25 03:55:36 PM PDT 24
Peak memory 218200 kb
Host smart-ae9e164a-4db4-458c-a709-4cd932b69786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074128107 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.2074128107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2827520954
Short name T570
Test name
Test status
Simulation time 1063401071 ps
CPU time 6.27 seconds
Started Apr 25 03:55:32 PM PDT 24
Finished Apr 25 03:55:39 PM PDT 24
Peak memory 218160 kb
Host smart-65c91265-31a5-494a-b93e-e333c579b482
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827520954 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2827520954 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.1932579946
Short name T284
Test name
Test status
Simulation time 160047258984 ps
CPU time 2439.97 seconds
Started Apr 25 03:55:27 PM PDT 24
Finished Apr 25 04:36:08 PM PDT 24
Peak memory 398784 kb
Host smart-07da545b-c9c2-4913-b9b0-026f3ad84e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1932579946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1932579946 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.1851314975
Short name T781
Test name
Test status
Simulation time 254550020904 ps
CPU time 2227.02 seconds
Started Apr 25 03:55:26 PM PDT 24
Finished Apr 25 04:32:34 PM PDT 24
Peak memory 384492 kb
Host smart-4205c161-b720-47eb-8b51-cf4f5b79a1de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1851314975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.1851314975 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.1836747315
Short name T411
Test name
Test status
Simulation time 85195356217 ps
CPU time 1929.52 seconds
Started Apr 25 03:55:28 PM PDT 24
Finished Apr 25 04:27:38 PM PDT 24
Peak memory 344360 kb
Host smart-218e9e21-da08-4fdc-ab5b-92e9ab00b750
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1836747315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.1836747315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.1918350055
Short name T851
Test name
Test status
Simulation time 49727383141 ps
CPU time 1326.42 seconds
Started Apr 25 03:55:24 PM PDT 24
Finished Apr 25 04:17:31 PM PDT 24
Peak memory 292356 kb
Host smart-288351e1-db50-405d-84bf-1dce825a7fc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1918350055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1918350055 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1007510688
Short name T742
Test name
Test status
Simulation time 63777568898 ps
CPU time 4722.58 seconds
Started Apr 25 03:55:27 PM PDT 24
Finished Apr 25 05:14:11 PM PDT 24
Peak memory 652336 kb
Host smart-20a53691-e42a-431e-a6c2-a761c6583dca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1007510688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1007510688 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.3847471919
Short name T621
Test name
Test status
Simulation time 585075783261 ps
CPU time 4472.01 seconds
Started Apr 25 03:55:33 PM PDT 24
Finished Apr 25 05:10:06 PM PDT 24
Peak memory 562772 kb
Host smart-182f095a-3f8d-499d-a2d0-904c151e2f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3847471919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.3847471919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.3142899006
Short name T1072
Test name
Test status
Simulation time 25288636 ps
CPU time 0.85 seconds
Started Apr 25 03:59:51 PM PDT 24
Finished Apr 25 03:59:52 PM PDT 24
Peak memory 217892 kb
Host smart-ffa5eb6f-ba13-491b-9ebc-eabf2a66046e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142899006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.3142899006 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.3261884137
Short name T862
Test name
Test status
Simulation time 31279589096 ps
CPU time 289.15 seconds
Started Apr 25 03:59:45 PM PDT 24
Finished Apr 25 04:04:35 PM PDT 24
Peak memory 245864 kb
Host smart-61cd171c-9730-4056-a720-07760a22e4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261884137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.3261884137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.1916863464
Short name T1003
Test name
Test status
Simulation time 42684603092 ps
CPU time 718.68 seconds
Started Apr 25 03:59:37 PM PDT 24
Finished Apr 25 04:11:36 PM PDT 24
Peak memory 234592 kb
Host smart-46ee62b0-34e2-498e-ab4e-53ef99362bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916863464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1916863464 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1854797907
Short name T739
Test name
Test status
Simulation time 144025943 ps
CPU time 0.97 seconds
Started Apr 25 03:59:44 PM PDT 24
Finished Apr 25 03:59:46 PM PDT 24
Peak memory 222408 kb
Host smart-db99cf21-bc42-4c47-b0f5-3dc587291662
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854797907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1854797907 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.2456564306
Short name T236
Test name
Test status
Simulation time 669381466 ps
CPU time 19.89 seconds
Started Apr 25 03:59:45 PM PDT 24
Finished Apr 25 04:00:06 PM PDT 24
Peak memory 226152 kb
Host smart-fc09df6e-303f-4e9f-8b5f-ca62f395f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456564306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2456564306 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.1530021567
Short name T914
Test name
Test status
Simulation time 45476737057 ps
CPU time 355.36 seconds
Started Apr 25 03:59:47 PM PDT 24
Finished Apr 25 04:05:43 PM PDT 24
Peak memory 256700 kb
Host smart-610e6df9-0cfd-4e18-80ac-91dd69461f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530021567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.1530021567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.1581854470
Short name T822
Test name
Test status
Simulation time 2505693841 ps
CPU time 3.66 seconds
Started Apr 25 03:59:45 PM PDT 24
Finished Apr 25 03:59:49 PM PDT 24
Peak memory 218196 kb
Host smart-cabc96a5-b6e1-4ab2-82ea-e0d3c24cf9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581854470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.1581854470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.4082597170
Short name T33
Test name
Test status
Simulation time 26869822 ps
CPU time 1.22 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:00:02 PM PDT 24
Peak memory 218192 kb
Host smart-feb4cd2d-0999-4afb-bf83-233b06d319e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082597170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.4082597170 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.2335397378
Short name T412
Test name
Test status
Simulation time 11352604030 ps
CPU time 674.54 seconds
Started Apr 25 03:59:38 PM PDT 24
Finished Apr 25 04:10:54 PM PDT 24
Peak memory 276040 kb
Host smart-aabaed44-f965-41b9-9743-7fd92d459b86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335397378 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_a
nd_output.2335397378 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.3405415293
Short name T681
Test name
Test status
Simulation time 3783997700 ps
CPU time 195.53 seconds
Started Apr 25 03:59:36 PM PDT 24
Finished Apr 25 04:02:52 PM PDT 24
Peak memory 237004 kb
Host smart-8b582535-9d7f-46eb-8bf4-e26639b9bd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405415293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.3405415293 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.4274947543
Short name T797
Test name
Test status
Simulation time 2046728828 ps
CPU time 33.79 seconds
Started Apr 25 03:59:31 PM PDT 24
Finished Apr 25 04:00:05 PM PDT 24
Peak memory 226208 kb
Host smart-074f49d5-1152-4938-b6ed-622f4f79a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274947543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.4274947543 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.3672651904
Short name T618
Test name
Test status
Simulation time 72616412591 ps
CPU time 520.3 seconds
Started Apr 25 03:59:57 PM PDT 24
Finished Apr 25 04:08:38 PM PDT 24
Peak memory 274652 kb
Host smart-fafd73cc-15d2-45c5-91d5-fbf13af863b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3672651904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.3672651904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.2900330295
Short name T258
Test name
Test status
Simulation time 173657817 ps
CPU time 5.97 seconds
Started Apr 25 03:59:40 PM PDT 24
Finished Apr 25 03:59:47 PM PDT 24
Peak memory 218204 kb
Host smart-429255f5-8038-4ed2-8594-96b22484fb96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900330295 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.2900330295 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.2178714106
Short name T353
Test name
Test status
Simulation time 115907085 ps
CPU time 6.27 seconds
Started Apr 25 03:59:40 PM PDT 24
Finished Apr 25 03:59:47 PM PDT 24
Peak memory 218220 kb
Host smart-809c04eb-3057-41c0-8047-dc9ff92f4671
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178714106 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.2178714106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.2564782007
Short name T492
Test name
Test status
Simulation time 21254088364 ps
CPU time 2011.93 seconds
Started Apr 25 03:59:34 PM PDT 24
Finished Apr 25 04:33:07 PM PDT 24
Peak memory 396168 kb
Host smart-85d1198c-9db1-4b12-b613-bdbe7032376b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2564782007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.2564782007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.1183001376
Short name T393
Test name
Test status
Simulation time 472544412049 ps
CPU time 2087.57 seconds
Started Apr 25 03:59:35 PM PDT 24
Finished Apr 25 04:34:24 PM PDT 24
Peak memory 383560 kb
Host smart-f8a7e886-c500-4487-9cbb-aa660cd18227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1183001376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1183001376 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.36173117
Short name T773
Test name
Test status
Simulation time 89694322021 ps
CPU time 1550.05 seconds
Started Apr 25 03:59:44 PM PDT 24
Finished Apr 25 04:25:35 PM PDT 24
Peak memory 335768 kb
Host smart-16b7ad01-7121-41e1-a131-12b14aacb194
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=36173117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.36173117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.1376575034
Short name T919
Test name
Test status
Simulation time 205453098117 ps
CPU time 1479.45 seconds
Started Apr 25 03:59:35 PM PDT 24
Finished Apr 25 04:24:15 PM PDT 24
Peak memory 301104 kb
Host smart-ad40f15e-3439-40c0-b1d4-7bd04750f915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1376575034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.1376575034 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.2725653233
Short name T624
Test name
Test status
Simulation time 1019844833884 ps
CPU time 5962.48 seconds
Started Apr 25 03:59:35 PM PDT 24
Finished Apr 25 05:38:59 PM PDT 24
Peak memory 640252 kb
Host smart-66a5bc0d-6e01-4694-9706-15612f4f3511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2725653233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2725653233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.3680818054
Short name T649
Test name
Test status
Simulation time 181290480558 ps
CPU time 4597.24 seconds
Started Apr 25 03:59:39 PM PDT 24
Finished Apr 25 05:16:18 PM PDT 24
Peak memory 577580 kb
Host smart-bae35fe3-1456-47e3-9646-26916331fca0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3680818054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.3680818054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.2198476746
Short name T760
Test name
Test status
Simulation time 43360529 ps
CPU time 0.76 seconds
Started Apr 25 04:00:18 PM PDT 24
Finished Apr 25 04:00:19 PM PDT 24
Peak memory 217880 kb
Host smart-21c5ec55-1ebf-4508-88b4-90cdd6a6deec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198476746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2198476746 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.3766473337
Short name T262
Test name
Test status
Simulation time 24790084312 ps
CPU time 329.8 seconds
Started Apr 25 04:00:06 PM PDT 24
Finished Apr 25 04:05:36 PM PDT 24
Peak memory 245940 kb
Host smart-8f5c6801-b94f-4efa-8aed-913e725d59f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766473337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3766473337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.3305848214
Short name T55
Test name
Test status
Simulation time 27740365659 ps
CPU time 239.14 seconds
Started Apr 25 03:59:55 PM PDT 24
Finished Apr 25 04:03:55 PM PDT 24
Peak memory 230556 kb
Host smart-65408377-f965-406d-b431-dc2471639b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305848214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.3305848214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.4289867873
Short name T814
Test name
Test status
Simulation time 220808287 ps
CPU time 14.55 seconds
Started Apr 25 04:00:12 PM PDT 24
Finished Apr 25 04:00:27 PM PDT 24
Peak memory 234376 kb
Host smart-e1d6a062-c9b1-49c6-8674-46350f0150fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4289867873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.4289867873 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.2961811538
Short name T384
Test name
Test status
Simulation time 160432488 ps
CPU time 1.29 seconds
Started Apr 25 04:00:11 PM PDT 24
Finished Apr 25 04:00:13 PM PDT 24
Peak memory 221768 kb
Host smart-3a62eb15-e841-4c8d-adce-012d723599e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2961811538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2961811538 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3929997690
Short name T677
Test name
Test status
Simulation time 14442454608 ps
CPU time 398.33 seconds
Started Apr 25 04:00:17 PM PDT 24
Finished Apr 25 04:06:56 PM PDT 24
Peak memory 252876 kb
Host smart-4fa6e214-ebc1-4352-a1a2-8da58fe21018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929997690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3929997690 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1503359908
Short name T926
Test name
Test status
Simulation time 6461963661 ps
CPU time 221.95 seconds
Started Apr 25 04:00:05 PM PDT 24
Finished Apr 25 04:03:47 PM PDT 24
Peak memory 251760 kb
Host smart-2d0b9fdd-9a68-4b74-96f3-d9e3c3ba38e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503359908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1503359908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.1206051286
Short name T666
Test name
Test status
Simulation time 653115063 ps
CPU time 4.47 seconds
Started Apr 25 04:00:10 PM PDT 24
Finished Apr 25 04:00:15 PM PDT 24
Peak memory 218100 kb
Host smart-75e6b11a-8ce4-4c9a-82d4-6bfff827ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206051286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1206051286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.1138176206
Short name T808
Test name
Test status
Simulation time 79387891 ps
CPU time 1.48 seconds
Started Apr 25 04:00:16 PM PDT 24
Finished Apr 25 04:00:18 PM PDT 24
Peak memory 219052 kb
Host smart-86447c2b-5f85-4a5a-853a-086170c7d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138176206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.1138176206 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.3293933435
Short name T1002
Test name
Test status
Simulation time 7376626299 ps
CPU time 795.81 seconds
Started Apr 25 03:59:56 PM PDT 24
Finished Apr 25 04:13:12 PM PDT 24
Peak memory 288452 kb
Host smart-7af431db-da87-4361-80f2-6bb595602e61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293933435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.3293933435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.2147765545
Short name T1065
Test name
Test status
Simulation time 13329220992 ps
CPU time 308.22 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:05:09 PM PDT 24
Peak memory 249160 kb
Host smart-7ec65935-f919-47cf-8c5a-1ff634521280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147765545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2147765545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.1690484016
Short name T357
Test name
Test status
Simulation time 760550878 ps
CPU time 20.22 seconds
Started Apr 25 03:59:57 PM PDT 24
Finished Apr 25 04:00:18 PM PDT 24
Peak memory 222724 kb
Host smart-835f3542-b6a1-4a7a-82e3-8e9fdfec2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690484016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1690484016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.4284628311
Short name T476
Test name
Test status
Simulation time 3275158229 ps
CPU time 307.98 seconds
Started Apr 25 04:00:17 PM PDT 24
Finished Apr 25 04:05:26 PM PDT 24
Peak memory 231108 kb
Host smart-c2027017-6baa-4671-8afb-584d32bd5704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4284628311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.4284628311 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3839687059
Short name T732
Test name
Test status
Simulation time 572786181 ps
CPU time 6.48 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:00:08 PM PDT 24
Peak memory 218228 kb
Host smart-5eedd913-cf65-4664-98ba-dc3f7411aea9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839687059 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3839687059 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.4236107471
Short name T602
Test name
Test status
Simulation time 263167790 ps
CPU time 6.77 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:00:07 PM PDT 24
Peak memory 218272 kb
Host smart-f143e065-c725-491e-bdcc-e7697143b94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236107471 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.4236107471 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.99766844
Short name T860
Test name
Test status
Simulation time 102212483731 ps
CPU time 2399.49 seconds
Started Apr 25 03:59:57 PM PDT 24
Finished Apr 25 04:39:57 PM PDT 24
Peak memory 398704 kb
Host smart-100811cf-d889-4b48-9a63-75868bc410c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=99766844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.99766844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1419034735
Short name T659
Test name
Test status
Simulation time 39925947528 ps
CPU time 2075.31 seconds
Started Apr 25 03:59:54 PM PDT 24
Finished Apr 25 04:34:31 PM PDT 24
Peak memory 384848 kb
Host smart-42cdba17-7b85-4d1f-aa01-0f365de2d4f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1419034735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1419034735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.1414939123
Short name T611
Test name
Test status
Simulation time 61260794411 ps
CPU time 1800.74 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:30:01 PM PDT 24
Peak memory 344736 kb
Host smart-1ca84e5a-2598-445d-aed6-9cae3629af9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1414939123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.1414939123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.3878128855
Short name T504
Test name
Test status
Simulation time 81316508264 ps
CPU time 1216.01 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 04:20:17 PM PDT 24
Peak memory 298888 kb
Host smart-d032454c-53b9-4c10-9568-27c98d5a3b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3878128855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3878128855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.4091808290
Short name T628
Test name
Test status
Simulation time 184229989408 ps
CPU time 5266.82 seconds
Started Apr 25 04:00:00 PM PDT 24
Finished Apr 25 05:27:48 PM PDT 24
Peak memory 668132 kb
Host smart-e0d3499d-045b-4831-b1f2-872e1460672f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4091808290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.4091808290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.2816894751
Short name T605
Test name
Test status
Simulation time 586777479189 ps
CPU time 4581.55 seconds
Started Apr 25 04:00:02 PM PDT 24
Finished Apr 25 05:16:24 PM PDT 24
Peak memory 553904 kb
Host smart-8c2ad36f-8c5d-47a8-a7f8-c92f43543675
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2816894751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2816894751 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.1924396032
Short name T585
Test name
Test status
Simulation time 45263826 ps
CPU time 0.83 seconds
Started Apr 25 04:00:35 PM PDT 24
Finished Apr 25 04:00:36 PM PDT 24
Peak memory 217892 kb
Host smart-ce604fc0-df58-4b39-b0ce-98d3ba5db2a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924396032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.1924396032 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.3264744807
Short name T48
Test name
Test status
Simulation time 8167043291 ps
CPU time 316.93 seconds
Started Apr 25 04:00:27 PM PDT 24
Finished Apr 25 04:05:44 PM PDT 24
Peak memory 250176 kb
Host smart-ab0c90cb-e130-49fb-8878-4dcc31c8b535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264744807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.3264744807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.3365433870
Short name T612
Test name
Test status
Simulation time 47396397405 ps
CPU time 1345.01 seconds
Started Apr 25 04:00:15 PM PDT 24
Finished Apr 25 04:22:41 PM PDT 24
Peak memory 237924 kb
Host smart-90b8d7ba-5387-4875-ac96-6142d4916c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365433870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.3365433870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3143611475
Short name T459
Test name
Test status
Simulation time 460311349 ps
CPU time 7.64 seconds
Started Apr 25 04:00:25 PM PDT 24
Finished Apr 25 04:00:33 PM PDT 24
Peak memory 234352 kb
Host smart-f4295295-0fb8-4258-a83f-8d4a8d0e63b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3143611475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3143611475 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.1623154286
Short name T422
Test name
Test status
Simulation time 16543677 ps
CPU time 0.89 seconds
Started Apr 25 04:00:27 PM PDT 24
Finished Apr 25 04:00:29 PM PDT 24
Peak memory 220168 kb
Host smart-9d978776-a73a-4054-ba89-0828e9e326bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1623154286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.1623154286 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.3456765725
Short name T266
Test name
Test status
Simulation time 1967021970 ps
CPU time 90.11 seconds
Started Apr 25 04:00:27 PM PDT 24
Finished Apr 25 04:01:58 PM PDT 24
Peak memory 230804 kb
Host smart-447fc0dd-5346-420d-81ac-51ba9e72f93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456765725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3456765725 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.2010736757
Short name T544
Test name
Test status
Simulation time 189814534341 ps
CPU time 634.19 seconds
Started Apr 25 04:00:28 PM PDT 24
Finished Apr 25 04:11:02 PM PDT 24
Peak memory 267336 kb
Host smart-e7d7b30e-5e3f-449f-be9e-447ce94b1478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010736757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2010736757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.214512843
Short name T1023
Test name
Test status
Simulation time 394978241 ps
CPU time 1.95 seconds
Started Apr 25 04:00:24 PM PDT 24
Finished Apr 25 04:00:27 PM PDT 24
Peak memory 218068 kb
Host smart-f4f99263-66c9-496d-9555-c0c11d757f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214512843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.214512843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.3227101872
Short name T586
Test name
Test status
Simulation time 105824633 ps
CPU time 1.2 seconds
Started Apr 25 04:00:30 PM PDT 24
Finished Apr 25 04:00:32 PM PDT 24
Peak memory 218188 kb
Host smart-57c302e8-d603-494a-8111-a9383ec5d0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227101872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.3227101872 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.4076213347
Short name T314
Test name
Test status
Simulation time 88593471641 ps
CPU time 1591.73 seconds
Started Apr 25 04:00:16 PM PDT 24
Finished Apr 25 04:26:48 PM PDT 24
Peak memory 338336 kb
Host smart-3ec4a999-3ee4-4035-b066-073f975d4b7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076213347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a
nd_output.4076213347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_smoke.229505503
Short name T946
Test name
Test status
Simulation time 2277573555 ps
CPU time 59.02 seconds
Started Apr 25 04:00:15 PM PDT 24
Finished Apr 25 04:01:15 PM PDT 24
Peak memory 226408 kb
Host smart-27344709-97b7-4482-9950-ed51ac94b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229505503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.229505503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.22476667
Short name T45
Test name
Test status
Simulation time 48974351689 ps
CPU time 218.37 seconds
Started Apr 25 04:00:30 PM PDT 24
Finished Apr 25 04:04:09 PM PDT 24
Peak memory 259180 kb
Host smart-4e8b7a6a-e5ac-48eb-b970-ca5ce2628847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=22476667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.22476667 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.1973621630
Short name T652
Test name
Test status
Simulation time 146736003 ps
CPU time 5.98 seconds
Started Apr 25 04:00:27 PM PDT 24
Finished Apr 25 04:00:34 PM PDT 24
Peak memory 218200 kb
Host smart-d4d0467c-31aa-44b5-b36a-41deb3721c23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973621630 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.1973621630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1749497844
Short name T721
Test name
Test status
Simulation time 106904287 ps
CPU time 5.9 seconds
Started Apr 25 04:00:27 PM PDT 24
Finished Apr 25 04:00:33 PM PDT 24
Peak memory 219172 kb
Host smart-6b2b5eaa-22ad-4bfc-b12d-0bc2634c3002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749497844 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1749497844 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1388974584
Short name T758
Test name
Test status
Simulation time 750378076714 ps
CPU time 2157.71 seconds
Started Apr 25 04:00:18 PM PDT 24
Finished Apr 25 04:36:16 PM PDT 24
Peak memory 398880 kb
Host smart-8a032db2-9669-4022-86e3-1b9267d71276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1388974584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1388974584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.2152897290
Short name T331
Test name
Test status
Simulation time 30187640114 ps
CPU time 1980.68 seconds
Started Apr 25 04:00:21 PM PDT 24
Finished Apr 25 04:33:23 PM PDT 24
Peak memory 381660 kb
Host smart-0666c4d3-5ff6-44b1-8271-7a9a5301c328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2152897290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.2152897290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.3808148704
Short name T834
Test name
Test status
Simulation time 190660444100 ps
CPU time 1712.43 seconds
Started Apr 25 04:00:20 PM PDT 24
Finished Apr 25 04:28:53 PM PDT 24
Peak memory 339832 kb
Host smart-bf71e1b0-1e22-46c5-a3a2-458d4a5f3618
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3808148704 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.3808148704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.1193290842
Short name T290
Test name
Test status
Simulation time 68635461762 ps
CPU time 1329.17 seconds
Started Apr 25 04:00:21 PM PDT 24
Finished Apr 25 04:22:31 PM PDT 24
Peak memory 299492 kb
Host smart-1515afb3-3042-449e-9a58-4d9e22181735
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1193290842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1193290842 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.1339703447
Short name T730
Test name
Test status
Simulation time 181307534547 ps
CPU time 5495.42 seconds
Started Apr 25 04:00:21 PM PDT 24
Finished Apr 25 05:31:57 PM PDT 24
Peak memory 650372 kb
Host smart-81dfbc4d-1a3f-4ddd-a5b4-430aed92e809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1339703447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.1339703447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1425900078
Short name T252
Test name
Test status
Simulation time 225656434565 ps
CPU time 4022.11 seconds
Started Apr 25 04:00:21 PM PDT 24
Finished Apr 25 05:07:24 PM PDT 24
Peak memory 577512 kb
Host smart-0a5b887e-ab81-42be-86b0-fda6f5bb9afb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1425900078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1425900078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.922267906
Short name T837
Test name
Test status
Simulation time 67718016 ps
CPU time 0.97 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:01:03 PM PDT 24
Peak memory 217872 kb
Host smart-db69bc4c-73ca-495f-8e89-6670b8fe8ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922267906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.922267906 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_app.2678720735
Short name T616
Test name
Test status
Simulation time 23901083264 ps
CPU time 395.53 seconds
Started Apr 25 04:00:50 PM PDT 24
Finished Apr 25 04:07:26 PM PDT 24
Peak memory 250152 kb
Host smart-d306d97c-ab06-4e19-9652-331d36100d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678720735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2678720735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/default/13.kmac_burst_write.1601027968
Short name T1022
Test name
Test status
Simulation time 158378514170 ps
CPU time 736.99 seconds
Started Apr 25 04:00:42 PM PDT 24
Finished Apr 25 04:13:00 PM PDT 24
Peak memory 242700 kb
Host smart-0eed999c-d6e8-4dc9-90e9-f5887d5a1d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601027968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1601027968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.52724735
Short name T843
Test name
Test status
Simulation time 313755081 ps
CPU time 27.08 seconds
Started Apr 25 04:00:56 PM PDT 24
Finished Apr 25 04:01:24 PM PDT 24
Peak memory 226628 kb
Host smart-e4768576-4219-469a-af38-a2fecd10ed6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=52724735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.52724735 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.759801362
Short name T299
Test name
Test status
Simulation time 30227629 ps
CPU time 0.9 seconds
Started Apr 25 04:00:57 PM PDT 24
Finished Apr 25 04:00:58 PM PDT 24
Peak memory 220164 kb
Host smart-1a88f472-c13e-44f7-bb82-154e17fdcf28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=759801362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.759801362 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.3522572519
Short name T779
Test name
Test status
Simulation time 7465794324 ps
CPU time 150.83 seconds
Started Apr 25 04:00:50 PM PDT 24
Finished Apr 25 04:03:21 PM PDT 24
Peak memory 235456 kb
Host smart-f6223fe8-e82e-4f6a-ba94-4dc18d43f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522572519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3522572519 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2120041853
Short name T723
Test name
Test status
Simulation time 7814610495 ps
CPU time 54.29 seconds
Started Apr 25 04:00:57 PM PDT 24
Finished Apr 25 04:01:52 PM PDT 24
Peak memory 236544 kb
Host smart-c7580e82-7651-4c59-ae1a-8eada35290b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120041853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2120041853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.851514362
Short name T697
Test name
Test status
Simulation time 1520686530 ps
CPU time 2.91 seconds
Started Apr 25 04:00:57 PM PDT 24
Finished Apr 25 04:01:00 PM PDT 24
Peak memory 218028 kb
Host smart-1bab6c28-fd46-48bf-bc66-8efa8f14e8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851514362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.851514362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.2733056676
Short name T658
Test name
Test status
Simulation time 157106939 ps
CPU time 1.54 seconds
Started Apr 25 04:01:03 PM PDT 24
Finished Apr 25 04:01:05 PM PDT 24
Peak memory 219080 kb
Host smart-df10bd33-ee23-415e-ab0f-bb5c115f323e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733056676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.2733056676 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.2273746982
Short name T402
Test name
Test status
Simulation time 9388097779 ps
CPU time 292.47 seconds
Started Apr 25 04:00:35 PM PDT 24
Finished Apr 25 04:05:28 PM PDT 24
Peak memory 247712 kb
Host smart-abe40f8a-4332-45c3-a819-2526cbef9547
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273746982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_a
nd_output.2273746982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.1798299843
Short name T654
Test name
Test status
Simulation time 54908091720 ps
CPU time 383.63 seconds
Started Apr 25 04:00:40 PM PDT 24
Finished Apr 25 04:07:04 PM PDT 24
Peak memory 246808 kb
Host smart-3b25ac36-db18-42d0-83a0-7b96ea99219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798299843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.1798299843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.891609064
Short name T187
Test name
Test status
Simulation time 3722492744 ps
CPU time 20.82 seconds
Started Apr 25 04:00:37 PM PDT 24
Finished Apr 25 04:00:58 PM PDT 24
Peak memory 226356 kb
Host smart-4e382bf6-81d8-4235-b798-523eb69ec7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891609064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.891609064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.2685890763
Short name T43
Test name
Test status
Simulation time 15267608108 ps
CPU time 154.35 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:03:37 PM PDT 24
Peak memory 259468 kb
Host smart-f3cdee50-9dd6-47e0-935a-3b6984ca108d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2685890763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2685890763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_stress_all_with_rand_reset.2779426880
Short name T47
Test name
Test status
Simulation time 37494494772 ps
CPU time 854.62 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:15:17 PM PDT 24
Peak memory 288516 kb
Host smart-b24949e6-ca90-4c20-add7-76e680c60fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2779426880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.2779426880 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.176359140
Short name T731
Test name
Test status
Simulation time 406249164 ps
CPU time 5.9 seconds
Started Apr 25 04:00:46 PM PDT 24
Finished Apr 25 04:00:53 PM PDT 24
Peak memory 218208 kb
Host smart-b4039a46-6c08-41e3-a5a4-0ee2aade6419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176359140 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.kmac_test_vectors_kmac.176359140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.2186137108
Short name T774
Test name
Test status
Simulation time 4358200056 ps
CPU time 7.92 seconds
Started Apr 25 04:00:51 PM PDT 24
Finished Apr 25 04:00:59 PM PDT 24
Peak memory 218312 kb
Host smart-42587cc4-6e62-4dbc-8f24-051cfed4f2eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186137108 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.kmac_test_vectors_kmac_xof.2186137108 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.4125739612
Short name T1028
Test name
Test status
Simulation time 276982849925 ps
CPU time 2371.39 seconds
Started Apr 25 04:00:40 PM PDT 24
Finished Apr 25 04:40:12 PM PDT 24
Peak memory 400164 kb
Host smart-f3e02e11-c431-4c6b-85c4-917b873b0fc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4125739612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.4125739612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3949832182
Short name T306
Test name
Test status
Simulation time 277893350835 ps
CPU time 1778.3 seconds
Started Apr 25 04:00:40 PM PDT 24
Finished Apr 25 04:30:19 PM PDT 24
Peak memory 335672 kb
Host smart-4caa996d-c4e5-4902-bf27-bb56ec0be5bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3949832182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3949832182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.674634274
Short name T734
Test name
Test status
Simulation time 178655989902 ps
CPU time 1311.98 seconds
Started Apr 25 04:00:41 PM PDT 24
Finished Apr 25 04:22:34 PM PDT 24
Peak memory 300232 kb
Host smart-28534b5e-4a6f-4392-8991-2fa2f5c13fbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=674634274 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.674634274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.551012353
Short name T853
Test name
Test status
Simulation time 357099100282 ps
CPU time 5659.57 seconds
Started Apr 25 04:00:44 PM PDT 24
Finished Apr 25 05:35:04 PM PDT 24
Peak memory 658580 kb
Host smart-c358d9f1-f538-4eab-8aba-3a5e31c2296b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=551012353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.551012353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.2931222227
Short name T581
Test name
Test status
Simulation time 841214827462 ps
CPU time 5170.6 seconds
Started Apr 25 04:00:42 PM PDT 24
Finished Apr 25 05:26:54 PM PDT 24
Peak memory 575652 kb
Host smart-9c87cbbd-34e0-47a2-ab06-590ff89e6fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2931222227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.2931222227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.3529596522
Short name T1062
Test name
Test status
Simulation time 24109641 ps
CPU time 0.87 seconds
Started Apr 25 04:01:19 PM PDT 24
Finished Apr 25 04:01:21 PM PDT 24
Peak memory 217872 kb
Host smart-acaa70b5-2743-49a0-b5ff-ae22fa8c7b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529596522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.3529596522 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.1297052940
Short name T194
Test name
Test status
Simulation time 18766627191 ps
CPU time 239.58 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 04:05:13 PM PDT 24
Peak memory 241816 kb
Host smart-0050ff17-de4b-4e98-9690-a2178c8e0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297052940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1297052940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.3488783200
Short name T561
Test name
Test status
Simulation time 132373463423 ps
CPU time 1241.68 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 04:21:55 PM PDT 24
Peak memory 237532 kb
Host smart-5ed3f3b5-d63a-470e-b10d-ac4f48f1d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488783200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3488783200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.3205214224
Short name T720
Test name
Test status
Simulation time 634035065 ps
CPU time 39.79 seconds
Started Apr 25 04:01:13 PM PDT 24
Finished Apr 25 04:01:53 PM PDT 24
Peak memory 226772 kb
Host smart-1cf88684-b2c2-470a-aefa-9eac0f664f99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205214224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.3205214224 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.2715516952
Short name T667
Test name
Test status
Simulation time 20178472 ps
CPU time 1.1 seconds
Started Apr 25 04:01:14 PM PDT 24
Finished Apr 25 04:01:16 PM PDT 24
Peak memory 221464 kb
Host smart-5ee200c5-65c8-4977-ab9d-bb11b99dd5ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2715516952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2715516952 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.1721450171
Short name T1010
Test name
Test status
Simulation time 10850974335 ps
CPU time 344.59 seconds
Started Apr 25 04:01:13 PM PDT 24
Finished Apr 25 04:06:58 PM PDT 24
Peak memory 247384 kb
Host smart-b83fd83f-a379-4c4a-b30e-bbf0cce096b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721450171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1721450171 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.391828728
Short name T935
Test name
Test status
Simulation time 18324494416 ps
CPU time 110.97 seconds
Started Apr 25 04:01:13 PM PDT 24
Finished Apr 25 04:03:04 PM PDT 24
Peak memory 243076 kb
Host smart-6b9a0160-e0c3-4963-914a-c9785d59572c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391828728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.391828728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.4100310830
Short name T999
Test name
Test status
Simulation time 105531102 ps
CPU time 1.21 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 04:01:15 PM PDT 24
Peak memory 218044 kb
Host smart-effd3ede-fad6-4bd4-bb40-56fc3e33bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100310830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.4100310830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.1638399135
Short name T105
Test name
Test status
Simulation time 170454102 ps
CPU time 1.63 seconds
Started Apr 25 04:01:19 PM PDT 24
Finished Apr 25 04:01:22 PM PDT 24
Peak memory 218228 kb
Host smart-d7023117-94b9-407b-9d63-1a3cc5c426c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638399135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.1638399135 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.4027896740
Short name T506
Test name
Test status
Simulation time 20352698245 ps
CPU time 554.13 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:10:17 PM PDT 24
Peak memory 259820 kb
Host smart-ad3c38e8-33fe-40bd-bcb8-d71c14196bb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027896740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.4027896740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.1477543634
Short name T695
Test name
Test status
Simulation time 6551430311 ps
CPU time 116.3 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:02:59 PM PDT 24
Peak memory 239872 kb
Host smart-cb0a4adf-75fa-49f5-ae35-d6231c0eec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477543634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.1477543634 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.4124028674
Short name T294
Test name
Test status
Simulation time 2292261000 ps
CPU time 26.03 seconds
Started Apr 25 04:01:02 PM PDT 24
Finished Apr 25 04:01:29 PM PDT 24
Peak memory 221340 kb
Host smart-7b42f68d-a86c-4dcf-9a1e-e959e5d08719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124028674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.4124028674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all.3948057641
Short name T657
Test name
Test status
Simulation time 128915151893 ps
CPU time 1487.14 seconds
Started Apr 25 04:01:19 PM PDT 24
Finished Apr 25 04:26:07 PM PDT 24
Peak memory 378088 kb
Host smart-1bf6c4ed-d0cb-4632-bdb8-d9cd89d71214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3948057641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3948057641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all/latest

Test location /workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3920579200
Short name T130
Test name
Test status
Simulation time 109754036393 ps
CPU time 2145.31 seconds
Started Apr 25 04:01:19 PM PDT 24
Finished Apr 25 04:37:06 PM PDT 24
Peak memory 349924 kb
Host smart-d712bc6a-7d9e-4a62-86d3-48a353290a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920579200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3920579200 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.2437290481
Short name T1033
Test name
Test status
Simulation time 1089483441 ps
CPU time 7.34 seconds
Started Apr 25 04:01:11 PM PDT 24
Finished Apr 25 04:01:19 PM PDT 24
Peak memory 219184 kb
Host smart-683c0667-4ae2-4b54-b2af-1404b9f5e226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437290481 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.kmac_test_vectors_kmac.2437290481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.990274698
Short name T728
Test name
Test status
Simulation time 515537417 ps
CPU time 7.11 seconds
Started Apr 25 04:01:13 PM PDT 24
Finished Apr 25 04:01:21 PM PDT 24
Peak memory 218188 kb
Host smart-dded9fcf-c00f-4597-bbdb-6b5401f1de82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990274698 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.kmac_test_vectors_kmac_xof.990274698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.3174782585
Short name T1020
Test name
Test status
Simulation time 68922616674 ps
CPU time 2282.15 seconds
Started Apr 25 04:01:11 PM PDT 24
Finished Apr 25 04:39:15 PM PDT 24
Peak memory 399476 kb
Host smart-d82713cb-e398-4db0-b6d5-eca644993211
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3174782585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.3174782585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.2554457820
Short name T591
Test name
Test status
Simulation time 134106209231 ps
CPU time 2127.37 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 04:36:40 PM PDT 24
Peak memory 383220 kb
Host smart-f68f43c0-0d23-4260-82ed-397b0f0f7551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2554457820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2554457820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.3225168074
Short name T909
Test name
Test status
Simulation time 309466162180 ps
CPU time 1810.51 seconds
Started Apr 25 04:01:13 PM PDT 24
Finished Apr 25 04:31:24 PM PDT 24
Peak memory 343680 kb
Host smart-ad361f32-8c4e-4f56-8eee-d50f8ec62990
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3225168074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.3225168074 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.241628042
Short name T524
Test name
Test status
Simulation time 99469690958 ps
CPU time 1402.29 seconds
Started Apr 25 04:01:11 PM PDT 24
Finished Apr 25 04:24:34 PM PDT 24
Peak memory 301824 kb
Host smart-5424e7de-ebcf-44d5-95b6-db6519029ee0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=241628042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.241628042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.3146168809
Short name T845
Test name
Test status
Simulation time 1287309900229 ps
CPU time 5307.4 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 05:29:41 PM PDT 24
Peak memory 641628 kb
Host smart-9daf257e-44b9-4990-8d76-97afb31fd20f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3146168809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3146168809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.1402670042
Short name T334
Test name
Test status
Simulation time 186490776155 ps
CPU time 4633.37 seconds
Started Apr 25 04:01:12 PM PDT 24
Finished Apr 25 05:18:26 PM PDT 24
Peak memory 565552 kb
Host smart-a03582f4-0648-4746-80e3-13374b4105a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1402670042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.1402670042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.933917031
Short name T1044
Test name
Test status
Simulation time 19293816 ps
CPU time 0.81 seconds
Started Apr 25 04:01:49 PM PDT 24
Finished Apr 25 04:01:51 PM PDT 24
Peak memory 217908 kb
Host smart-07b12b21-b0db-4d64-ab12-c811d988a4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933917031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.933917031 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.4130402082
Short name T717
Test name
Test status
Simulation time 1092645608 ps
CPU time 7.32 seconds
Started Apr 25 04:01:43 PM PDT 24
Finished Apr 25 04:01:51 PM PDT 24
Peak memory 218296 kb
Host smart-269c8d72-56a8-45d7-a4f6-66cba5a6b5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130402082 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.4130402082 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_burst_write.2362017036
Short name T286
Test name
Test status
Simulation time 3589704677 ps
CPU time 189.15 seconds
Started Apr 25 04:01:57 PM PDT 24
Finished Apr 25 04:05:10 PM PDT 24
Peak memory 226812 kb
Host smart-9f280da4-ae0d-453c-9c1f-867599aa524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362017036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2362017036 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.1540940022
Short name T965
Test name
Test status
Simulation time 41305865 ps
CPU time 1.08 seconds
Started Apr 25 04:01:52 PM PDT 24
Finished Apr 25 04:01:55 PM PDT 24
Peak memory 222304 kb
Host smart-34143e1d-5f0b-4546-b8c3-1e12a12e99d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540940022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.1540940022 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.1998041424
Short name T14
Test name
Test status
Simulation time 18208815 ps
CPU time 0.9 seconds
Started Apr 25 04:01:53 PM PDT 24
Finished Apr 25 04:01:56 PM PDT 24
Peak memory 220092 kb
Host smart-8ce9c155-d878-46ce-85b2-533edb60596e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1998041424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1998041424 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.3957796767
Short name T1070
Test name
Test status
Simulation time 4128294499 ps
CPU time 99.58 seconds
Started Apr 25 04:01:41 PM PDT 24
Finished Apr 25 04:03:21 PM PDT 24
Peak memory 241176 kb
Host smart-47301f30-2fdf-41f6-8954-0e15b120f715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957796767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.3957796767 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.254655431
Short name T766
Test name
Test status
Simulation time 1804738123 ps
CPU time 146.65 seconds
Started Apr 25 04:01:41 PM PDT 24
Finished Apr 25 04:04:08 PM PDT 24
Peak memory 243732 kb
Host smart-0742d134-475d-46a6-9c69-dec65cc9eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254655431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.254655431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.1272711379
Short name T17
Test name
Test status
Simulation time 4599504167 ps
CPU time 6.74 seconds
Started Apr 25 04:01:43 PM PDT 24
Finished Apr 25 04:01:50 PM PDT 24
Peak memory 218164 kb
Host smart-770e9c2f-84c7-4012-a3db-46972c5c12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272711379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.1272711379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.3885106982
Short name T22
Test name
Test status
Simulation time 40152653 ps
CPU time 1.42 seconds
Started Apr 25 04:01:48 PM PDT 24
Finished Apr 25 04:01:50 PM PDT 24
Peak memory 218220 kb
Host smart-336c7373-3d55-43ce-8da3-cf788e876a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885106982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.3885106982 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.288985451
Short name T1017
Test name
Test status
Simulation time 53475582168 ps
CPU time 1313.97 seconds
Started Apr 25 04:01:19 PM PDT 24
Finished Apr 25 04:23:14 PM PDT 24
Peak memory 323280 kb
Host smart-ea2ced72-e2ab-440f-bd56-34d2bac94278
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288985451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_an
d_output.288985451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.1107362107
Short name T850
Test name
Test status
Simulation time 68571224226 ps
CPU time 393.82 seconds
Started Apr 25 04:01:24 PM PDT 24
Finished Apr 25 04:07:59 PM PDT 24
Peak memory 247396 kb
Host smart-e8b3fb8d-6ff0-4b83-9171-7692526bf5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107362107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1107362107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.1827340427
Short name T824
Test name
Test status
Simulation time 9620593408 ps
CPU time 62.04 seconds
Started Apr 25 04:01:20 PM PDT 24
Finished Apr 25 04:02:23 PM PDT 24
Peak memory 226336 kb
Host smart-9e682281-f61d-4be9-9716-dc4154cab152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827340427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.1827340427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1351030113
Short name T371
Test name
Test status
Simulation time 4364943354 ps
CPU time 140.51 seconds
Started Apr 25 04:01:53 PM PDT 24
Finished Apr 25 04:04:15 PM PDT 24
Peak memory 242948 kb
Host smart-57204166-8969-44eb-a9e9-eb7ea5e01b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1351030113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1351030113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.1865008294
Short name T370
Test name
Test status
Simulation time 204712755 ps
CPU time 5.5 seconds
Started Apr 25 04:01:48 PM PDT 24
Finished Apr 25 04:01:55 PM PDT 24
Peak memory 218152 kb
Host smart-6a943ee2-1bdd-4316-a71f-4ea202be9168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865008294 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.1865008294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3719439409
Short name T465
Test name
Test status
Simulation time 464808892 ps
CPU time 6.46 seconds
Started Apr 25 04:01:41 PM PDT 24
Finished Apr 25 04:01:48 PM PDT 24
Peak memory 218244 kb
Host smart-858a0cc2-2867-4413-b631-1eb4efda39dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719439409 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3719439409 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.4159244248
Short name T119
Test name
Test status
Simulation time 100364495319 ps
CPU time 2497.87 seconds
Started Apr 25 04:01:29 PM PDT 24
Finished Apr 25 04:43:07 PM PDT 24
Peak memory 397284 kb
Host smart-f6571e5f-fd65-49ea-b350-ae42e3341f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4159244248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.4159244248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.202629882
Short name T1005
Test name
Test status
Simulation time 43552484989 ps
CPU time 1942.76 seconds
Started Apr 25 04:01:33 PM PDT 24
Finished Apr 25 04:33:56 PM PDT 24
Peak memory 393272 kb
Host smart-0d0efee1-4933-45e1-8fa1-3bf827da320a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=202629882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.202629882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.278248622
Short name T903
Test name
Test status
Simulation time 16058771887 ps
CPU time 1688.27 seconds
Started Apr 25 04:01:37 PM PDT 24
Finished Apr 25 04:29:46 PM PDT 24
Peak memory 341468 kb
Host smart-00b851ce-13ce-4e44-9bd5-339988e999ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=278248622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.278248622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.4138389545
Short name T805
Test name
Test status
Simulation time 205961648675 ps
CPU time 1404.01 seconds
Started Apr 25 04:01:37 PM PDT 24
Finished Apr 25 04:25:02 PM PDT 24
Peak memory 300384 kb
Host smart-0d90696b-63c2-4374-af4a-11de41b33e5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4138389545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.4138389545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.1507726463
Short name T1041
Test name
Test status
Simulation time 58928731229 ps
CPU time 4413.92 seconds
Started Apr 25 04:02:03 PM PDT 24
Finished Apr 25 05:15:38 PM PDT 24
Peak memory 639628 kb
Host smart-958627a7-2570-48b7-a222-f70671b231ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1507726463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1507726463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.1892308849
Short name T466
Test name
Test status
Simulation time 220336021723 ps
CPU time 4767.14 seconds
Started Apr 25 04:01:37 PM PDT 24
Finished Apr 25 05:21:06 PM PDT 24
Peak memory 581424 kb
Host smart-b4c78d82-69c4-4d21-873b-4dedb5ffa768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1892308849 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1892308849 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_app.2866888965
Short name T215
Test name
Test status
Simulation time 22360501434 ps
CPU time 344.18 seconds
Started Apr 25 04:02:02 PM PDT 24
Finished Apr 25 04:07:47 PM PDT 24
Peak memory 249780 kb
Host smart-d9220e41-26bb-4133-9a2b-b44a28ddd9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866888965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.2866888965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.2394184812
Short name T103
Test name
Test status
Simulation time 14103302017 ps
CPU time 657.57 seconds
Started Apr 25 04:01:52 PM PDT 24
Finished Apr 25 04:12:51 PM PDT 24
Peak memory 234208 kb
Host smart-678fe838-7571-4a6f-948d-5e1aab50b27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394184812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.2394184812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.1111562977
Short name T79
Test name
Test status
Simulation time 32860981 ps
CPU time 1.2 seconds
Started Apr 25 04:02:02 PM PDT 24
Finished Apr 25 04:02:04 PM PDT 24
Peak memory 222588 kb
Host smart-894d0997-5701-4356-a363-0d22d7cd66d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1111562977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.1111562977 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.3549590860
Short name T397
Test name
Test status
Simulation time 83356133 ps
CPU time 0.96 seconds
Started Apr 25 04:02:02 PM PDT 24
Finished Apr 25 04:02:04 PM PDT 24
Peak memory 220004 kb
Host smart-f877cdb9-0d80-4516-b5ea-85284e00e52b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3549590860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.3549590860 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.1644407571
Short name T1045
Test name
Test status
Simulation time 416541403 ps
CPU time 12.24 seconds
Started Apr 25 04:02:01 PM PDT 24
Finished Apr 25 04:02:15 PM PDT 24
Peak memory 219932 kb
Host smart-a6ebe138-ada1-46a7-b891-6af6bb28e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644407571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1644407571 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.3428703433
Short name T876
Test name
Test status
Simulation time 156030054590 ps
CPU time 330.57 seconds
Started Apr 25 04:02:03 PM PDT 24
Finished Apr 25 04:07:34 PM PDT 24
Peak memory 254136 kb
Host smart-d0af8c00-4d91-4e9c-85f1-52193d10b314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428703433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.3428703433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2076331771
Short name T1056
Test name
Test status
Simulation time 45893895 ps
CPU time 1.44 seconds
Started Apr 25 04:02:02 PM PDT 24
Finished Apr 25 04:02:04 PM PDT 24
Peak memory 218200 kb
Host smart-fe54cade-2f4b-4429-95f7-613c88a1962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076331771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2076331771 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.3864750831
Short name T963
Test name
Test status
Simulation time 67602199255 ps
CPU time 1710.17 seconds
Started Apr 25 04:01:58 PM PDT 24
Finished Apr 25 04:30:30 PM PDT 24
Peak memory 349904 kb
Host smart-15105e01-2a92-4263-8dd8-30a975cc4526
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864750831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a
nd_output.3864750831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.3212795053
Short name T241
Test name
Test status
Simulation time 26999288278 ps
CPU time 424.45 seconds
Started Apr 25 04:01:53 PM PDT 24
Finished Apr 25 04:08:59 PM PDT 24
Peak memory 251996 kb
Host smart-aca26d35-b363-4f5a-887e-67d96f878b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212795053 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3212795053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.4021222212
Short name T238
Test name
Test status
Simulation time 2206231974 ps
CPU time 76.68 seconds
Started Apr 25 04:01:52 PM PDT 24
Finished Apr 25 04:03:10 PM PDT 24
Peak memory 226408 kb
Host smart-f0a5fec9-8f5e-41aa-9205-2f3d334da3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021222212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.4021222212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.4074333000
Short name T815
Test name
Test status
Simulation time 138595060508 ps
CPU time 1695.84 seconds
Started Apr 25 04:02:02 PM PDT 24
Finished Apr 25 04:30:19 PM PDT 24
Peak memory 346072 kb
Host smart-f8e81100-cb8b-48f1-be5f-0826027530e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4074333000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.4074333000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.1101652997
Short name T727
Test name
Test status
Simulation time 196538929 ps
CPU time 6.13 seconds
Started Apr 25 04:01:57 PM PDT 24
Finished Apr 25 04:02:05 PM PDT 24
Peak memory 218208 kb
Host smart-8ec4926d-10e9-48c0-8b0f-e68bc76a4f60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101652997 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.1101652997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.337313890
Short name T364
Test name
Test status
Simulation time 2271758437 ps
CPU time 6.26 seconds
Started Apr 25 04:01:59 PM PDT 24
Finished Apr 25 04:02:07 PM PDT 24
Peak memory 218208 kb
Host smart-69e3be01-0d62-488a-ab6c-abe69cf10197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337313890 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.kmac_test_vectors_kmac_xof.337313890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.3592294678
Short name T715
Test name
Test status
Simulation time 399827187307 ps
CPU time 2381.68 seconds
Started Apr 25 04:01:57 PM PDT 24
Finished Apr 25 04:41:41 PM PDT 24
Peak memory 391588 kb
Host smart-7157f72a-1409-4b67-adba-f6daf8442b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3592294678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3592294678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.1243149531
Short name T249
Test name
Test status
Simulation time 28570719269 ps
CPU time 1829.41 seconds
Started Apr 25 04:01:56 PM PDT 24
Finished Apr 25 04:32:28 PM PDT 24
Peak memory 395520 kb
Host smart-03279714-9e20-422a-9626-3932e0ad7b78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1243149531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1243149531 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1259115791
Short name T679
Test name
Test status
Simulation time 148738398135 ps
CPU time 1737.82 seconds
Started Apr 25 04:02:04 PM PDT 24
Finished Apr 25 04:31:03 PM PDT 24
Peak memory 344928 kb
Host smart-cffe62bb-07ff-4a63-a117-e5dd8be5566a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1259115791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1259115791 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1369470184
Short name T528
Test name
Test status
Simulation time 49811871838 ps
CPU time 1290.44 seconds
Started Apr 25 04:01:57 PM PDT 24
Finished Apr 25 04:23:30 PM PDT 24
Peak memory 296120 kb
Host smart-8a057726-ee6b-4449-ad6a-1611f8b948a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1369470184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1369470184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.1149633980
Short name T1006
Test name
Test status
Simulation time 1941240827584 ps
CPU time 5366.16 seconds
Started Apr 25 04:01:58 PM PDT 24
Finished Apr 25 05:31:26 PM PDT 24
Peak memory 645228 kb
Host smart-f982365d-5b2c-4924-84c6-7d963cdfc3e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1149633980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.1149633980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_alert_test.135114783
Short name T51
Test name
Test status
Simulation time 12777386 ps
CPU time 0.84 seconds
Started Apr 25 04:02:29 PM PDT 24
Finished Apr 25 04:02:30 PM PDT 24
Peak memory 217872 kb
Host smart-dfdee0fd-bf7f-47c5-a8a2-81ceedf44f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135114783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.135114783 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2671890377
Short name T593
Test name
Test status
Simulation time 23290728489 ps
CPU time 101.75 seconds
Started Apr 25 04:02:25 PM PDT 24
Finished Apr 25 04:04:07 PM PDT 24
Peak memory 234184 kb
Host smart-9045412c-9c5b-4dcd-b5fc-8cbcb26c75b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671890377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2671890377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2176311869
Short name T1075
Test name
Test status
Simulation time 44025985418 ps
CPU time 572.8 seconds
Started Apr 25 04:02:14 PM PDT 24
Finished Apr 25 04:11:47 PM PDT 24
Peak memory 231324 kb
Host smart-2d4eb239-75a4-4ac6-9a4e-adf83ba2dd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176311869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2176311869 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1880795355
Short name T456
Test name
Test status
Simulation time 559928231 ps
CPU time 50.24 seconds
Started Apr 25 04:02:25 PM PDT 24
Finished Apr 25 04:03:16 PM PDT 24
Peak memory 226828 kb
Host smart-28ba04cc-ec2a-4c9a-b66f-7224164483ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1880795355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1880795355 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.1454914054
Short name T82
Test name
Test status
Simulation time 63229070 ps
CPU time 1.24 seconds
Started Apr 25 04:02:23 PM PDT 24
Finished Apr 25 04:02:25 PM PDT 24
Peak memory 221424 kb
Host smart-e547bbba-1897-4159-b8a6-8c39770f1afd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1454914054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1454914054 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_error.1097078828
Short name T409
Test name
Test status
Simulation time 17406867942 ps
CPU time 399.89 seconds
Started Apr 25 04:02:23 PM PDT 24
Finished Apr 25 04:09:03 PM PDT 24
Peak memory 259032 kb
Host smart-18d2e7a0-5437-4c80-8260-069e86ce6373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097078828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1097078828 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.2580493038
Short name T1031
Test name
Test status
Simulation time 339721517 ps
CPU time 1.04 seconds
Started Apr 25 04:02:25 PM PDT 24
Finished Apr 25 04:02:27 PM PDT 24
Peak memory 218012 kb
Host smart-c712267d-97ae-432b-b8c0-012910d26b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580493038 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2580493038 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.2081402783
Short name T551
Test name
Test status
Simulation time 52477939 ps
CPU time 1.54 seconds
Started Apr 25 04:02:31 PM PDT 24
Finished Apr 25 04:02:33 PM PDT 24
Peak memory 218200 kb
Host smart-ccef42c3-a9dc-45e7-9b60-f79af1b87b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081402783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.2081402783 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.438272353
Short name T810
Test name
Test status
Simulation time 59791493496 ps
CPU time 1883.2 seconds
Started Apr 25 04:02:08 PM PDT 24
Finished Apr 25 04:33:32 PM PDT 24
Peak memory 395800 kb
Host smart-8f121e1b-dd98-4944-9614-94a63028c370
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438272353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_an
d_output.438272353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.3697318239
Short name T957
Test name
Test status
Simulation time 21574779716 ps
CPU time 211.75 seconds
Started Apr 25 04:02:12 PM PDT 24
Finished Apr 25 04:05:45 PM PDT 24
Peak memory 238188 kb
Host smart-2cc81949-c3c5-4a35-8361-b1faccf4c64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697318239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3697318239 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1176595056
Short name T823
Test name
Test status
Simulation time 6996406500 ps
CPU time 36.82 seconds
Started Apr 25 04:02:08 PM PDT 24
Finished Apr 25 04:02:45 PM PDT 24
Peak memory 225304 kb
Host smart-c4a24242-9a16-4c81-aa23-7257c470c9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176595056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1176595056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all.2030501209
Short name T918
Test name
Test status
Simulation time 447555727765 ps
CPU time 845.82 seconds
Started Apr 25 04:02:24 PM PDT 24
Finished Apr 25 04:16:30 PM PDT 24
Peak memory 269624 kb
Host smart-5819511a-9a25-4f85-b1cb-b525649b70b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2030501209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.2030501209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.437291396
Short name T114
Test name
Test status
Simulation time 89177682 ps
CPU time 6.01 seconds
Started Apr 25 04:02:20 PM PDT 24
Finished Apr 25 04:02:26 PM PDT 24
Peak memory 218204 kb
Host smart-f42e6f06-fa87-47ce-a683-dca8b9aeaf0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437291396 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.437291396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2274366614
Short name T567
Test name
Test status
Simulation time 481999496 ps
CPU time 7.26 seconds
Started Apr 25 04:02:19 PM PDT 24
Finished Apr 25 04:02:27 PM PDT 24
Peak memory 218224 kb
Host smart-37ce59ee-f1f4-46cf-aeb2-c9c920cc7169
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274366614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2274366614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.1573484170
Short name T913
Test name
Test status
Simulation time 437829032247 ps
CPU time 2205.56 seconds
Started Apr 25 04:02:15 PM PDT 24
Finished Apr 25 04:39:01 PM PDT 24
Peak memory 391416 kb
Host smart-04fd58f2-441a-4995-851e-f9a79e6f8861
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1573484170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.1573484170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.3009327415
Short name T873
Test name
Test status
Simulation time 273048919545 ps
CPU time 2254.84 seconds
Started Apr 25 04:02:13 PM PDT 24
Finished Apr 25 04:39:48 PM PDT 24
Peak memory 393208 kb
Host smart-48cb273f-eb88-4f7c-adff-2b136eb345f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3009327415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3009327415 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.655573031
Short name T365
Test name
Test status
Simulation time 93322301400 ps
CPU time 1494.06 seconds
Started Apr 25 04:02:18 PM PDT 24
Finished Apr 25 04:27:13 PM PDT 24
Peak memory 334416 kb
Host smart-a42a3b07-6aab-40a7-a75c-123841cba35a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=655573031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.655573031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.2692637689
Short name T1015
Test name
Test status
Simulation time 33874671005 ps
CPU time 1421.94 seconds
Started Apr 25 04:02:20 PM PDT 24
Finished Apr 25 04:26:03 PM PDT 24
Peak memory 303716 kb
Host smart-51cba749-5e75-48d2-b498-0964301b64ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2692637689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.2692637689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.1926381402
Short name T640
Test name
Test status
Simulation time 261493189423 ps
CPU time 5831.71 seconds
Started Apr 25 04:02:18 PM PDT 24
Finished Apr 25 05:39:31 PM PDT 24
Peak memory 664584 kb
Host smart-4538e97d-ff51-488b-82d1-673fe4463348
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1926381402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.1926381402 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.838289011
Short name T248
Test name
Test status
Simulation time 473400656705 ps
CPU time 4772.79 seconds
Started Apr 25 04:02:18 PM PDT 24
Finished Apr 25 05:21:52 PM PDT 24
Peak memory 576100 kb
Host smart-25490e12-cbca-45d8-acc6-036042b82f0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=838289011 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.838289011 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.988088833
Short name T986
Test name
Test status
Simulation time 15638894 ps
CPU time 0.9 seconds
Started Apr 25 04:02:46 PM PDT 24
Finished Apr 25 04:02:47 PM PDT 24
Peak memory 217888 kb
Host smart-5f048e43-6d36-4810-b74e-8ea28c3a6334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988088833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.988088833 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2147905488
Short name T531
Test name
Test status
Simulation time 5462007446 ps
CPU time 295.93 seconds
Started Apr 25 04:02:46 PM PDT 24
Finished Apr 25 04:07:42 PM PDT 24
Peak memory 245928 kb
Host smart-5f006a9d-5dc6-4d8c-9ce9-360c2e192132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147905488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2147905488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.1469937369
Short name T1073
Test name
Test status
Simulation time 52951718247 ps
CPU time 441.97 seconds
Started Apr 25 04:02:34 PM PDT 24
Finished Apr 25 04:09:56 PM PDT 24
Peak memory 240560 kb
Host smart-69e86b98-cf13-4b65-9a1f-53fc7c9d4ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469937369 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.1469937369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.3162246201
Short name T419
Test name
Test status
Simulation time 5048066874 ps
CPU time 39.14 seconds
Started Apr 25 04:02:46 PM PDT 24
Finished Apr 25 04:03:25 PM PDT 24
Peak memory 235444 kb
Host smart-0a43a4f1-39bf-4e15-b884-0c5f26eebe98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162246201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3162246201 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.408365435
Short name T250
Test name
Test status
Simulation time 86877234 ps
CPU time 1.34 seconds
Started Apr 25 04:02:43 PM PDT 24
Finished Apr 25 04:02:45 PM PDT 24
Peak memory 221256 kb
Host smart-5184faf3-a35a-4c44-a99c-912501f431d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=408365435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.408365435 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3160746050
Short name T349
Test name
Test status
Simulation time 12696835038 ps
CPU time 76.9 seconds
Started Apr 25 04:02:47 PM PDT 24
Finished Apr 25 04:04:05 PM PDT 24
Peak memory 230272 kb
Host smart-b97e39df-e16a-4a92-824d-a5277de8ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160746050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3160746050 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.474364196
Short name T750
Test name
Test status
Simulation time 74693390503 ps
CPU time 454.18 seconds
Started Apr 25 04:02:41 PM PDT 24
Finished Apr 25 04:10:16 PM PDT 24
Peak memory 267864 kb
Host smart-5af6016e-51b1-4d84-b153-d4b470374737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474364196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.474364196 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.1494844447
Short name T770
Test name
Test status
Simulation time 810098638 ps
CPU time 4.65 seconds
Started Apr 25 04:02:41 PM PDT 24
Finished Apr 25 04:02:46 PM PDT 24
Peak memory 218152 kb
Host smart-f409f7d4-9095-4cdb-8402-366a66ab34bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494844447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.1494844447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.2298873985
Short name T323
Test name
Test status
Simulation time 65097744419 ps
CPU time 1577.39 seconds
Started Apr 25 04:02:33 PM PDT 24
Finished Apr 25 04:28:51 PM PDT 24
Peak memory 358992 kb
Host smart-7bd850d4-99c6-4184-9f7e-2b3af9af29ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298873985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.2298873985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.3403626572
Short name T783
Test name
Test status
Simulation time 1773117664 ps
CPU time 114.81 seconds
Started Apr 25 04:02:29 PM PDT 24
Finished Apr 25 04:04:25 PM PDT 24
Peak memory 230372 kb
Host smart-e20613d5-eff3-4050-acda-67db3ca26db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403626572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3403626572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.188799684
Short name T701
Test name
Test status
Simulation time 1837845714 ps
CPU time 68.8 seconds
Started Apr 25 04:02:30 PM PDT 24
Finished Apr 25 04:03:39 PM PDT 24
Peak memory 226264 kb
Host smart-49288664-f9ea-4092-a306-909fb16af6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188799684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.188799684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.2644919584
Short name T748
Test name
Test status
Simulation time 26879874273 ps
CPU time 523.09 seconds
Started Apr 25 04:02:48 PM PDT 24
Finished Apr 25 04:11:31 PM PDT 24
Peak memory 274480 kb
Host smart-35b59270-30a9-4208-805b-1c2b46361570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2644919584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.2644919584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.2379500318
Short name T579
Test name
Test status
Simulation time 441284419 ps
CPU time 5.73 seconds
Started Apr 25 04:02:41 PM PDT 24
Finished Apr 25 04:02:47 PM PDT 24
Peak memory 218232 kb
Host smart-d08251c6-8cd1-4900-97b2-6a31e4b95124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379500318 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.2379500318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.2680711622
Short name T282
Test name
Test status
Simulation time 268965287 ps
CPU time 7.31 seconds
Started Apr 25 04:02:41 PM PDT 24
Finished Apr 25 04:02:49 PM PDT 24
Peak memory 218240 kb
Host smart-155ca7f3-e58c-48ea-8d3c-75e2199e2f67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680711622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.2680711622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.3521149324
Short name T864
Test name
Test status
Simulation time 381268166536 ps
CPU time 2290.51 seconds
Started Apr 25 04:02:29 PM PDT 24
Finished Apr 25 04:40:40 PM PDT 24
Peak memory 390272 kb
Host smart-29ca171a-bcc2-4ba5-ab74-79c7905b83df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3521149324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3521149324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.3102980853
Short name T674
Test name
Test status
Simulation time 148348932660 ps
CPU time 1826.12 seconds
Started Apr 25 04:02:30 PM PDT 24
Finished Apr 25 04:32:56 PM PDT 24
Peak memory 386956 kb
Host smart-41713bdf-a3b8-4788-9277-a6cb3bef44c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3102980853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.3102980853 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.2607886865
Short name T955
Test name
Test status
Simulation time 15221732101 ps
CPU time 1684.28 seconds
Started Apr 25 04:02:29 PM PDT 24
Finished Apr 25 04:30:34 PM PDT 24
Peak memory 335464 kb
Host smart-3e48adb4-bb6d-48d5-b1c7-8c5cc5075114
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2607886865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.2607886865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.2779589263
Short name T714
Test name
Test status
Simulation time 22497407573 ps
CPU time 1196.96 seconds
Started Apr 25 04:02:35 PM PDT 24
Finished Apr 25 04:22:32 PM PDT 24
Peak memory 302932 kb
Host smart-a54c91fd-87fb-4080-8ddb-57d86886b7c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2779589263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.2779589263 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.623171537
Short name T675
Test name
Test status
Simulation time 398358929373 ps
CPU time 5815.88 seconds
Started Apr 25 04:02:37 PM PDT 24
Finished Apr 25 05:39:33 PM PDT 24
Peak memory 657100 kb
Host smart-072e5f05-3e99-4398-80dd-5872b4af2f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=623171537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.623171537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.455879438
Short name T260
Test name
Test status
Simulation time 62744896754 ps
CPU time 3985.42 seconds
Started Apr 25 04:02:37 PM PDT 24
Finished Apr 25 05:09:03 PM PDT 24
Peak memory 576172 kb
Host smart-645691ac-8c4c-40ff-a542-e177d5feec76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=455879438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.455879438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1328102520
Short name T242
Test name
Test status
Simulation time 31304289 ps
CPU time 0.9 seconds
Started Apr 25 04:03:15 PM PDT 24
Finished Apr 25 04:03:16 PM PDT 24
Peak memory 217880 kb
Host smart-b12997e1-107f-493d-98ed-ecbea248503f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328102520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1328102520 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2062989222
Short name T1046
Test name
Test status
Simulation time 15483755909 ps
CPU time 350.43 seconds
Started Apr 25 04:03:02 PM PDT 24
Finished Apr 25 04:08:53 PM PDT 24
Peak memory 248324 kb
Host smart-c35fe6e6-7b6f-4386-93d4-ac816fa914bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062989222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2062989222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.2872810626
Short name T574
Test name
Test status
Simulation time 59554957899 ps
CPU time 749.41 seconds
Started Apr 25 04:02:47 PM PDT 24
Finished Apr 25 04:15:17 PM PDT 24
Peak memory 234700 kb
Host smart-db0ddd42-9b98-40ad-8d80-85f2b0b6e28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872810626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.2872810626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.2985333901
Short name T76
Test name
Test status
Simulation time 81547021 ps
CPU time 1.16 seconds
Started Apr 25 04:03:08 PM PDT 24
Finished Apr 25 04:03:10 PM PDT 24
Peak memory 222648 kb
Host smart-317ad811-27f3-4412-8a81-c66989a40b08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2985333901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.2985333901 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.1135543843
Short name T83
Test name
Test status
Simulation time 58454147 ps
CPU time 1.03 seconds
Started Apr 25 04:03:08 PM PDT 24
Finished Apr 25 04:03:10 PM PDT 24
Peak memory 221420 kb
Host smart-830d31aa-6c31-4db8-a3cc-3790f6fb3354
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135543843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.1135543843 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.3433186933
Short name T820
Test name
Test status
Simulation time 26254550042 ps
CPU time 190.47 seconds
Started Apr 25 04:03:02 PM PDT 24
Finished Apr 25 04:06:13 PM PDT 24
Peak memory 242752 kb
Host smart-dd1db7d9-6838-4604-b88f-38962f97fe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433186933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3433186933 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.1663286788
Short name T959
Test name
Test status
Simulation time 18456977200 ps
CPU time 367.72 seconds
Started Apr 25 04:03:02 PM PDT 24
Finished Apr 25 04:09:10 PM PDT 24
Peak memory 259148 kb
Host smart-3cd308bb-aec3-4393-8dba-f27f9b61ae22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663286788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1663286788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.2419722888
Short name T558
Test name
Test status
Simulation time 2074648496 ps
CPU time 6.2 seconds
Started Apr 25 04:03:02 PM PDT 24
Finished Apr 25 04:03:09 PM PDT 24
Peak memory 218128 kb
Host smart-f18cd01a-8139-4ae5-9ce8-a08e975842fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419722888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2419722888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.4182602565
Short name T86
Test name
Test status
Simulation time 87612642 ps
CPU time 1.62 seconds
Started Apr 25 04:03:09 PM PDT 24
Finished Apr 25 04:03:11 PM PDT 24
Peak memory 218164 kb
Host smart-efa7f371-7f1f-48db-8274-72d333d3fcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182602565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4182602565 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.1341795446
Short name T21
Test name
Test status
Simulation time 2242374469275 ps
CPU time 3297.08 seconds
Started Apr 25 04:02:48 PM PDT 24
Finished Apr 25 04:57:46 PM PDT 24
Peak memory 483112 kb
Host smart-00ec6e8d-91ce-40ff-8b3f-23a0dfff0f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341795446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.1341795446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.914415151
Short name T495
Test name
Test status
Simulation time 16103756909 ps
CPU time 393.09 seconds
Started Apr 25 04:02:45 PM PDT 24
Finished Apr 25 04:09:18 PM PDT 24
Peak memory 248448 kb
Host smart-978ec205-553d-4705-a56d-5dc2271e3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914415151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.914415151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.411936972
Short name T366
Test name
Test status
Simulation time 2033277353 ps
CPU time 80.12 seconds
Started Apr 25 04:02:47 PM PDT 24
Finished Apr 25 04:04:08 PM PDT 24
Peak memory 221908 kb
Host smart-a768c2b1-37c4-4d29-87c0-17aefbc6c665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411936972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.411936972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.301254757
Short name T998
Test name
Test status
Simulation time 88743963143 ps
CPU time 1284.29 seconds
Started Apr 25 04:03:08 PM PDT 24
Finished Apr 25 04:24:33 PM PDT 24
Peak memory 319968 kb
Host smart-6a29c648-af7b-4cd3-83f9-892d8b5fec3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=301254757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.301254757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.999169479
Short name T653
Test name
Test status
Simulation time 432411022 ps
CPU time 6.06 seconds
Started Apr 25 04:03:01 PM PDT 24
Finished Apr 25 04:03:08 PM PDT 24
Peak memory 218312 kb
Host smart-d6a4b81f-af57-4a7a-9582-a4ccb87cd3c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999169479 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.999169479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.3472966782
Short name T192
Test name
Test status
Simulation time 266987286 ps
CPU time 6.59 seconds
Started Apr 25 04:03:00 PM PDT 24
Finished Apr 25 04:03:07 PM PDT 24
Peak memory 218280 kb
Host smart-ecc40463-830d-44c0-b5b7-ab774a2fc556
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472966782 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.3472966782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.3438822139
Short name T737
Test name
Test status
Simulation time 68154926510 ps
CPU time 2237.88 seconds
Started Apr 25 04:02:51 PM PDT 24
Finished Apr 25 04:40:10 PM PDT 24
Peak memory 391100 kb
Host smart-f211d9ed-37f4-4654-83da-adf1d01451ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3438822139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3438822139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.3494144099
Short name T234
Test name
Test status
Simulation time 19996301721 ps
CPU time 1919.93 seconds
Started Apr 25 04:02:53 PM PDT 24
Finished Apr 25 04:34:53 PM PDT 24
Peak memory 394088 kb
Host smart-0e66df02-8dea-49e7-a64c-b8ee0a01b45c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3494144099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.3494144099 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.2019719095
Short name T333
Test name
Test status
Simulation time 150986376110 ps
CPU time 1923.65 seconds
Started Apr 25 04:02:51 PM PDT 24
Finished Apr 25 04:34:55 PM PDT 24
Peak memory 341956 kb
Host smart-a128180c-b65d-4a86-9510-3b171ca97160
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2019719095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.2019719095 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.575701887
Short name T463
Test name
Test status
Simulation time 33330064276 ps
CPU time 1347.86 seconds
Started Apr 25 04:02:52 PM PDT 24
Finished Apr 25 04:25:21 PM PDT 24
Peak memory 298412 kb
Host smart-1057ec48-da01-4431-9b4d-e5e1d0fb4b16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=575701887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.575701887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.2401755014
Short name T835
Test name
Test status
Simulation time 1457966984645 ps
CPU time 5234.46 seconds
Started Apr 25 04:02:51 PM PDT 24
Finished Apr 25 05:30:07 PM PDT 24
Peak memory 639220 kb
Host smart-be6fbf23-309b-445d-83e5-2a93ef29e151
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2401755014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.2401755014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.2111810344
Short name T184
Test name
Test status
Simulation time 871415790946 ps
CPU time 5031.09 seconds
Started Apr 25 04:03:00 PM PDT 24
Finished Apr 25 05:26:52 PM PDT 24
Peak memory 562044 kb
Host smart-bcb3e548-b47b-4322-969c-6c4d5c7e558d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2111810344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.2111810344 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.3933106284
Short name T790
Test name
Test status
Simulation time 17318279 ps
CPU time 0.89 seconds
Started Apr 25 03:55:57 PM PDT 24
Finished Apr 25 03:55:59 PM PDT 24
Peak memory 217876 kb
Host smart-23c7c8ce-b7b8-4ccf-a176-84f69dd6262a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933106284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3933106284 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.2437282696
Short name T1047
Test name
Test status
Simulation time 17904697432 ps
CPU time 145.18 seconds
Started Apr 25 03:55:43 PM PDT 24
Finished Apr 25 03:58:09 PM PDT 24
Peak memory 235540 kb
Host smart-4894a457-de93-4466-b3ad-315f2e4cf2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437282696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.2437282696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.2505874290
Short name T613
Test name
Test status
Simulation time 15411498994 ps
CPU time 129.4 seconds
Started Apr 25 03:55:46 PM PDT 24
Finished Apr 25 03:57:56 PM PDT 24
Peak memory 234452 kb
Host smart-97a96a99-ca2b-47cb-9022-d2a5c3f65457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505874290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2505874290 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.4147391971
Short name T879
Test name
Test status
Simulation time 208882048 ps
CPU time 11.51 seconds
Started Apr 25 03:55:42 PM PDT 24
Finished Apr 25 03:55:54 PM PDT 24
Peak memory 223548 kb
Host smart-f643bffa-efcf-414e-8d8e-0a27e167ef53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147391971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.4147391971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2342898692
Short name T392
Test name
Test status
Simulation time 1590658011 ps
CPU time 23.14 seconds
Started Apr 25 03:55:47 PM PDT 24
Finished Apr 25 03:56:11 PM PDT 24
Peak memory 225040 kb
Host smart-614cefa2-0970-4eea-a107-8abf46d5ab8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2342898692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2342898692 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.3638772166
Short name T320
Test name
Test status
Simulation time 1353612221 ps
CPU time 39.54 seconds
Started Apr 25 03:55:52 PM PDT 24
Finished Apr 25 03:56:33 PM PDT 24
Peak memory 234368 kb
Host smart-0b3d7fc0-b810-4a60-8d83-8151e5bdb2ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638772166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3638772166 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.2596246863
Short name T751
Test name
Test status
Simulation time 4298284427 ps
CPU time 43.19 seconds
Started Apr 25 03:55:53 PM PDT 24
Finished Apr 25 03:56:37 PM PDT 24
Peak memory 218976 kb
Host smart-b9e4d9bb-aade-44a8-a511-89d0e2a9581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596246863 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2596246863 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.4026439662
Short name T992
Test name
Test status
Simulation time 2099698120 ps
CPU time 44.04 seconds
Started Apr 25 03:55:48 PM PDT 24
Finished Apr 25 03:56:32 PM PDT 24
Peak memory 225140 kb
Host smart-cab2dc84-d353-4dac-b5b7-0899be31459c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026439662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.4026439662 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/2.kmac_error.1046431904
Short name T416
Test name
Test status
Simulation time 56613687118 ps
CPU time 409.37 seconds
Started Apr 25 03:55:51 PM PDT 24
Finished Apr 25 04:02:41 PM PDT 24
Peak memory 259040 kb
Host smart-bde957d1-fb54-4d41-9a59-c46f98a18b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046431904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1046431904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.237798454
Short name T942
Test name
Test status
Simulation time 2118343750 ps
CPU time 6.95 seconds
Started Apr 25 03:55:47 PM PDT 24
Finished Apr 25 03:55:54 PM PDT 24
Peak memory 218144 kb
Host smart-a2a5b806-4c30-413d-8fdb-f92d9b68c3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237798454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.237798454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.2785809217
Short name T1048
Test name
Test status
Simulation time 81904645 ps
CPU time 1.38 seconds
Started Apr 25 03:55:52 PM PDT 24
Finished Apr 25 03:55:55 PM PDT 24
Peak memory 218172 kb
Host smart-f2ddf4de-cc0c-4f9b-ba14-d853c7d08f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785809217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2785809217 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.3398606048
Short name T651
Test name
Test status
Simulation time 110984170266 ps
CPU time 2824.96 seconds
Started Apr 25 03:55:40 PM PDT 24
Finished Apr 25 04:42:46 PM PDT 24
Peak memory 437316 kb
Host smart-9cb08a07-a223-41aa-8196-08ea7a10a9e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398606048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.3398606048 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.1202528576
Short name T10
Test name
Test status
Simulation time 17191198584 ps
CPU time 319.59 seconds
Started Apr 25 03:55:47 PM PDT 24
Finished Apr 25 04:01:07 PM PDT 24
Peak memory 249044 kb
Host smart-a0493fba-5c0a-4476-93be-4f14c2adc501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202528576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.1202528576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_smoke.2352971694
Short name T230
Test name
Test status
Simulation time 2460179282 ps
CPU time 58.15 seconds
Started Apr 25 03:55:43 PM PDT 24
Finished Apr 25 03:56:41 PM PDT 24
Peak memory 226344 kb
Host smart-2b624b44-9ed6-476f-b4f8-ec14a40a753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352971694 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2352971694 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.4095605235
Short name T939
Test name
Test status
Simulation time 10390677384 ps
CPU time 150.07 seconds
Started Apr 25 03:55:52 PM PDT 24
Finished Apr 25 03:58:24 PM PDT 24
Peak memory 245956 kb
Host smart-d08a0bfc-d839-4f10-9ea3-5f9d41f45af7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4095605235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.4095605235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.970812811
Short name T218
Test name
Test status
Simulation time 240462998 ps
CPU time 7.03 seconds
Started Apr 25 03:55:45 PM PDT 24
Finished Apr 25 03:55:53 PM PDT 24
Peak memory 218176 kb
Host smart-39dc5229-1df3-4049-99d5-d12f59ff0c21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970812811 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.970812811 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3250151622
Short name T307
Test name
Test status
Simulation time 247305511 ps
CPU time 7.31 seconds
Started Apr 25 03:55:45 PM PDT 24
Finished Apr 25 03:55:52 PM PDT 24
Peak memory 219116 kb
Host smart-d43e7f52-f627-4302-927c-1cbce559f779
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250151622 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3250151622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.118679798
Short name T921
Test name
Test status
Simulation time 99509622966 ps
CPU time 2392 seconds
Started Apr 25 03:55:43 PM PDT 24
Finished Apr 25 04:35:36 PM PDT 24
Peak memory 404656 kb
Host smart-79e5a161-e86a-460c-819c-dea1b43e95b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=118679798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.118679798 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.1779039223
Short name T417
Test name
Test status
Simulation time 109792750895 ps
CPU time 2017.63 seconds
Started Apr 25 03:55:41 PM PDT 24
Finished Apr 25 04:29:19 PM PDT 24
Peak memory 373380 kb
Host smart-7f593dae-6de7-4245-8ed8-12b039dd4899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1779039223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.1779039223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.1348206840
Short name T328
Test name
Test status
Simulation time 48912295689 ps
CPU time 1707.25 seconds
Started Apr 25 03:55:41 PM PDT 24
Finished Apr 25 04:24:09 PM PDT 24
Peak memory 342092 kb
Host smart-4514bf4a-e615-43a2-9cc1-32d8ceda9f5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1348206840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.1348206840 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1127729279
Short name T447
Test name
Test status
Simulation time 273180303098 ps
CPU time 1348.71 seconds
Started Apr 25 03:55:42 PM PDT 24
Finished Apr 25 04:18:12 PM PDT 24
Peak memory 296464 kb
Host smart-0f433ce8-db1a-41f2-bd59-28d41401f275
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1127729279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1127729279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.4186163493
Short name T1057
Test name
Test status
Simulation time 198503519870 ps
CPU time 5474.94 seconds
Started Apr 25 03:55:42 PM PDT 24
Finished Apr 25 05:26:59 PM PDT 24
Peak memory 658780 kb
Host smart-f8013428-0d57-4621-8820-0eabf579bf2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4186163493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.4186163493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.2184178031
Short name T206
Test name
Test status
Simulation time 54343623786 ps
CPU time 4631.19 seconds
Started Apr 25 03:55:43 PM PDT 24
Finished Apr 25 05:12:55 PM PDT 24
Peak memory 558552 kb
Host smart-36c6ceaf-41dd-4fcc-be44-f42592d9232d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2184178031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.2184178031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1018397303
Short name T418
Test name
Test status
Simulation time 17012635 ps
CPU time 0.88 seconds
Started Apr 25 04:03:30 PM PDT 24
Finished Apr 25 04:03:31 PM PDT 24
Peak memory 217900 kb
Host smart-6a8168a9-c2fd-4a34-9685-7b4f45ef2977
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018397303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1018397303 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.4280377916
Short name T713
Test name
Test status
Simulation time 9734724599 ps
CPU time 176.53 seconds
Started Apr 25 04:03:25 PM PDT 24
Finished Apr 25 04:06:22 PM PDT 24
Peak memory 238276 kb
Host smart-9fa2c375-889a-4cbd-9af2-7f9dda90cbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280377916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.4280377916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.2295706236
Short name T995
Test name
Test status
Simulation time 9050849020 ps
CPU time 323.26 seconds
Started Apr 25 04:03:14 PM PDT 24
Finished Apr 25 04:08:38 PM PDT 24
Peak memory 238276 kb
Host smart-9e0219b4-ad76-4c44-be2f-6cbb2dc3b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295706236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.2295706236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.4111896725
Short name T61
Test name
Test status
Simulation time 16579871090 ps
CPU time 174.95 seconds
Started Apr 25 04:03:24 PM PDT 24
Finished Apr 25 04:06:20 PM PDT 24
Peak memory 238400 kb
Host smart-73d51eb9-6d24-4b01-9f42-3b35b33447ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111896725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.4111896725 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.1579823698
Short name T462
Test name
Test status
Simulation time 1304552002 ps
CPU time 34.32 seconds
Started Apr 25 04:03:24 PM PDT 24
Finished Apr 25 04:03:59 PM PDT 24
Peak memory 240708 kb
Host smart-0714fe85-f049-4d93-bef9-542d75b2349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579823698 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.1579823698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.479928660
Short name T852
Test name
Test status
Simulation time 2084596808 ps
CPU time 1.98 seconds
Started Apr 25 04:03:24 PM PDT 24
Finished Apr 25 04:03:27 PM PDT 24
Peak memory 218092 kb
Host smart-2426632b-0a26-4ede-b018-24e560585998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479928660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.479928660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1096759660
Short name T232
Test name
Test status
Simulation time 64458171253 ps
CPU time 1808.29 seconds
Started Apr 25 04:03:17 PM PDT 24
Finished Apr 25 04:33:26 PM PDT 24
Peak memory 351384 kb
Host smart-cae2ae9d-488b-45d8-a09a-b743ded33f5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096759660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1096759660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.1694586782
Short name T478
Test name
Test status
Simulation time 348030728 ps
CPU time 15.5 seconds
Started Apr 25 04:03:16 PM PDT 24
Finished Apr 25 04:03:32 PM PDT 24
Peak memory 234140 kb
Host smart-54d862c2-d1b3-4210-8180-4dd5db80bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694586782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1694586782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.3819756951
Short name T188
Test name
Test status
Simulation time 7279504079 ps
CPU time 82.07 seconds
Started Apr 25 04:03:13 PM PDT 24
Finished Apr 25 04:04:36 PM PDT 24
Peak memory 218276 kb
Host smart-738e3478-c7a9-484e-b386-9c3ee20af323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819756951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.3819756951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2426661569
Short name T655
Test name
Test status
Simulation time 10166586248 ps
CPU time 154.67 seconds
Started Apr 25 04:03:26 PM PDT 24
Finished Apr 25 04:06:01 PM PDT 24
Peak memory 251280 kb
Host smart-44e1f935-06aa-4b56-ac87-ed012f819d1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2426661569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2426661569 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.3683865616
Short name T326
Test name
Test status
Simulation time 1000062430 ps
CPU time 6.54 seconds
Started Apr 25 04:03:19 PM PDT 24
Finished Apr 25 04:03:27 PM PDT 24
Peak memory 218132 kb
Host smart-7a718d3d-bed7-4b96-88bd-bb8a260c2b3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683865616 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.kmac_test_vectors_kmac.3683865616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.4028160818
Short name T53
Test name
Test status
Simulation time 170608068 ps
CPU time 6.61 seconds
Started Apr 25 04:03:24 PM PDT 24
Finished Apr 25 04:03:31 PM PDT 24
Peak memory 218248 kb
Host smart-d28959fc-f428-4cbb-9018-6f2c36382478
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028160818 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.kmac_test_vectors_kmac_xof.4028160818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.2470215232
Short name T202
Test name
Test status
Simulation time 80112472441 ps
CPU time 2085.08 seconds
Started Apr 25 04:03:14 PM PDT 24
Finished Apr 25 04:38:00 PM PDT 24
Peak memory 394400 kb
Host smart-1ed4fd6a-acc7-4896-b189-8c313fd0d630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2470215232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.2470215232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.507742903
Short name T12
Test name
Test status
Simulation time 93408817122 ps
CPU time 2051.32 seconds
Started Apr 25 04:03:20 PM PDT 24
Finished Apr 25 04:37:32 PM PDT 24
Peak memory 387932 kb
Host smart-4bfb5cd0-8d66-446e-b286-06f3cf1be330
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=507742903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.507742903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.3121194690
Short name T594
Test name
Test status
Simulation time 79980903694 ps
CPU time 1622.28 seconds
Started Apr 25 04:03:19 PM PDT 24
Finished Apr 25 04:30:23 PM PDT 24
Peak memory 336780 kb
Host smart-27ce0499-7e91-4cca-925e-c2d9493761f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3121194690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.3121194690 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.3557862825
Short name T671
Test name
Test status
Simulation time 11053382672 ps
CPU time 1267.46 seconds
Started Apr 25 04:03:19 PM PDT 24
Finished Apr 25 04:24:28 PM PDT 24
Peak memory 301552 kb
Host smart-97d912bc-2c86-4e71-8990-f053facd9a23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3557862825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.3557862825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.1818545379
Short name T140
Test name
Test status
Simulation time 63987865545 ps
CPU time 4793.11 seconds
Started Apr 25 04:03:18 PM PDT 24
Finished Apr 25 05:23:12 PM PDT 24
Peak memory 665412 kb
Host smart-e45f172e-b241-4238-8bc9-e8f7cf5e9e13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1818545379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.1818545379 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.2647143494
Short name T969
Test name
Test status
Simulation time 104905657097 ps
CPU time 4462.88 seconds
Started Apr 25 04:03:20 PM PDT 24
Finished Apr 25 05:17:45 PM PDT 24
Peak memory 570268 kb
Host smart-4f12d060-61f6-4172-8487-1cb913a81702
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2647143494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2647143494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.2599985
Short name T947
Test name
Test status
Simulation time 31846285 ps
CPU time 0.93 seconds
Started Apr 25 04:03:51 PM PDT 24
Finished Apr 25 04:03:53 PM PDT 24
Peak memory 217872 kb
Host smart-d471bbd1-0672-44ac-a261-71e63490061a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.2599985 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_app.4020776802
Short name T672
Test name
Test status
Simulation time 1980598400 ps
CPU time 116.49 seconds
Started Apr 25 04:03:46 PM PDT 24
Finished Apr 25 04:05:44 PM PDT 24
Peak memory 233692 kb
Host smart-f9292045-273e-4325-b6be-ce5bd3905204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020776802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.4020776802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/default/21.kmac_burst_write.1729314558
Short name T724
Test name
Test status
Simulation time 195977717027 ps
CPU time 647.77 seconds
Started Apr 25 04:03:41 PM PDT 24
Finished Apr 25 04:14:29 PM PDT 24
Peak memory 242572 kb
Host smart-f8404003-dbbc-4338-8b61-add19a9e925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729314558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.1729314558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.425183840
Short name T310
Test name
Test status
Simulation time 36221914406 ps
CPU time 292.85 seconds
Started Apr 25 04:03:47 PM PDT 24
Finished Apr 25 04:08:41 PM PDT 24
Peak memory 244064 kb
Host smart-87658e02-b588-45cf-ac61-3135edcf8c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425183840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.425183840 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.1420386269
Short name T538
Test name
Test status
Simulation time 368542040 ps
CPU time 9.09 seconds
Started Apr 25 04:03:50 PM PDT 24
Finished Apr 25 04:04:00 PM PDT 24
Peak memory 226296 kb
Host smart-d83087d2-0ced-4e08-951b-a909e45c17fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420386269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1420386269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.3506902970
Short name T665
Test name
Test status
Simulation time 4042758861 ps
CPU time 5.81 seconds
Started Apr 25 04:03:47 PM PDT 24
Finished Apr 25 04:03:53 PM PDT 24
Peak memory 218200 kb
Host smart-bb0a188c-7d22-4508-a5f9-538ade4988f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506902970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.3506902970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.2152643999
Short name T489
Test name
Test status
Simulation time 34209061 ps
CPU time 1.36 seconds
Started Apr 25 04:03:48 PM PDT 24
Finished Apr 25 04:03:51 PM PDT 24
Peak memory 218216 kb
Host smart-5ffcc8d4-25cd-4ed5-a2df-627e46705e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152643999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.2152643999 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.1095598314
Short name T608
Test name
Test status
Simulation time 88024400069 ps
CPU time 1621.72 seconds
Started Apr 25 04:03:34 PM PDT 24
Finished Apr 25 04:30:37 PM PDT 24
Peak memory 349208 kb
Host smart-68bef67d-d2d6-4efe-878b-ef77a72aa6ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095598314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.1095598314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2179309327
Short name T678
Test name
Test status
Simulation time 9602863142 ps
CPU time 305.66 seconds
Started Apr 25 04:03:36 PM PDT 24
Finished Apr 25 04:08:42 PM PDT 24
Peak memory 244800 kb
Host smart-91021833-868f-48fc-9434-b6b6537a8d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179309327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2179309327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2710030653
Short name T923
Test name
Test status
Simulation time 4561764372 ps
CPU time 28.78 seconds
Started Apr 25 04:03:29 PM PDT 24
Finished Apr 25 04:03:59 PM PDT 24
Peak memory 223192 kb
Host smart-cf27674a-d465-481e-a3ce-719101faf9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710030653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2710030653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.4102298084
Short name T493
Test name
Test status
Simulation time 106284727397 ps
CPU time 2045.03 seconds
Started Apr 25 04:03:51 PM PDT 24
Finished Apr 25 04:37:58 PM PDT 24
Peak memory 431480 kb
Host smart-4a375901-8e78-4cb7-8b2f-ff4cee760f4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4102298084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.4102298084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.3206677007
Short name T205
Test name
Test status
Simulation time 509087556 ps
CPU time 6.41 seconds
Started Apr 25 04:03:48 PM PDT 24
Finished Apr 25 04:03:56 PM PDT 24
Peak memory 218256 kb
Host smart-b4d0c783-b3af-4483-9e79-0203e2798a16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206677007 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.3206677007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.1086370787
Short name T253
Test name
Test status
Simulation time 246083211 ps
CPU time 6.54 seconds
Started Apr 25 04:03:46 PM PDT 24
Finished Apr 25 04:03:53 PM PDT 24
Peak memory 218268 kb
Host smart-2b242d5b-bbf6-4b2a-8e84-cf817f0efcf9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086370787 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.kmac_test_vectors_kmac_xof.1086370787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.3106113371
Short name T516
Test name
Test status
Simulation time 84244731408 ps
CPU time 2112.34 seconds
Started Apr 25 04:03:41 PM PDT 24
Finished Apr 25 04:38:54 PM PDT 24
Peak memory 398300 kb
Host smart-5a48e633-dbc7-43ab-88cf-005a7e8b2ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3106113371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.3106113371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.3255454808
Short name T764
Test name
Test status
Simulation time 378857504583 ps
CPU time 2171.64 seconds
Started Apr 25 04:03:42 PM PDT 24
Finished Apr 25 04:39:54 PM PDT 24
Peak memory 384060 kb
Host smart-ca3bedd7-2f66-4b23-aef0-dda4b4b7114d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3255454808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3255454808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3611953377
Short name T380
Test name
Test status
Simulation time 16488216338 ps
CPU time 1523.69 seconds
Started Apr 25 04:03:46 PM PDT 24
Finished Apr 25 04:29:11 PM PDT 24
Peak memory 342468 kb
Host smart-6e3a949e-d03e-4f76-93a7-433af518720c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3611953377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3611953377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.58972486
Short name T564
Test name
Test status
Simulation time 34026474569 ps
CPU time 1250.85 seconds
Started Apr 25 04:03:46 PM PDT 24
Finished Apr 25 04:24:38 PM PDT 24
Peak memory 300884 kb
Host smart-c24c26cf-0d75-4421-a362-937ffa0cfcd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=58972486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.58972486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.2446981184
Short name T472
Test name
Test status
Simulation time 937346020904 ps
CPU time 5568.09 seconds
Started Apr 25 04:03:45 PM PDT 24
Finished Apr 25 05:36:35 PM PDT 24
Peak memory 651268 kb
Host smart-9f6cfc03-712c-425a-8d49-9abd81a30115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2446981184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.2446981184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3879151558
Short name T765
Test name
Test status
Simulation time 984479186504 ps
CPU time 4704.85 seconds
Started Apr 25 04:03:45 PM PDT 24
Finished Apr 25 05:22:11 PM PDT 24
Peak memory 569020 kb
Host smart-49b44038-d647-4546-b31e-a944c71d84f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3879151558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3879151558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.3479886112
Short name T741
Test name
Test status
Simulation time 282013309 ps
CPU time 0.87 seconds
Started Apr 25 04:04:12 PM PDT 24
Finished Apr 25 04:04:14 PM PDT 24
Peak memory 217912 kb
Host smart-6f674456-2d9b-41f6-99f8-940bc8645dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479886112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.3479886112 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.3727859994
Short name T339
Test name
Test status
Simulation time 93348179086 ps
CPU time 351.18 seconds
Started Apr 25 04:04:03 PM PDT 24
Finished Apr 25 04:09:56 PM PDT 24
Peak memory 248624 kb
Host smart-9c963c7b-33b4-4ffe-8b2d-cf184f3ebeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727859994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.3727859994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.1703790178
Short name T265
Test name
Test status
Simulation time 8882885736 ps
CPU time 913.31 seconds
Started Apr 25 04:04:05 PM PDT 24
Finished Apr 25 04:19:19 PM PDT 24
Peak memory 235064 kb
Host smart-6e973aa0-b30b-4363-86e5-5438613b18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703790178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.1703790178 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.3933006940
Short name T812
Test name
Test status
Simulation time 22438488737 ps
CPU time 161.99 seconds
Started Apr 25 04:04:03 PM PDT 24
Finished Apr 25 04:06:47 PM PDT 24
Peak memory 237388 kb
Host smart-2fb66960-a176-4770-957e-bfd936491302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933006940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3933006940 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.1969505518
Short name T321
Test name
Test status
Simulation time 5796217039 ps
CPU time 154.75 seconds
Started Apr 25 04:04:02 PM PDT 24
Finished Apr 25 04:06:38 PM PDT 24
Peak memory 243724 kb
Host smart-55053bc5-a9d8-4739-b713-e0bbaf8fa2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969505518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.1969505518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.3320446969
Short name T109
Test name
Test status
Simulation time 16711020243 ps
CPU time 6.89 seconds
Started Apr 25 04:04:05 PM PDT 24
Finished Apr 25 04:04:12 PM PDT 24
Peak memory 218180 kb
Host smart-92c6c7e1-a150-47a7-abb9-e760f3130afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320446969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.3320446969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2271838420
Short name T28
Test name
Test status
Simulation time 125307590 ps
CPU time 1.25 seconds
Started Apr 25 04:04:04 PM PDT 24
Finished Apr 25 04:04:06 PM PDT 24
Peak memory 218204 kb
Host smart-7576939b-4b69-4499-aa63-2aba1c97148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271838420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2271838420 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.2670401640
Short name T719
Test name
Test status
Simulation time 4523291025 ps
CPU time 163.36 seconds
Started Apr 25 04:03:52 PM PDT 24
Finished Apr 25 04:06:37 PM PDT 24
Peak memory 242708 kb
Host smart-e0fd9661-f85f-4de5-9806-eeaab228f2d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670401640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.2670401640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.2137668289
Short name T691
Test name
Test status
Simulation time 101367565229 ps
CPU time 395.82 seconds
Started Apr 25 04:03:57 PM PDT 24
Finished Apr 25 04:10:34 PM PDT 24
Peak memory 248516 kb
Host smart-95111d5b-55e8-4b43-85e9-5ee07bb9df26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137668289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.2137668289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.182010110
Short name T273
Test name
Test status
Simulation time 1718982258 ps
CPU time 11.82 seconds
Started Apr 25 04:03:51 PM PDT 24
Finished Apr 25 04:04:05 PM PDT 24
Peak memory 226144 kb
Host smart-f037aaca-8fc4-4660-bbae-8afe6e8b155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182010110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.182010110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.601586070
Short name T511
Test name
Test status
Simulation time 11577278605 ps
CPU time 317.56 seconds
Started Apr 25 04:04:02 PM PDT 24
Finished Apr 25 04:09:22 PM PDT 24
Peak memory 267656 kb
Host smart-14113ae9-2e4c-4cdf-9440-34ec85d30bc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=601586070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.601586070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.1936992387
Short name T912
Test name
Test status
Simulation time 247550032 ps
CPU time 6.63 seconds
Started Apr 25 04:04:02 PM PDT 24
Finished Apr 25 04:04:10 PM PDT 24
Peak memory 218224 kb
Host smart-cdb934c6-57b9-4f3e-bba4-4eb621aaff1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936992387 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.1936992387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.2223610955
Short name T838
Test name
Test status
Simulation time 163701286 ps
CPU time 5.79 seconds
Started Apr 25 04:04:02 PM PDT 24
Finished Apr 25 04:04:09 PM PDT 24
Peak memory 218152 kb
Host smart-50c4c6c4-94af-412f-b320-0be4cf279d67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223610955 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.2223610955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.3021460058
Short name T1008
Test name
Test status
Simulation time 165452082768 ps
CPU time 2377.12 seconds
Started Apr 25 04:03:58 PM PDT 24
Finished Apr 25 04:43:37 PM PDT 24
Peak memory 399244 kb
Host smart-e3336d27-30a1-4158-98e7-5e274934c752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3021460058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.3021460058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.704627612
Short name T712
Test name
Test status
Simulation time 91767060868 ps
CPU time 2063.57 seconds
Started Apr 25 04:03:59 PM PDT 24
Finished Apr 25 04:38:24 PM PDT 24
Peak memory 387516 kb
Host smart-862b4cc6-295e-4770-a3f1-f6d1e8f9e1d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=704627612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.704627612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.3429017754
Short name T688
Test name
Test status
Simulation time 78869233078 ps
CPU time 1759.29 seconds
Started Apr 25 04:03:57 PM PDT 24
Finished Apr 25 04:33:17 PM PDT 24
Peak memory 342292 kb
Host smart-c39622aa-09f7-4491-95cf-cd8475ecc224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3429017754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.3429017754 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.4288147876
Short name T1024
Test name
Test status
Simulation time 48224547502 ps
CPU time 1177.32 seconds
Started Apr 25 04:03:58 PM PDT 24
Finished Apr 25 04:23:37 PM PDT 24
Peak memory 297320 kb
Host smart-fe042d7f-a359-470c-8e35-254e7a18f3ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4288147876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.4288147876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1180613024
Short name T569
Test name
Test status
Simulation time 1070206757742 ps
CPU time 4890.03 seconds
Started Apr 25 04:03:58 PM PDT 24
Finished Apr 25 05:25:30 PM PDT 24
Peak memory 675156 kb
Host smart-ddc2f2d9-4513-4944-9ffa-fd4db758dc24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1180613024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1180613024 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1273901030
Short name T769
Test name
Test status
Simulation time 63907883427 ps
CPU time 3977.3 seconds
Started Apr 25 04:03:57 PM PDT 24
Finished Apr 25 05:10:16 PM PDT 24
Peak memory 564604 kb
Host smart-99786b25-21e0-45a8-84cb-c5cde9891c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1273901030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1273901030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.2755190262
Short name T11
Test name
Test status
Simulation time 19958450 ps
CPU time 0.91 seconds
Started Apr 25 04:04:32 PM PDT 24
Finished Apr 25 04:04:33 PM PDT 24
Peak memory 217872 kb
Host smart-2f0f0261-0dd1-4dca-8e8e-e92d9c9c04ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755190262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.2755190262 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.1028828860
Short name T588
Test name
Test status
Simulation time 8957523147 ps
CPU time 133.72 seconds
Started Apr 25 04:04:20 PM PDT 24
Finished Apr 25 04:06:34 PM PDT 24
Peak memory 234432 kb
Host smart-1eecfcb8-6c59-4398-97cb-54e3a8d5b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028828860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1028828860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.1745135142
Short name T525
Test name
Test status
Simulation time 11883829053 ps
CPU time 1185.46 seconds
Started Apr 25 04:04:09 PM PDT 24
Finished Apr 25 04:23:56 PM PDT 24
Peak memory 236696 kb
Host smart-a29830c8-8ecd-4e6f-a5f5-1af53a06c652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745135142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.1745135142 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.1518470012
Short name T256
Test name
Test status
Simulation time 1770313344 ps
CPU time 63.43 seconds
Started Apr 25 04:04:25 PM PDT 24
Finished Apr 25 04:05:29 PM PDT 24
Peak memory 237404 kb
Host smart-cd57eb5d-e6ef-4bd7-b09e-5916ee186c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518470012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1518470012 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3553541504
Short name T182
Test name
Test status
Simulation time 1939539603 ps
CPU time 52.09 seconds
Started Apr 25 04:04:26 PM PDT 24
Finished Apr 25 04:05:19 PM PDT 24
Peak memory 242600 kb
Host smart-6be29bf6-e91b-42cf-8b2f-803d0395fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553541504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3553541504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.1687814879
Short name T270
Test name
Test status
Simulation time 332134509 ps
CPU time 1.99 seconds
Started Apr 25 04:04:25 PM PDT 24
Finished Apr 25 04:04:28 PM PDT 24
Peak memory 218116 kb
Host smart-06ed19fc-d694-4f3a-b413-2859a036987e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687814879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.1687814879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.2895841574
Short name T952
Test name
Test status
Simulation time 66946506536 ps
CPU time 1812.6 seconds
Started Apr 25 04:04:08 PM PDT 24
Finished Apr 25 04:34:23 PM PDT 24
Peak memory 347600 kb
Host smart-98ba4d97-2b7f-4a0a-ba60-2f63f513f9ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895841574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a
nd_output.2895841574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2740076805
Short name T317
Test name
Test status
Simulation time 68940127485 ps
CPU time 433.8 seconds
Started Apr 25 04:04:09 PM PDT 24
Finished Apr 25 04:11:24 PM PDT 24
Peak memory 252584 kb
Host smart-486c7b13-95cc-42b6-b87d-4c71ea419b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740076805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2740076805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.2789041005
Short name T710
Test name
Test status
Simulation time 1396682669 ps
CPU time 30.55 seconds
Started Apr 25 04:04:08 PM PDT 24
Finished Apr 25 04:04:40 PM PDT 24
Peak memory 226096 kb
Host smart-8aada0a5-657f-4953-9221-ba8b235a1407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789041005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.2789041005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.3588974310
Short name T170
Test name
Test status
Simulation time 113229852241 ps
CPU time 211.26 seconds
Started Apr 25 04:04:24 PM PDT 24
Finished Apr 25 04:07:56 PM PDT 24
Peak memory 255604 kb
Host smart-d3ab132a-9fc4-4cd6-9f85-8c3eed96b90d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3588974310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.3588974310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.3873950080
Short name T381
Test name
Test status
Simulation time 194764076 ps
CPU time 6.35 seconds
Started Apr 25 04:04:20 PM PDT 24
Finished Apr 25 04:04:26 PM PDT 24
Peak memory 218152 kb
Host smart-992eb1cd-38f3-45f9-9c44-4b757396c594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873950080 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.3873950080 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.3782007433
Short name T52
Test name
Test status
Simulation time 214255276 ps
CPU time 6.78 seconds
Started Apr 25 04:04:20 PM PDT 24
Finished Apr 25 04:04:27 PM PDT 24
Peak memory 218280 kb
Host smart-0a49ec95-f409-4b2b-b865-d07b9cac3a13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782007433 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.3782007433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.2853517604
Short name T296
Test name
Test status
Simulation time 416300299863 ps
CPU time 2370.11 seconds
Started Apr 25 04:04:08 PM PDT 24
Finished Apr 25 04:43:40 PM PDT 24
Peak memory 407772 kb
Host smart-b05fb4b1-c0c6-47cb-8949-39242dd7115c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2853517604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2853517604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.3805440288
Short name T385
Test name
Test status
Simulation time 57316479982 ps
CPU time 1838.13 seconds
Started Apr 25 04:04:13 PM PDT 24
Finished Apr 25 04:34:53 PM PDT 24
Peak memory 383092 kb
Host smart-c2a29414-9ced-4aaa-9e7a-9367c255def5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3805440288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3805440288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.2994396335
Short name T223
Test name
Test status
Simulation time 15261633616 ps
CPU time 1743.43 seconds
Started Apr 25 04:04:16 PM PDT 24
Finished Apr 25 04:33:20 PM PDT 24
Peak memory 342924 kb
Host smart-7ae13896-85cd-4917-9af6-cbc87b357176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2994396335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.2994396335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.1693444908
Short name T189
Test name
Test status
Simulation time 57469890363 ps
CPU time 1322.72 seconds
Started Apr 25 04:04:15 PM PDT 24
Finished Apr 25 04:26:19 PM PDT 24
Peak memory 304320 kb
Host smart-6b7f0f52-24ef-4a52-a71b-52cc22267863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1693444908 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.1693444908 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.2839624135
Short name T279
Test name
Test status
Simulation time 357764956482 ps
CPU time 5061.56 seconds
Started Apr 25 04:04:16 PM PDT 24
Finished Apr 25 05:28:39 PM PDT 24
Peak memory 642360 kb
Host smart-f9c4f17a-1ca0-4358-90ae-be04c486d1c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2839624135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.2839624135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.3934396446
Short name T881
Test name
Test status
Simulation time 599442041343 ps
CPU time 4794.14 seconds
Started Apr 25 04:04:20 PM PDT 24
Finished Apr 25 05:24:15 PM PDT 24
Peak memory 563668 kb
Host smart-976f41c5-0e16-4f58-a7c1-5e3754292021
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3934396446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3934396446 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.2996248567
Short name T883
Test name
Test status
Simulation time 29302249 ps
CPU time 0.76 seconds
Started Apr 25 04:04:47 PM PDT 24
Finished Apr 25 04:04:48 PM PDT 24
Peak memory 217892 kb
Host smart-5db4b06e-8685-40b8-a4c0-e29d81cc2e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996248567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.2996248567 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.3226352430
Short name T329
Test name
Test status
Simulation time 12861407324 ps
CPU time 198.71 seconds
Started Apr 25 04:04:42 PM PDT 24
Finished Apr 25 04:08:01 PM PDT 24
Peak memory 240980 kb
Host smart-a8182fc6-8001-4248-b905-909e347cc22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226352430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3226352430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.3425808103
Short name T637
Test name
Test status
Simulation time 80038737270 ps
CPU time 948.41 seconds
Started Apr 25 04:04:30 PM PDT 24
Finished Apr 25 04:20:19 PM PDT 24
Peak memory 242732 kb
Host smart-b20e19a9-f99e-4f85-b8b2-799cfc976d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425808103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3425808103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_error.1313547640
Short name T362
Test name
Test status
Simulation time 16900491365 ps
CPU time 343.93 seconds
Started Apr 25 04:04:41 PM PDT 24
Finished Apr 25 04:10:26 PM PDT 24
Peak memory 259112 kb
Host smart-1bc13cd7-1710-4bd6-bca0-10a26fd294b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313547640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.1313547640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.1040477205
Short name T106
Test name
Test status
Simulation time 6442125429 ps
CPU time 3.76 seconds
Started Apr 25 04:04:42 PM PDT 24
Finished Apr 25 04:04:46 PM PDT 24
Peak memory 218160 kb
Host smart-4caff238-ffac-466a-ac7d-ac404bbb343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040477205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.1040477205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.1574044780
Short name T67
Test name
Test status
Simulation time 46898879 ps
CPU time 1.25 seconds
Started Apr 25 04:04:39 PM PDT 24
Finished Apr 25 04:04:40 PM PDT 24
Peak memory 218204 kb
Host smart-0823ebcc-ccc3-44ca-9dd0-d4b1cf4954be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574044780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.1574044780 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.3922073459
Short name T512
Test name
Test status
Simulation time 5895691729 ps
CPU time 156.22 seconds
Started Apr 25 04:04:31 PM PDT 24
Finished Apr 25 04:07:08 PM PDT 24
Peak memory 242624 kb
Host smart-0377f0d0-603a-4bad-8fac-c9820a337873
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922073459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a
nd_output.3922073459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2885537165
Short name T1011
Test name
Test status
Simulation time 37047363779 ps
CPU time 283.45 seconds
Started Apr 25 04:04:30 PM PDT 24
Finished Apr 25 04:09:15 PM PDT 24
Peak memory 242592 kb
Host smart-e9e228d2-1c68-4ee0-a785-f2bf92c131db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885537165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2885537165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.1679014651
Short name T338
Test name
Test status
Simulation time 444991404 ps
CPU time 11.2 seconds
Started Apr 25 04:04:30 PM PDT 24
Finished Apr 25 04:04:42 PM PDT 24
Peak memory 226136 kb
Host smart-1df42b84-5db5-4b57-b3a7-1641e77a3d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679014651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.1679014651 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.2416369788
Short name T906
Test name
Test status
Simulation time 55534648473 ps
CPU time 476.83 seconds
Started Apr 25 04:04:42 PM PDT 24
Finished Apr 25 04:12:40 PM PDT 24
Peak memory 283708 kb
Host smart-bcb8a1f6-7a10-44a4-9614-2afdbe85b81d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2416369788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.2416369788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_stress_all_with_rand_reset.1086694732
Short name T996
Test name
Test status
Simulation time 189227543967 ps
CPU time 5576.13 seconds
Started Apr 25 04:04:40 PM PDT 24
Finished Apr 25 05:37:37 PM PDT 24
Peak memory 676380 kb
Host smart-d3ca1b20-f0c7-47f3-908f-bf2d05cf6ec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086694732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all_with_rand_reset.1086694732 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.3438879317
Short name T2
Test name
Test status
Simulation time 717339806 ps
CPU time 6.66 seconds
Started Apr 25 04:04:35 PM PDT 24
Finished Apr 25 04:04:43 PM PDT 24
Peak memory 218192 kb
Host smart-f4f33f22-2f1f-494c-9dc2-8f3c142407f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438879317 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.3438879317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.3316273070
Short name T787
Test name
Test status
Simulation time 206781403 ps
CPU time 6.52 seconds
Started Apr 25 04:04:35 PM PDT 24
Finished Apr 25 04:04:42 PM PDT 24
Peak memory 218232 kb
Host smart-37404024-a373-44cb-9619-cafa674f8ee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316273070 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.kmac_test_vectors_kmac_xof.3316273070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2395910493
Short name T987
Test name
Test status
Simulation time 142702109156 ps
CPU time 2239.36 seconds
Started Apr 25 04:04:31 PM PDT 24
Finished Apr 25 04:41:51 PM PDT 24
Peak memory 398780 kb
Host smart-b90ef9a4-8c40-4988-ac39-04ef82036a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2395910493 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2395910493 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_256.2859788262
Short name T246
Test name
Test status
Simulation time 100807147066 ps
CPU time 1938.64 seconds
Started Apr 25 04:04:31 PM PDT 24
Finished Apr 25 04:36:50 PM PDT 24
Peak memory 387120 kb
Host smart-ca2f8415-f70b-4b2f-ac17-4e0997fce8c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2859788262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.2859788262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.3910252139
Short name T619
Test name
Test status
Simulation time 15225675404 ps
CPU time 1561.98 seconds
Started Apr 25 04:04:35 PM PDT 24
Finished Apr 25 04:30:38 PM PDT 24
Peak memory 336632 kb
Host smart-d1282c3a-086b-4a83-81c7-ebceeb94a9a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3910252139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.3910252139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.2640512674
Short name T545
Test name
Test status
Simulation time 53563090063 ps
CPU time 1314.78 seconds
Started Apr 25 04:04:35 PM PDT 24
Finished Apr 25 04:26:31 PM PDT 24
Peak memory 302504 kb
Host smart-384a79e4-857b-4440-bee6-51ad508c466b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2640512674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.2640512674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3002578626
Short name T468
Test name
Test status
Simulation time 251263607618 ps
CPU time 5278.21 seconds
Started Apr 25 04:04:37 PM PDT 24
Finished Apr 25 05:32:37 PM PDT 24
Peak memory 665652 kb
Host smart-1d591259-a977-4b48-849f-8ddb177c58e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3002578626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3002578626 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1827835252
Short name T905
Test name
Test status
Simulation time 215386570180 ps
CPU time 4718.48 seconds
Started Apr 25 04:04:34 PM PDT 24
Finished Apr 25 05:23:13 PM PDT 24
Peak memory 556608 kb
Host smart-0b087bd6-2dce-4c60-9bb4-dd647af47541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1827835252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1827835252 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1022299759
Short name T1069
Test name
Test status
Simulation time 39405473 ps
CPU time 0.88 seconds
Started Apr 25 04:04:58 PM PDT 24
Finished Apr 25 04:04:59 PM PDT 24
Peak memory 217872 kb
Host smart-9bf3ab15-56fa-44dc-adda-42bc0b9035e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022299759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1022299759 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.3604525914
Short name T894
Test name
Test status
Simulation time 151606392614 ps
CPU time 202.69 seconds
Started Apr 25 04:04:51 PM PDT 24
Finished Apr 25 04:08:14 PM PDT 24
Peak memory 239016 kb
Host smart-8af973fa-ca06-423a-915a-8851c8cedb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604525914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3604525914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.2835180717
Short name T467
Test name
Test status
Simulation time 14782024390 ps
CPU time 413.99 seconds
Started Apr 25 04:04:46 PM PDT 24
Finished Apr 25 04:11:41 PM PDT 24
Peak memory 234548 kb
Host smart-d793a02a-1970-4f2e-8ee0-4c9f6703ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835180717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.2835180717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.589828843
Short name T445
Test name
Test status
Simulation time 13478473723 ps
CPU time 160.44 seconds
Started Apr 25 04:04:51 PM PDT 24
Finished Apr 25 04:07:32 PM PDT 24
Peak memory 238056 kb
Host smart-7e1bc87c-f902-4d37-b4e5-7583c6794208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589828843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.589828843 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.1262954717
Short name T647
Test name
Test status
Simulation time 12106466291 ps
CPU time 96.53 seconds
Started Apr 25 04:04:51 PM PDT 24
Finished Apr 25 04:06:28 PM PDT 24
Peak memory 242712 kb
Host smart-d4bb4f43-5bdb-49ab-b64e-92fc4e8f6b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262954717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.1262954717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.1108411528
Short name T945
Test name
Test status
Simulation time 1667136425 ps
CPU time 2.94 seconds
Started Apr 25 04:04:50 PM PDT 24
Finished Apr 25 04:04:54 PM PDT 24
Peak memory 218116 kb
Host smart-ff4027fc-fe47-43b7-8728-609957f5b1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108411528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.1108411528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.1876173920
Short name T568
Test name
Test status
Simulation time 31488518922 ps
CPU time 275.29 seconds
Started Apr 25 04:04:46 PM PDT 24
Finished Apr 25 04:09:22 PM PDT 24
Peak memory 243708 kb
Host smart-314694fd-11fd-40c8-9351-4d9a6c627466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876173920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.1876173920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2022883188
Short name T576
Test name
Test status
Simulation time 4972331525 ps
CPU time 468.71 seconds
Started Apr 25 04:04:46 PM PDT 24
Finished Apr 25 04:12:36 PM PDT 24
Peak memory 254428 kb
Host smart-d2eb2a1e-0394-4b36-951b-25eef4a88386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022883188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2022883188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.3367358924
Short name T535
Test name
Test status
Simulation time 1118460595 ps
CPU time 43.9 seconds
Started Apr 25 04:04:47 PM PDT 24
Finished Apr 25 04:05:31 PM PDT 24
Peak memory 221784 kb
Host smart-47076122-892b-495d-9900-8df513a81801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367358924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.3367358924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3440536393
Short name T343
Test name
Test status
Simulation time 157887196770 ps
CPU time 2204.29 seconds
Started Apr 25 04:04:52 PM PDT 24
Finished Apr 25 04:41:37 PM PDT 24
Peak memory 437900 kb
Host smart-4931676b-3870-4c20-aa23-2eb73ace3689
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3440536393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3440536393 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.1454520704
Short name T692
Test name
Test status
Simulation time 150610811 ps
CPU time 5.61 seconds
Started Apr 25 04:04:46 PM PDT 24
Finished Apr 25 04:04:53 PM PDT 24
Peak memory 218172 kb
Host smart-80e8aca0-129e-41cb-bafc-1a3cee89b71e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454520704 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.1454520704 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.592395
Short name T977
Test name
Test status
Simulation time 1494534005 ps
CPU time 6.35 seconds
Started Apr 25 04:04:50 PM PDT 24
Finished Apr 25 04:04:57 PM PDT 24
Peak memory 219144 kb
Host smart-2470fc1c-590e-47b3-beb9-a42ee151d8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592395 -assert nopostproc +UVM_TESTNAME=kmac_base_tes
t +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac_xof.592395 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.2323302945
Short name T382
Test name
Test status
Simulation time 86275140742 ps
CPU time 2076.94 seconds
Started Apr 25 04:04:46 PM PDT 24
Finished Apr 25 04:39:24 PM PDT 24
Peak memory 392780 kb
Host smart-30ae1fe0-669e-4573-9006-b596ce32b37e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2323302945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.2323302945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2607949630
Short name T259
Test name
Test status
Simulation time 79161029173 ps
CPU time 1913.85 seconds
Started Apr 25 04:04:50 PM PDT 24
Finished Apr 25 04:36:44 PM PDT 24
Peak memory 382140 kb
Host smart-5130b6e3-5db4-4ec5-ba98-f7d2bd12e236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2607949630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2607949630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.578658776
Short name T209
Test name
Test status
Simulation time 30125819159 ps
CPU time 1434.41 seconds
Started Apr 25 04:04:53 PM PDT 24
Finished Apr 25 04:28:48 PM PDT 24
Peak memory 335984 kb
Host smart-04c94b2c-dbae-4ab3-ab6a-99c5f2d4b7fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=578658776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.578658776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.4252233434
Short name T557
Test name
Test status
Simulation time 36139388828 ps
CPU time 1325.9 seconds
Started Apr 25 04:04:48 PM PDT 24
Finished Apr 25 04:26:55 PM PDT 24
Peak memory 306676 kb
Host smart-a49d9eb5-c487-4c19-8460-9514224991cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4252233434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.4252233434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.4062630425
Short name T405
Test name
Test status
Simulation time 54903622167 ps
CPU time 4061.85 seconds
Started Apr 25 04:04:48 PM PDT 24
Finished Apr 25 05:12:31 PM PDT 24
Peak memory 560888 kb
Host smart-7844ca44-2eb2-482a-a004-4bff54309af1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4062630425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.4062630425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.1441698572
Short name T801
Test name
Test status
Simulation time 34914750 ps
CPU time 0.81 seconds
Started Apr 25 04:05:19 PM PDT 24
Finished Apr 25 04:05:20 PM PDT 24
Peak memory 217868 kb
Host smart-3e03c74a-2ace-4cf8-8440-d3c7cfb1f7d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441698572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1441698572 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.80266157
Short name T744
Test name
Test status
Simulation time 18435173822 ps
CPU time 227.34 seconds
Started Apr 25 04:05:09 PM PDT 24
Finished Apr 25 04:08:57 PM PDT 24
Peak memory 242744 kb
Host smart-14879e8d-50e4-433b-941a-cf69392ff903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80266157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.80266157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.1954010418
Short name T858
Test name
Test status
Simulation time 5857794842 ps
CPU time 169.27 seconds
Started Apr 25 04:04:59 PM PDT 24
Finished Apr 25 04:07:49 PM PDT 24
Peak memory 227156 kb
Host smart-a9a4a5c1-61a9-4aef-bcef-61e8860c92d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954010418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1954010418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.1536677083
Short name T427
Test name
Test status
Simulation time 7322646727 ps
CPU time 209.62 seconds
Started Apr 25 04:05:09 PM PDT 24
Finished Apr 25 04:08:39 PM PDT 24
Peak memory 240944 kb
Host smart-7084acb5-f14c-42bb-af7d-430e9ac6f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536677083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.1536677083 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.3954637248
Short name T1009
Test name
Test status
Simulation time 10398650444 ps
CPU time 313.94 seconds
Started Apr 25 04:05:10 PM PDT 24
Finished Apr 25 04:10:24 PM PDT 24
Peak memory 257788 kb
Host smart-75c1c3fd-6ffd-4ac2-a79c-115124818354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954637248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.3954637248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2732434403
Short name T595
Test name
Test status
Simulation time 3713376185 ps
CPU time 6.28 seconds
Started Apr 25 04:05:14 PM PDT 24
Finished Apr 25 04:05:21 PM PDT 24
Peak memory 218204 kb
Host smart-121afc92-48db-4fa9-bf5e-72c0421c5ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732434403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2732434403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.3290694502
Short name T442
Test name
Test status
Simulation time 36180851 ps
CPU time 1.5 seconds
Started Apr 25 04:05:13 PM PDT 24
Finished Apr 25 04:05:15 PM PDT 24
Peak memory 218240 kb
Host smart-56cf136f-ca95-4b48-a6e6-3f039a93e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290694502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3290694502 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.312341106
Short name T661
Test name
Test status
Simulation time 480925964356 ps
CPU time 3450.26 seconds
Started Apr 25 04:04:55 PM PDT 24
Finished Apr 25 05:02:27 PM PDT 24
Peak memory 486348 kb
Host smart-3d69d7b6-58cd-4e7e-8a51-eaaf70ec6787
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312341106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_an
d_output.312341106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.1866345413
Short name T49
Test name
Test status
Simulation time 22483325889 ps
CPU time 432.98 seconds
Started Apr 25 04:04:59 PM PDT 24
Finished Apr 25 04:12:12 PM PDT 24
Peak memory 250996 kb
Host smart-507e7e55-6fb9-4c36-9c1c-c924c004fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866345413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1866345413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.27362860
Short name T904
Test name
Test status
Simulation time 9572869447 ps
CPU time 74.81 seconds
Started Apr 25 04:04:56 PM PDT 24
Finished Apr 25 04:06:12 PM PDT 24
Peak memory 219264 kb
Host smart-2f794354-16e2-44de-abc9-caca5d5002c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27362860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.27362860 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.3676952417
Short name T1051
Test name
Test status
Simulation time 5521945757 ps
CPU time 473.53 seconds
Started Apr 25 04:05:13 PM PDT 24
Finished Apr 25 04:13:07 PM PDT 24
Peak memory 260608 kb
Host smart-280ee9d0-8ff4-4767-88b7-780b591a85d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3676952417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.3676952417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.1655639676
Short name T962
Test name
Test status
Simulation time 286651323 ps
CPU time 6.06 seconds
Started Apr 25 04:05:02 PM PDT 24
Finished Apr 25 04:05:08 PM PDT 24
Peak memory 218128 kb
Host smart-0e7da3a2-7dcb-4004-9600-08de2f34e3c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655639676 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.1655639676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.321718902
Short name T968
Test name
Test status
Simulation time 370634683 ps
CPU time 6.55 seconds
Started Apr 25 04:05:02 PM PDT 24
Finished Apr 25 04:05:09 PM PDT 24
Peak memory 218104 kb
Host smart-a2f9139d-22f7-4d18-8ae0-d57488da2642
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321718902 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.kmac_test_vectors_kmac_xof.321718902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.18158970
Short name T484
Test name
Test status
Simulation time 69134556523 ps
CPU time 2054.96 seconds
Started Apr 25 04:04:56 PM PDT 24
Finished Apr 25 04:39:12 PM PDT 24
Peak memory 400116 kb
Host smart-590fe2eb-c04d-4ec1-8e99-15f5de0d5e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=18158970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.18158970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_256.3941772904
Short name T227
Test name
Test status
Simulation time 243732040409 ps
CPU time 1942.32 seconds
Started Apr 25 04:05:01 PM PDT 24
Finished Apr 25 04:37:24 PM PDT 24
Peak memory 388384 kb
Host smart-73b21860-ab2e-4479-a12d-2bb51656ce73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3941772904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.3941772904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.953468800
Short name T446
Test name
Test status
Simulation time 74808296706 ps
CPU time 1785.35 seconds
Started Apr 25 04:05:04 PM PDT 24
Finished Apr 25 04:34:50 PM PDT 24
Peak memory 340672 kb
Host smart-dd88e5af-18f6-4132-9a91-dc0d0aed84e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=953468800 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.953468800 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.2625484157
Short name T490
Test name
Test status
Simulation time 11629375107 ps
CPU time 1117.82 seconds
Started Apr 25 04:05:01 PM PDT 24
Finished Apr 25 04:23:40 PM PDT 24
Peak memory 299636 kb
Host smart-3c5e2ff1-6f98-4d1a-846f-2564b53223a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2625484157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.2625484157 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.3210662131
Short name T884
Test name
Test status
Simulation time 739149548685 ps
CPU time 5670.46 seconds
Started Apr 25 04:05:02 PM PDT 24
Finished Apr 25 05:39:33 PM PDT 24
Peak memory 661580 kb
Host smart-bf003e77-7499-4053-8307-4ca01f3407cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3210662131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.3210662131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.3838837160
Short name T452
Test name
Test status
Simulation time 53438917036 ps
CPU time 4161.61 seconds
Started Apr 25 04:05:04 PM PDT 24
Finished Apr 25 05:14:27 PM PDT 24
Peak memory 567520 kb
Host smart-e7bee31c-1edc-4ef2-89d0-fc18c484435a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3838837160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.3838837160 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.3549139462
Short name T287
Test name
Test status
Simulation time 22958525 ps
CPU time 0.94 seconds
Started Apr 25 04:05:31 PM PDT 24
Finished Apr 25 04:05:33 PM PDT 24
Peak memory 217900 kb
Host smart-a24308e0-cec1-41aa-8e53-d40381add76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549139462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.3549139462 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.38456226
Short name T297
Test name
Test status
Simulation time 868398624 ps
CPU time 47.37 seconds
Started Apr 25 04:05:31 PM PDT 24
Finished Apr 25 04:06:20 PM PDT 24
Peak memory 226820 kb
Host smart-4776432f-0176-4c5c-9b0a-419bc35c09b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38456226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.38456226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.357481773
Short name T841
Test name
Test status
Simulation time 31739732290 ps
CPU time 1073.88 seconds
Started Apr 25 04:05:18 PM PDT 24
Finished Apr 25 04:23:12 PM PDT 24
Peak memory 242736 kb
Host smart-eced39ea-9396-49e3-bb51-ee87ea891bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357481773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.357481773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.1987720693
Short name T434
Test name
Test status
Simulation time 19207809844 ps
CPU time 184 seconds
Started Apr 25 04:05:29 PM PDT 24
Finished Apr 25 04:08:34 PM PDT 24
Peak memory 239424 kb
Host smart-70bf7ff4-1700-41a7-ae85-842989286a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987720693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.1987720693 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.2177008288
Short name T64
Test name
Test status
Simulation time 11502013538 ps
CPU time 196.78 seconds
Started Apr 25 04:05:32 PM PDT 24
Finished Apr 25 04:08:50 PM PDT 24
Peak memory 251848 kb
Host smart-4604f5d3-1b55-4c3a-a07f-bbf8f8ced13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177008288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.2177008288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.295562119
Short name T813
Test name
Test status
Simulation time 612906361 ps
CPU time 4.3 seconds
Started Apr 25 04:05:31 PM PDT 24
Finished Apr 25 04:05:37 PM PDT 24
Peak memory 218108 kb
Host smart-29535791-0d6e-434f-89d8-0b7bd2c43e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295562119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.295562119 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.709067251
Short name T69
Test name
Test status
Simulation time 133450132 ps
CPU time 1.52 seconds
Started Apr 25 04:05:32 PM PDT 24
Finished Apr 25 04:05:35 PM PDT 24
Peak memory 218144 kb
Host smart-c4bf9048-5817-4fa3-8f01-516bfc941c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709067251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.709067251 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.1159654967
Short name T817
Test name
Test status
Simulation time 84706751224 ps
CPU time 2658.62 seconds
Started Apr 25 04:05:19 PM PDT 24
Finished Apr 25 04:49:38 PM PDT 24
Peak memory 437332 kb
Host smart-683cf2d1-660d-4129-b9a1-e32c3f19550e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159654967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a
nd_output.1159654967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.2685689934
Short name T510
Test name
Test status
Simulation time 5473045866 ps
CPU time 424.39 seconds
Started Apr 25 04:05:20 PM PDT 24
Finished Apr 25 04:12:25 PM PDT 24
Peak memory 250816 kb
Host smart-d0193d02-66ac-442b-b5b8-d8b284fae904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685689934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.2685689934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.3403745251
Short name T623
Test name
Test status
Simulation time 3968114136 ps
CPU time 37.26 seconds
Started Apr 25 04:05:19 PM PDT 24
Finished Apr 25 04:05:57 PM PDT 24
Peak memory 226388 kb
Host smart-ff4cf7d0-7c0b-4e63-aa57-58b10298b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403745251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.3403745251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.3046920276
Short name T573
Test name
Test status
Simulation time 18383859521 ps
CPU time 649.27 seconds
Started Apr 25 04:05:32 PM PDT 24
Finished Apr 25 04:16:22 PM PDT 24
Peak memory 289992 kb
Host smart-1d5f4a23-19ea-4189-a89a-859dde5d0257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3046920276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.3046920276 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.3742816388
Short name T908
Test name
Test status
Simulation time 255996194 ps
CPU time 6.13 seconds
Started Apr 25 04:05:25 PM PDT 24
Finished Apr 25 04:05:31 PM PDT 24
Peak memory 218188 kb
Host smart-eeff7c25-de5b-48bd-84ed-56475d5da4d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742816388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.kmac_test_vectors_kmac.3742816388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3758688109
Short name T308
Test name
Test status
Simulation time 197045187 ps
CPU time 5.61 seconds
Started Apr 25 04:05:24 PM PDT 24
Finished Apr 25 04:05:30 PM PDT 24
Peak memory 218228 kb
Host smart-89d5829f-f46a-44ee-94da-3944c615942f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758688109 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3758688109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.67824893
Short name T363
Test name
Test status
Simulation time 20869612438 ps
CPU time 1963.17 seconds
Started Apr 25 04:05:20 PM PDT 24
Finished Apr 25 04:38:04 PM PDT 24
Peak memory 401480 kb
Host smart-b90e40a5-8740-42c7-8519-b149b87fa763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=67824893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.67824893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.804258540
Short name T280
Test name
Test status
Simulation time 20232537905 ps
CPU time 1878.77 seconds
Started Apr 25 04:05:20 PM PDT 24
Finished Apr 25 04:36:39 PM PDT 24
Peak memory 387604 kb
Host smart-63202394-acb5-4a49-9d6c-fc1b50fc5e95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=804258540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.804258540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.3245075022
Short name T278
Test name
Test status
Simulation time 94475747841 ps
CPU time 1632.07 seconds
Started Apr 25 04:05:24 PM PDT 24
Finished Apr 25 04:32:37 PM PDT 24
Peak memory 338484 kb
Host smart-efc44362-04a9-45f3-a768-76f48dadda66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3245075022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.3245075022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.3246114968
Short name T1012
Test name
Test status
Simulation time 138477429337 ps
CPU time 1271.17 seconds
Started Apr 25 04:05:25 PM PDT 24
Finished Apr 25 04:26:37 PM PDT 24
Peak memory 300132 kb
Host smart-deedd05b-18ba-4c99-b48b-e1b2202cb7f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3246114968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.3246114968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.671852132
Short name T197
Test name
Test status
Simulation time 834193950587 ps
CPU time 5398.95 seconds
Started Apr 25 04:05:33 PM PDT 24
Finished Apr 25 05:35:33 PM PDT 24
Peak memory 649604 kb
Host smart-e8a01844-9cfd-4690-b3ab-38cfa8e25471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=671852132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.671852132 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3645673222
Short name T186
Test name
Test status
Simulation time 199424356644 ps
CPU time 3931.36 seconds
Started Apr 25 04:05:28 PM PDT 24
Finished Apr 25 05:11:00 PM PDT 24
Peak memory 567984 kb
Host smart-b23a0aa2-c40a-47f9-b4d7-95f520ce7f86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3645673222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3645673222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3699555532
Short name T780
Test name
Test status
Simulation time 19062564 ps
CPU time 0.8 seconds
Started Apr 25 04:05:56 PM PDT 24
Finished Apr 25 04:05:57 PM PDT 24
Peak memory 217900 kb
Host smart-67f35afe-4e1c-4391-81de-929f4117501b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699555532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3699555532 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.3874477327
Short name T485
Test name
Test status
Simulation time 29964545564 ps
CPU time 157.88 seconds
Started Apr 25 04:05:46 PM PDT 24
Finished Apr 25 04:08:24 PM PDT 24
Peak memory 237984 kb
Host smart-194f8764-6091-4498-8e79-338245295aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874477327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.3874477327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.2278675002
Short name T360
Test name
Test status
Simulation time 174422003999 ps
CPU time 1200.47 seconds
Started Apr 25 04:05:37 PM PDT 24
Finished Apr 25 04:25:39 PM PDT 24
Peak memory 237492 kb
Host smart-679a74d9-ff63-48a1-a179-7f72252064e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278675002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2278675002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.4265097844
Short name T324
Test name
Test status
Simulation time 4764153477 ps
CPU time 26.37 seconds
Started Apr 25 04:05:44 PM PDT 24
Finished Apr 25 04:06:11 PM PDT 24
Peak memory 222772 kb
Host smart-79fdff3c-e5e5-4c3f-a485-0ee1c8b0b107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265097844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.4265097844 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.2004240607
Short name T497
Test name
Test status
Simulation time 11295889350 ps
CPU time 361.89 seconds
Started Apr 25 04:05:50 PM PDT 24
Finished Apr 25 04:11:53 PM PDT 24
Peak memory 259124 kb
Host smart-b2d03532-4c1a-43ee-929c-d580e7daeb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004240607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.2004240607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.1256919907
Short name T108
Test name
Test status
Simulation time 1101901099 ps
CPU time 2.7 seconds
Started Apr 25 04:05:49 PM PDT 24
Finished Apr 25 04:05:52 PM PDT 24
Peak memory 218084 kb
Host smart-149a1c3f-a0b5-404f-99bf-a310883aa55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256919907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.1256919907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.3133123122
Short name T949
Test name
Test status
Simulation time 82531498 ps
CPU time 1.38 seconds
Started Apr 25 04:05:50 PM PDT 24
Finished Apr 25 04:05:52 PM PDT 24
Peak memory 219060 kb
Host smart-2471a018-87de-47d6-9003-f39663dbcfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133123122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3133123122 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.2440534511
Short name T313
Test name
Test status
Simulation time 83797934436 ps
CPU time 2099.94 seconds
Started Apr 25 04:05:34 PM PDT 24
Finished Apr 25 04:40:35 PM PDT 24
Peak memory 392624 kb
Host smart-580ec1a1-fd71-4026-bbe7-6cb0665a37b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440534511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.2440534511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.3741179419
Short name T700
Test name
Test status
Simulation time 13919875073 ps
CPU time 87.8 seconds
Started Apr 25 04:05:35 PM PDT 24
Finished Apr 25 04:07:03 PM PDT 24
Peak memory 228976 kb
Host smart-3c79fdd1-fefd-4244-9311-3b74e9669904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741179419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.3741179419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.1192635278
Short name T1068
Test name
Test status
Simulation time 824670839 ps
CPU time 5.19 seconds
Started Apr 25 04:05:32 PM PDT 24
Finished Apr 25 04:05:38 PM PDT 24
Peak memory 223524 kb
Host smart-3575d23f-fa0b-4870-b604-fdbdfb21aad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192635278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.1192635278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.2614660948
Short name T589
Test name
Test status
Simulation time 151954100518 ps
CPU time 2438.88 seconds
Started Apr 25 04:05:50 PM PDT 24
Finished Apr 25 04:46:30 PM PDT 24
Peak memory 455592 kb
Host smart-87d51b3f-be3e-4c7e-b53a-d06fc2722938
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2614660948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.2614660948 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.2136919434
Short name T849
Test name
Test status
Simulation time 316387256 ps
CPU time 6.71 seconds
Started Apr 25 04:05:45 PM PDT 24
Finished Apr 25 04:05:52 PM PDT 24
Peak memory 218152 kb
Host smart-88df701f-a9f3-4ee7-a5dd-422050bd47f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136919434 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.2136919434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.594899030
Short name T848
Test name
Test status
Simulation time 404322692 ps
CPU time 6.08 seconds
Started Apr 25 04:05:45 PM PDT 24
Finished Apr 25 04:05:51 PM PDT 24
Peak memory 218172 kb
Host smart-a31f4f92-2e98-40ff-bb8b-d04cc35f8c8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594899030 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.kmac_test_vectors_kmac_xof.594899030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3403366817
Short name T471
Test name
Test status
Simulation time 49328109191 ps
CPU time 1964.55 seconds
Started Apr 25 04:05:35 PM PDT 24
Finished Apr 25 04:38:20 PM PDT 24
Peak memory 398876 kb
Host smart-40b13bba-f46f-494e-a2cd-fc1b75cc5697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3403366817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3403366817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.1951959151
Short name T235
Test name
Test status
Simulation time 129637669204 ps
CPU time 1757.3 seconds
Started Apr 25 04:05:37 PM PDT 24
Finished Apr 25 04:34:56 PM PDT 24
Peak memory 389036 kb
Host smart-76a26b61-688f-4dfe-844c-77ba333463c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1951959151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.1951959151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2705218597
Short name T859
Test name
Test status
Simulation time 700546306225 ps
CPU time 1748.15 seconds
Started Apr 25 04:05:39 PM PDT 24
Finished Apr 25 04:34:48 PM PDT 24
Peak memory 338400 kb
Host smart-9afcb221-8b99-4335-9cfc-df0cc66fbabe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2705218597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2705218597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.35625527
Short name T316
Test name
Test status
Simulation time 81981825720 ps
CPU time 1280.39 seconds
Started Apr 25 04:05:39 PM PDT 24
Finished Apr 25 04:27:00 PM PDT 24
Peak memory 299888 kb
Host smart-b2fee3bf-6201-4008-b596-884a9e6fba0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=35625527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.35625527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.829020652
Short name T391
Test name
Test status
Simulation time 121637428567 ps
CPU time 4404.92 seconds
Started Apr 25 04:05:46 PM PDT 24
Finished Apr 25 05:19:12 PM PDT 24
Peak memory 644116 kb
Host smart-b3f3cd2d-0d9f-47e2-bc3a-a3bd6549b0c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=829020652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.829020652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.3668065187
Short name T410
Test name
Test status
Simulation time 107375360705 ps
CPU time 4051.15 seconds
Started Apr 25 04:05:45 PM PDT 24
Finished Apr 25 05:13:17 PM PDT 24
Peak memory 572180 kb
Host smart-b06ff538-34c9-4b62-bfb7-3bb132bec8c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3668065187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3668065187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.2436832460
Short name T319
Test name
Test status
Simulation time 24938202 ps
CPU time 0.86 seconds
Started Apr 25 04:06:08 PM PDT 24
Finished Apr 25 04:06:10 PM PDT 24
Peak memory 217884 kb
Host smart-21796017-001f-4c2a-a919-398da73d951e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436832460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.2436832460 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.1073897490
Short name T660
Test name
Test status
Simulation time 47990790053 ps
CPU time 324.62 seconds
Started Apr 25 04:06:09 PM PDT 24
Finished Apr 25 04:11:35 PM PDT 24
Peak memory 248368 kb
Host smart-72bf3f13-62e4-4b1a-8532-f206920f3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073897490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.1073897490 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.3840823614
Short name T1067
Test name
Test status
Simulation time 118978450746 ps
CPU time 1272.98 seconds
Started Apr 25 04:05:56 PM PDT 24
Finished Apr 25 04:27:09 PM PDT 24
Peak memory 237500 kb
Host smart-a45d7ccc-097b-4e71-82e8-3814814cfe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840823614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3840823614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.1390591973
Short name T698
Test name
Test status
Simulation time 2591559421 ps
CPU time 130.41 seconds
Started Apr 25 04:06:04 PM PDT 24
Finished Apr 25 04:08:15 PM PDT 24
Peak memory 236092 kb
Host smart-d71a8a13-3d02-4085-8a55-5a4e20e2f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390591973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1390591973 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_key_error.3711042202
Short name T372
Test name
Test status
Simulation time 707664443 ps
CPU time 4.24 seconds
Started Apr 25 04:06:11 PM PDT 24
Finished Apr 25 04:06:15 PM PDT 24
Peak memory 218060 kb
Host smart-3da4e12f-4a98-4324-9f3e-156af5d365a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711042202 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.3711042202 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.3070223409
Short name T519
Test name
Test status
Simulation time 32488375 ps
CPU time 1.29 seconds
Started Apr 25 04:06:08 PM PDT 24
Finished Apr 25 04:06:10 PM PDT 24
Peak memory 219044 kb
Host smart-82393a93-e70b-410c-983d-0a94a4f41187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070223409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3070223409 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1218690648
Short name T1032
Test name
Test status
Simulation time 12629535797 ps
CPU time 1147.41 seconds
Started Apr 25 04:05:53 PM PDT 24
Finished Apr 25 04:25:01 PM PDT 24
Peak memory 333964 kb
Host smart-04bba3ef-dfc6-4577-9040-9f4b003ca226
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218690648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1218690648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.3164993257
Short name T499
Test name
Test status
Simulation time 4264794576 ps
CPU time 87.61 seconds
Started Apr 25 04:05:54 PM PDT 24
Finished Apr 25 04:07:22 PM PDT 24
Peak memory 230804 kb
Host smart-82341d58-6764-49a0-9db6-bd4baa46450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164993257 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.3164993257 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.3539435259
Short name T135
Test name
Test status
Simulation time 12372802929 ps
CPU time 81.11 seconds
Started Apr 25 04:05:54 PM PDT 24
Finished Apr 25 04:07:15 PM PDT 24
Peak memory 226356 kb
Host smart-0e701cb4-ce6f-43a2-8531-df9c16eed77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539435259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.3539435259 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3517056666
Short name T42
Test name
Test status
Simulation time 98225749363 ps
CPU time 2160.15 seconds
Started Apr 25 04:06:07 PM PDT 24
Finished Apr 25 04:42:08 PM PDT 24
Peak memory 433040 kb
Host smart-9399e4b9-3819-43dc-8434-df38dfead403
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3517056666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3517056666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.2856690301
Short name T600
Test name
Test status
Simulation time 201128278 ps
CPU time 6.35 seconds
Started Apr 25 04:06:05 PM PDT 24
Finished Apr 25 04:06:12 PM PDT 24
Peak memory 219228 kb
Host smart-cf60c283-6136-4bcd-bda1-883b501c848f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856690301 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.2856690301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2369169761
Short name T610
Test name
Test status
Simulation time 304967536 ps
CPU time 6.01 seconds
Started Apr 25 04:06:03 PM PDT 24
Finished Apr 25 04:06:09 PM PDT 24
Peak memory 219152 kb
Host smart-a3c112bb-5d6a-45ad-b5fd-972163c58263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369169761 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2369169761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2169269985
Short name T251
Test name
Test status
Simulation time 20634186146 ps
CPU time 1977.26 seconds
Started Apr 25 04:06:01 PM PDT 24
Finished Apr 25 04:38:59 PM PDT 24
Peak memory 397632 kb
Host smart-568d2280-4b18-4b94-9df8-2476902cac4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2169269985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2169269985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.2132014671
Short name T474
Test name
Test status
Simulation time 63304049720 ps
CPU time 2173.25 seconds
Started Apr 25 04:05:58 PM PDT 24
Finished Apr 25 04:42:13 PM PDT 24
Peak memory 388072 kb
Host smart-e8228014-1d42-4391-b40f-5ac42d97d089
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2132014671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.2132014671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.1623118564
Short name T836
Test name
Test status
Simulation time 28981445810 ps
CPU time 1505.36 seconds
Started Apr 25 04:06:00 PM PDT 24
Finished Apr 25 04:31:06 PM PDT 24
Peak memory 336664 kb
Host smart-d27650b2-8fc3-4aff-84c0-9f2439a322a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1623118564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.1623118564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1735294275
Short name T347
Test name
Test status
Simulation time 133253760350 ps
CPU time 1245.05 seconds
Started Apr 25 04:06:08 PM PDT 24
Finished Apr 25 04:26:54 PM PDT 24
Peak memory 299536 kb
Host smart-003448bd-08ec-4c41-b733-c391dc296876
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1735294275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1735294275 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.1300171068
Short name T361
Test name
Test status
Simulation time 668604809524 ps
CPU time 5819.54 seconds
Started Apr 25 04:06:09 PM PDT 24
Finished Apr 25 05:43:10 PM PDT 24
Peak memory 653268 kb
Host smart-8417c999-83f2-4eff-b41d-55ce2d21e81f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1300171068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1300171068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.2969351045
Short name T1076
Test name
Test status
Simulation time 218420918388 ps
CPU time 4787.82 seconds
Started Apr 25 04:06:09 PM PDT 24
Finished Apr 25 05:25:58 PM PDT 24
Peak memory 568524 kb
Host smart-1fedfb75-2652-4c2a-89e9-25851ac629a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2969351045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2969351045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.4281782370
Short name T746
Test name
Test status
Simulation time 67358613 ps
CPU time 0.87 seconds
Started Apr 25 03:56:36 PM PDT 24
Finished Apr 25 03:56:38 PM PDT 24
Peak memory 217904 kb
Host smart-25c3c987-bbe5-4c04-8ffc-6a61cc78a79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281782370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4281782370 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.537548541
Short name T1000
Test name
Test status
Simulation time 3365753892 ps
CPU time 82.38 seconds
Started Apr 25 03:56:16 PM PDT 24
Finished Apr 25 03:57:39 PM PDT 24
Peak memory 230408 kb
Host smart-901d1716-710d-4087-af44-f9f5e6e9d1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537548541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.537548541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.842891987
Short name T759
Test name
Test status
Simulation time 51603569986 ps
CPU time 356.39 seconds
Started Apr 25 03:56:12 PM PDT 24
Finished Apr 25 04:02:10 PM PDT 24
Peak memory 247804 kb
Host smart-3e339d49-ec0a-4003-b77c-717ca2e01d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842891987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.842891987 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.3783055537
Short name T309
Test name
Test status
Simulation time 10693637444 ps
CPU time 907.59 seconds
Started Apr 25 03:56:02 PM PDT 24
Finished Apr 25 04:11:11 PM PDT 24
Peak memory 242740 kb
Host smart-567f6adb-0a2c-4073-a35c-8d4c7b36d13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783055537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.3783055537 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.2071750766
Short name T302
Test name
Test status
Simulation time 1825466900 ps
CPU time 41.09 seconds
Started Apr 25 03:56:15 PM PDT 24
Finished Apr 25 03:56:57 PM PDT 24
Peak memory 227032 kb
Host smart-d6b1ee22-ad74-4b4f-9f8d-1bb4a94e67b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2071750766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2071750766 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.1603475179
Short name T885
Test name
Test status
Simulation time 350755846 ps
CPU time 1.41 seconds
Started Apr 25 03:56:20 PM PDT 24
Finished Apr 25 03:56:22 PM PDT 24
Peak memory 221796 kb
Host smart-cb8aa821-6c90-4925-8446-e23555dd3fe9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1603475179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.1603475179 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.1177124399
Short name T56
Test name
Test status
Simulation time 10842280681 ps
CPU time 36.9 seconds
Started Apr 25 03:56:20 PM PDT 24
Finished Apr 25 03:56:57 PM PDT 24
Peak memory 218344 kb
Host smart-5e38ea11-d9c8-44b4-8fb9-db21d66ee36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177124399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1177124399 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.634381573
Short name T793
Test name
Test status
Simulation time 57526716098 ps
CPU time 378.47 seconds
Started Apr 25 03:56:15 PM PDT 24
Finished Apr 25 04:02:34 PM PDT 24
Peak memory 253544 kb
Host smart-172f97d5-0e84-455a-88c7-f04fae367567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634381573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.634381573 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_error.2851566479
Short name T161
Test name
Test status
Simulation time 4305131686 ps
CPU time 374.84 seconds
Started Apr 25 03:56:20 PM PDT 24
Finished Apr 25 04:02:36 PM PDT 24
Peak memory 259104 kb
Host smart-12c2ed10-02b1-4a61-b5c6-a89072fec6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851566479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.2851566479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/default/3.kmac_key_error.532531850
Short name T663
Test name
Test status
Simulation time 967868012 ps
CPU time 2.5 seconds
Started Apr 25 03:56:14 PM PDT 24
Finished Apr 25 03:56:18 PM PDT 24
Peak memory 218096 kb
Host smart-876343e6-c813-4d8a-9e68-ae40d869bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532531850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.532531850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.2853269395
Short name T680
Test name
Test status
Simulation time 47355292 ps
CPU time 1.43 seconds
Started Apr 25 03:56:24 PM PDT 24
Finished Apr 25 03:56:26 PM PDT 24
Peak memory 218232 kb
Host smart-9717a367-f344-4ce7-ba8c-ce2c00750b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853269395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2853269395 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.4268417506
Short name T386
Test name
Test status
Simulation time 96865205557 ps
CPU time 2545.33 seconds
Started Apr 25 03:56:02 PM PDT 24
Finished Apr 25 04:38:28 PM PDT 24
Peak memory 422408 kb
Host smart-b2f782ea-5436-4396-ac66-9f926e5747b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268417506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.4268417506 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.982708141
Short name T643
Test name
Test status
Simulation time 23948685642 ps
CPU time 161.47 seconds
Started Apr 25 03:56:16 PM PDT 24
Finished Apr 25 03:58:58 PM PDT 24
Peak memory 237132 kb
Host smart-19ea56e3-3672-4796-8116-0a478d424585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982708141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.982708141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1879379025
Short name T111
Test name
Test status
Simulation time 4679573154 ps
CPU time 47.84 seconds
Started Apr 25 03:56:40 PM PDT 24
Finished Apr 25 03:57:29 PM PDT 24
Peak memory 256192 kb
Host smart-7349360c-abe9-4927-82c2-094be08d336a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879379025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1879379025 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.1669353532
Short name T305
Test name
Test status
Simulation time 4407967376 ps
CPU time 28.82 seconds
Started Apr 25 03:56:06 PM PDT 24
Finished Apr 25 03:56:36 PM PDT 24
Peak memory 223976 kb
Host smart-4e56a83c-d376-484a-9e49-7b822c0e852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669353532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.1669353532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.3182554782
Short name T877
Test name
Test status
Simulation time 2594064347 ps
CPU time 26.39 seconds
Started Apr 25 03:56:05 PM PDT 24
Finished Apr 25 03:56:32 PM PDT 24
Peak memory 222500 kb
Host smart-8ded6c86-3875-4ecf-b8b7-a8ac9caf1238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182554782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3182554782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.3714266563
Short name T134
Test name
Test status
Simulation time 88296659027 ps
CPU time 2716.04 seconds
Started Apr 25 03:56:31 PM PDT 24
Finished Apr 25 04:41:49 PM PDT 24
Peak memory 380424 kb
Host smart-d603760f-cfac-47e1-9d04-5f2b55c06da3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714266563 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.3714266563 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.571901162
Short name T118
Test name
Test status
Simulation time 296333642 ps
CPU time 6.4 seconds
Started Apr 25 03:56:15 PM PDT 24
Finished Apr 25 03:56:22 PM PDT 24
Peak memory 218196 kb
Host smart-c6602cbd-cc9a-463b-bab4-ba006862ddae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571901162 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.kmac_test_vectors_kmac.571901162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.2542722369
Short name T295
Test name
Test status
Simulation time 241729667 ps
CPU time 6.31 seconds
Started Apr 25 03:56:15 PM PDT 24
Finished Apr 25 03:56:22 PM PDT 24
Peak memory 218276 kb
Host smart-62f3e1ca-f878-4660-80ce-83e6af048cef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542722369 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.2542722369 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.265231022
Short name T395
Test name
Test status
Simulation time 42443514979 ps
CPU time 1972.81 seconds
Started Apr 25 03:56:02 PM PDT 24
Finished Apr 25 04:28:56 PM PDT 24
Peak memory 397396 kb
Host smart-c6361357-af83-4a07-989f-0b1c0ecb4f3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=265231022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.265231022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.312419079
Short name T530
Test name
Test status
Simulation time 502017686422 ps
CPU time 2331.42 seconds
Started Apr 25 03:56:03 PM PDT 24
Finished Apr 25 04:34:56 PM PDT 24
Peak memory 393428 kb
Host smart-bbb3b461-e200-4a44-b6e1-a8d86d52d889
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=312419079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.312419079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.1867500349
Short name T441
Test name
Test status
Simulation time 58428599209 ps
CPU time 1466.69 seconds
Started Apr 25 03:56:09 PM PDT 24
Finished Apr 25 04:20:37 PM PDT 24
Peak memory 334144 kb
Host smart-769d3c39-adc2-4406-947f-794b6f82946f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1867500349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.1867500349 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3625813238
Short name T136
Test name
Test status
Simulation time 205606349870 ps
CPU time 1371.22 seconds
Started Apr 25 03:56:08 PM PDT 24
Finished Apr 25 04:19:00 PM PDT 24
Peak memory 300640 kb
Host smart-51beeb43-ea7f-4022-9ebf-e4f011214269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3625813238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3625813238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.609768649
Short name T599
Test name
Test status
Simulation time 268169175634 ps
CPU time 6122.11 seconds
Started Apr 25 03:56:09 PM PDT 24
Finished Apr 25 05:38:13 PM PDT 24
Peak memory 647128 kb
Host smart-55351262-e8bb-4d4f-96ba-353739226d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=609768649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.609768649 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.3802514723
Short name T915
Test name
Test status
Simulation time 231292180709 ps
CPU time 4887.49 seconds
Started Apr 25 03:56:11 PM PDT 24
Finished Apr 25 05:17:40 PM PDT 24
Peak memory 569076 kb
Host smart-5bce17bc-4a19-4403-95e3-3272f2163dd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3802514723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.3802514723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.2173685118
Short name T743
Test name
Test status
Simulation time 25678821 ps
CPU time 0.85 seconds
Started Apr 25 04:06:28 PM PDT 24
Finished Apr 25 04:06:29 PM PDT 24
Peak memory 217820 kb
Host smart-866b80b8-c57a-497d-b8db-bde983f04eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173685118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2173685118 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.2763430817
Short name T169
Test name
Test status
Simulation time 3803579752 ps
CPU time 90.24 seconds
Started Apr 25 04:06:19 PM PDT 24
Finished Apr 25 04:07:50 PM PDT 24
Peak memory 231008 kb
Host smart-eba78d33-fa7a-4ad0-8e6a-7bdc0e8bbc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763430817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.2763430817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.2418465371
Short name T546
Test name
Test status
Simulation time 90143000498 ps
CPU time 869.49 seconds
Started Apr 25 04:06:13 PM PDT 24
Finished Apr 25 04:20:44 PM PDT 24
Peak memory 234524 kb
Host smart-4805746e-255a-4cec-9f26-a1225453224d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418465371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2418465371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_error.2849505558
Short name T615
Test name
Test status
Simulation time 23454633542 ps
CPU time 148.3 seconds
Started Apr 25 04:06:18 PM PDT 24
Finished Apr 25 04:08:47 PM PDT 24
Peak memory 256328 kb
Host smart-b6d5c637-8356-4a0f-a807-245aafe9d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849505558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.2849505558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2988391502
Short name T685
Test name
Test status
Simulation time 924850878 ps
CPU time 1.85 seconds
Started Apr 25 04:06:19 PM PDT 24
Finished Apr 25 04:06:22 PM PDT 24
Peak memory 218128 kb
Host smart-eeadd5e1-4c7b-4797-92fe-d95550d3446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988391502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2988391502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.289210637
Short name T587
Test name
Test status
Simulation time 2692329573 ps
CPU time 37.82 seconds
Started Apr 25 04:06:23 PM PDT 24
Finished Apr 25 04:07:02 PM PDT 24
Peak memory 235572 kb
Host smart-6ebf043b-2d1e-4493-a231-3724e1067f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289210637 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.289210637 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.3471112223
Short name T240
Test name
Test status
Simulation time 51669916490 ps
CPU time 316.61 seconds
Started Apr 25 04:06:15 PM PDT 24
Finished Apr 25 04:11:32 PM PDT 24
Peak memory 243544 kb
Host smart-cea17321-4a8c-4641-92f0-6d9ca29e2e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471112223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.3471112223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.3981694691
Short name T388
Test name
Test status
Simulation time 53680134791 ps
CPU time 389.54 seconds
Started Apr 25 04:06:13 PM PDT 24
Finished Apr 25 04:12:43 PM PDT 24
Peak memory 249720 kb
Host smart-413527be-df54-43c6-bd4c-57cf80f45c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981694691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.3981694691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.2986513386
Short name T142
Test name
Test status
Simulation time 544059805 ps
CPU time 16.3 seconds
Started Apr 25 04:06:12 PM PDT 24
Finished Apr 25 04:06:29 PM PDT 24
Peak memory 226316 kb
Host smart-27373694-e2a3-49c1-9329-2f59cb242420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986513386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2986513386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.2439823757
Short name T880
Test name
Test status
Simulation time 182476164327 ps
CPU time 1703.6 seconds
Started Apr 25 04:06:24 PM PDT 24
Finished Apr 25 04:34:49 PM PDT 24
Peak memory 348160 kb
Host smart-04624a12-ab56-43a9-be63-4000ef5346e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2439823757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.2439823757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_stress_all_with_rand_reset.2874804676
Short name T128
Test name
Test status
Simulation time 44712264260 ps
CPU time 1947.68 seconds
Started Apr 25 04:06:23 PM PDT 24
Finished Apr 25 04:38:52 PM PDT 24
Peak memory 405256 kb
Host smart-870518c9-5694-471b-8d75-67bcededa3b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2874804676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all_with_rand_reset.2874804676 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.4175267627
Short name T609
Test name
Test status
Simulation time 763847746 ps
CPU time 6.31 seconds
Started Apr 25 04:06:19 PM PDT 24
Finished Apr 25 04:06:26 PM PDT 24
Peak memory 218236 kb
Host smart-d69910d6-7cf8-4663-bc5a-5d95a2db690d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175267627 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.4175267627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3729159770
Short name T421
Test name
Test status
Simulation time 433111281 ps
CPU time 6.44 seconds
Started Apr 25 04:06:19 PM PDT 24
Finished Apr 25 04:06:27 PM PDT 24
Peak memory 218208 kb
Host smart-86e0e379-135c-4ff5-aca1-c0d37f1da58e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729159770 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3729159770 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.2308126220
Short name T190
Test name
Test status
Simulation time 100655768054 ps
CPU time 2077.5 seconds
Started Apr 25 04:06:14 PM PDT 24
Finished Apr 25 04:40:52 PM PDT 24
Peak memory 403804 kb
Host smart-c7c5ecfb-cadc-4d73-9d96-906d438910a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2308126220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.2308126220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.2866719433
Short name T3
Test name
Test status
Simulation time 38818316032 ps
CPU time 1875.52 seconds
Started Apr 25 04:06:14 PM PDT 24
Finished Apr 25 04:37:30 PM PDT 24
Peak memory 394920 kb
Host smart-fc0a865a-18a1-4475-b84f-00a8865bc06b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2866719433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.2866719433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2044024512
Short name T622
Test name
Test status
Simulation time 706536733348 ps
CPU time 1818.8 seconds
Started Apr 25 04:06:12 PM PDT 24
Finished Apr 25 04:36:32 PM PDT 24
Peak memory 341316 kb
Host smart-72d1e68d-cdd2-49fe-a1f7-692229181af0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2044024512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2044024512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.2366661231
Short name T951
Test name
Test status
Simulation time 17205209666 ps
CPU time 1127.01 seconds
Started Apr 25 04:06:14 PM PDT 24
Finished Apr 25 04:25:02 PM PDT 24
Peak memory 301776 kb
Host smart-0438c74e-0df9-43de-9e49-f4c6e05e2f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2366661231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.2366661231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.3120229294
Short name T756
Test name
Test status
Simulation time 993533526949 ps
CPU time 5034.11 seconds
Started Apr 25 04:06:12 PM PDT 24
Finished Apr 25 05:30:07 PM PDT 24
Peak memory 658576 kb
Host smart-0d05a216-80fb-4aeb-9afc-e61e25ee55fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3120229294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.3120229294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.1812395028
Short name T555
Test name
Test status
Simulation time 868530802701 ps
CPU time 4920.53 seconds
Started Apr 25 04:06:19 PM PDT 24
Finished Apr 25 05:28:21 PM PDT 24
Peak memory 563340 kb
Host smart-ab524fb1-8361-4a37-9b85-539857d0f9f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1812395028 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.1812395028 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.1973510022
Short name T237
Test name
Test status
Simulation time 39545960 ps
CPU time 0.77 seconds
Started Apr 25 04:06:54 PM PDT 24
Finished Apr 25 04:06:56 PM PDT 24
Peak memory 217880 kb
Host smart-56aed113-95ea-49e3-8ae9-b514a8ff425d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973510022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.1973510022 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.2440069310
Short name T168
Test name
Test status
Simulation time 7060410144 ps
CPU time 114.78 seconds
Started Apr 25 04:06:39 PM PDT 24
Finished Apr 25 04:08:34 PM PDT 24
Peak memory 235108 kb
Host smart-13bac040-8602-4d4a-a355-6cf634577d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440069310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.2440069310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.1909319857
Short name T369
Test name
Test status
Simulation time 33006664448 ps
CPU time 1104.73 seconds
Started Apr 25 04:06:30 PM PDT 24
Finished Apr 25 04:24:55 PM PDT 24
Peak memory 242664 kb
Host smart-e89b3b72-cc34-4b03-8832-16e904a9a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909319857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1909319857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.859400836
Short name T726
Test name
Test status
Simulation time 28838430948 ps
CPU time 253.64 seconds
Started Apr 25 04:06:37 PM PDT 24
Finished Apr 25 04:10:51 PM PDT 24
Peak memory 244524 kb
Host smart-7ab096de-2720-456d-9c19-975353f1e775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859400836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.859400836 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.2957060497
Short name T345
Test name
Test status
Simulation time 10259875179 ps
CPU time 353.56 seconds
Started Apr 25 04:06:50 PM PDT 24
Finished Apr 25 04:12:44 PM PDT 24
Peak memory 268208 kb
Host smart-ae3e2715-599c-4764-8358-8e81e51edb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957060497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.2957060497 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2144211076
Short name T1030
Test name
Test status
Simulation time 759794963 ps
CPU time 2.69 seconds
Started Apr 25 04:06:43 PM PDT 24
Finished Apr 25 04:06:46 PM PDT 24
Peak memory 218128 kb
Host smart-9222a4ec-a32c-4f20-8844-e78ce92c69c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144211076 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2144211076 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.640838663
Short name T85
Test name
Test status
Simulation time 79049412 ps
CPU time 1.32 seconds
Started Apr 25 04:06:48 PM PDT 24
Finished Apr 25 04:06:50 PM PDT 24
Peak memory 218172 kb
Host smart-c2ef6413-4f3a-4ba1-9731-ba109eaae5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640838663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.640838663 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.3807224615
Short name T231
Test name
Test status
Simulation time 2805829224 ps
CPU time 302.57 seconds
Started Apr 25 04:06:32 PM PDT 24
Finished Apr 25 04:11:35 PM PDT 24
Peak memory 242916 kb
Host smart-9b82d236-610a-4fe0-a059-46a161d0386d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807224615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.3807224615 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.1376575586
Short name T379
Test name
Test status
Simulation time 87653731319 ps
CPU time 586.69 seconds
Started Apr 25 04:06:29 PM PDT 24
Finished Apr 25 04:16:16 PM PDT 24
Peak memory 255880 kb
Host smart-e555f85a-4caa-4846-9493-137a9e74d3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376575586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.1376575586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.989067603
Short name T275
Test name
Test status
Simulation time 7498462882 ps
CPU time 36.14 seconds
Started Apr 25 04:06:33 PM PDT 24
Finished Apr 25 04:07:10 PM PDT 24
Peak memory 218268 kb
Host smart-fea33fe4-40c2-492a-9666-3db51d823dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989067603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.989067603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.3053457991
Short name T491
Test name
Test status
Simulation time 140910554990 ps
CPU time 959.9 seconds
Started Apr 25 04:06:43 PM PDT 24
Finished Apr 25 04:22:43 PM PDT 24
Peak memory 336400 kb
Host smart-00f7fb3d-5f38-4c86-bdad-2c3361604558
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3053457991 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.3053457991 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.3614682175
Short name T1053
Test name
Test status
Simulation time 421208216 ps
CPU time 5.42 seconds
Started Apr 25 04:06:38 PM PDT 24
Finished Apr 25 04:06:44 PM PDT 24
Peak memory 218208 kb
Host smart-a7d137ed-03de-4b39-afeb-e34cd6a7f9ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614682175 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.3614682175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1372207671
Short name T390
Test name
Test status
Simulation time 839418030 ps
CPU time 6.79 seconds
Started Apr 25 04:06:38 PM PDT 24
Finished Apr 25 04:06:45 PM PDT 24
Peak memory 218236 kb
Host smart-ecb83799-9a81-4d2c-b99c-93f909507445
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372207671 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1372207671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.2467354006
Short name T526
Test name
Test status
Simulation time 41259677214 ps
CPU time 1811.34 seconds
Started Apr 25 04:06:32 PM PDT 24
Finished Apr 25 04:36:44 PM PDT 24
Peak memory 392240 kb
Host smart-9a857ac7-c4ff-4abb-ac21-64f851774cb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2467354006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.2467354006 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.248041316
Short name T518
Test name
Test status
Simulation time 284841934018 ps
CPU time 2186.11 seconds
Started Apr 25 04:06:30 PM PDT 24
Finished Apr 25 04:42:57 PM PDT 24
Peak memory 390296 kb
Host smart-b9b88510-92e4-4a99-95fa-d71732224805
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=248041316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.248041316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.4035760233
Short name T264
Test name
Test status
Simulation time 93947875582 ps
CPU time 1772.73 seconds
Started Apr 25 04:06:33 PM PDT 24
Finished Apr 25 04:36:06 PM PDT 24
Peak memory 345624 kb
Host smart-f86ed5ff-4091-4d84-b95f-442fc216a8d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4035760233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.4035760233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.2338077049
Short name T487
Test name
Test status
Simulation time 21311875415 ps
CPU time 1064.62 seconds
Started Apr 25 04:06:34 PM PDT 24
Finished Apr 25 04:24:19 PM PDT 24
Peak memory 298040 kb
Host smart-b5a0e9e5-9aa8-455e-b320-8b7559ade552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2338077049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2338077049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.4123412553
Short name T448
Test name
Test status
Simulation time 1095199038916 ps
CPU time 5189.81 seconds
Started Apr 25 04:06:34 PM PDT 24
Finished Apr 25 05:33:05 PM PDT 24
Peak memory 640940 kb
Host smart-271ecf2a-383c-4412-ac7a-543e14496a6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4123412553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.4123412553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.3397228412
Short name T811
Test name
Test status
Simulation time 234268418521 ps
CPU time 4373.3 seconds
Started Apr 25 04:06:33 PM PDT 24
Finished Apr 25 05:19:27 PM PDT 24
Peak memory 569284 kb
Host smart-9698f5d8-476a-438d-bddb-11591aad4b3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3397228412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3397228412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.4259563019
Short name T735
Test name
Test status
Simulation time 42259643 ps
CPU time 0.86 seconds
Started Apr 25 04:07:00 PM PDT 24
Finished Apr 25 04:07:01 PM PDT 24
Peak memory 217924 kb
Host smart-4eab3c17-383f-41bd-b054-c575a5003c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259563019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.4259563019 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.2086890224
Short name T889
Test name
Test status
Simulation time 15640642419 ps
CPU time 204.15 seconds
Started Apr 25 04:06:55 PM PDT 24
Finished Apr 25 04:10:20 PM PDT 24
Peak memory 240584 kb
Host smart-92fbd291-0a7b-4ae7-b140-d5956e850380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086890224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2086890224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.3692868930
Short name T120
Test name
Test status
Simulation time 35989612453 ps
CPU time 766.76 seconds
Started Apr 25 04:06:55 PM PDT 24
Finished Apr 25 04:19:42 PM PDT 24
Peak memory 239852 kb
Host smart-fe51291f-9b5c-477d-8be6-6c8725c24537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692868930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.3692868930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.94517794
Short name T73
Test name
Test status
Simulation time 10271946279 ps
CPU time 268.46 seconds
Started Apr 25 04:06:56 PM PDT 24
Finished Apr 25 04:11:25 PM PDT 24
Peak memory 244772 kb
Host smart-a27e075b-dcd0-4ee9-88a9-3ba9e21e6e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94517794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.94517794 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_key_error.2956312705
Short name T291
Test name
Test status
Simulation time 2938273977 ps
CPU time 3.05 seconds
Started Apr 25 04:06:56 PM PDT 24
Finished Apr 25 04:07:00 PM PDT 24
Peak memory 218168 kb
Host smart-81ef071f-b66c-4a1b-850b-7e3fa69c8855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956312705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.2956312705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2179673654
Short name T31
Test name
Test status
Simulation time 37244211 ps
CPU time 1.22 seconds
Started Apr 25 04:06:56 PM PDT 24
Finished Apr 25 04:06:57 PM PDT 24
Peak memory 218204 kb
Host smart-ace41642-f5cf-4455-9459-0942b65209ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179673654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2179673654 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.125386542
Short name T494
Test name
Test status
Simulation time 275989609861 ps
CPU time 870.39 seconds
Started Apr 25 04:06:46 PM PDT 24
Finished Apr 25 04:21:17 PM PDT 24
Peak memory 280160 kb
Host smart-27d67577-e9ab-4726-87f2-34ae42e219d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125386542 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_an
d_output.125386542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.1988582269
Short name T269
Test name
Test status
Simulation time 6089226058 ps
CPU time 73.76 seconds
Started Apr 25 04:06:55 PM PDT 24
Finished Apr 25 04:08:09 PM PDT 24
Peak memory 229856 kb
Host smart-7f9c6663-7613-4807-81b3-8b707a5cb253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988582269 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1988582269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.1829806583
Short name T496
Test name
Test status
Simulation time 725240860 ps
CPU time 8.65 seconds
Started Apr 25 04:06:47 PM PDT 24
Finished Apr 25 04:06:56 PM PDT 24
Peak memory 226196 kb
Host smart-04b7ba30-01c0-49b9-a33c-342624f8085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829806583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1829806583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.179476333
Short name T458
Test name
Test status
Simulation time 129359776824 ps
CPU time 1657.88 seconds
Started Apr 25 04:06:57 PM PDT 24
Finished Apr 25 04:34:36 PM PDT 24
Peak memory 390516 kb
Host smart-9d2bc6fd-862e-4676-b400-f60caf9ee855
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=179476333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.179476333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.180638533
Short name T644
Test name
Test status
Simulation time 547373209 ps
CPU time 6.18 seconds
Started Apr 25 04:06:52 PM PDT 24
Finished Apr 25 04:06:58 PM PDT 24
Peak memory 218232 kb
Host smart-c1aa1b55-cc10-4db6-b6da-9107874705fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180638533 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.kmac_test_vectors_kmac.180638533 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.1053729812
Short name T5
Test name
Test status
Simulation time 202101388577 ps
CPU time 2126.49 seconds
Started Apr 25 04:06:55 PM PDT 24
Finished Apr 25 04:42:22 PM PDT 24
Peak memory 396328 kb
Host smart-bb79b7a1-7f31-477e-93b3-567a3ea91afb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1053729812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.1053729812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.4105947617
Short name T785
Test name
Test status
Simulation time 387964309857 ps
CPU time 2355.95 seconds
Started Apr 25 04:06:53 PM PDT 24
Finished Apr 25 04:46:09 PM PDT 24
Peak memory 390340 kb
Host smart-ecdb8589-aef3-48e0-b2e8-f9177e043851
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4105947617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.4105947617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.2989637702
Short name T893
Test name
Test status
Simulation time 251927008715 ps
CPU time 1670.97 seconds
Started Apr 25 04:06:52 PM PDT 24
Finished Apr 25 04:34:44 PM PDT 24
Peak memory 345552 kb
Host smart-80212a3d-ad81-41a3-ade1-1ed8990aab33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2989637702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.2989637702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.4132508498
Short name T910
Test name
Test status
Simulation time 34797636217 ps
CPU time 1303.05 seconds
Started Apr 25 04:06:53 PM PDT 24
Finished Apr 25 04:28:37 PM PDT 24
Peak memory 297964 kb
Host smart-3465bd1e-2ab6-4320-acba-d5217a009517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4132508498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.4132508498 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.2707145717
Short name T204
Test name
Test status
Simulation time 1228091224145 ps
CPU time 5697.97 seconds
Started Apr 25 04:06:52 PM PDT 24
Finished Apr 25 05:41:51 PM PDT 24
Peak memory 649448 kb
Host smart-2fd380a7-87f8-4059-8d14-a51573325dc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2707145717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.2707145717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.1379028789
Short name T662
Test name
Test status
Simulation time 745361225903 ps
CPU time 4033.34 seconds
Started Apr 25 04:06:53 PM PDT 24
Finished Apr 25 05:14:07 PM PDT 24
Peak memory 563164 kb
Host smart-744ec605-5a6e-4d0a-9506-9aee3c574acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1379028789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.1379028789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.3242470709
Short name T707
Test name
Test status
Simulation time 31321386 ps
CPU time 0.87 seconds
Started Apr 25 04:07:26 PM PDT 24
Finished Apr 25 04:07:27 PM PDT 24
Peak memory 217900 kb
Host smart-6edf38bc-42e4-4c5d-ac01-7494ccab9094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242470709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.3242470709 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.2034754422
Short name T437
Test name
Test status
Simulation time 20209812020 ps
CPU time 299.19 seconds
Started Apr 25 04:07:16 PM PDT 24
Finished Apr 25 04:12:16 PM PDT 24
Peak memory 247620 kb
Host smart-659b8bd0-2b31-4ca7-8d8f-76ed9862151f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034754422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.2034754422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.3565219825
Short name T563
Test name
Test status
Simulation time 58032933631 ps
CPU time 1551.07 seconds
Started Apr 25 04:07:01 PM PDT 24
Finished Apr 25 04:32:53 PM PDT 24
Peak memory 240472 kb
Host smart-80227bb4-49dc-400c-8ac4-0dc5792886e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565219825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.3565219825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.1090877671
Short name T631
Test name
Test status
Simulation time 13402104360 ps
CPU time 71.08 seconds
Started Apr 25 04:07:16 PM PDT 24
Finished Apr 25 04:08:27 PM PDT 24
Peak memory 229388 kb
Host smart-c657a448-bb35-473d-be53-345881d65e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090877671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.1090877671 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.1750243585
Short name T413
Test name
Test status
Simulation time 18385085434 ps
CPU time 401.82 seconds
Started Apr 25 04:07:24 PM PDT 24
Finished Apr 25 04:14:06 PM PDT 24
Peak memory 259164 kb
Host smart-01405904-3dcf-4832-9516-0d34ab4694a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750243585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.1750243585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.5329463
Short name T16
Test name
Test status
Simulation time 466895895 ps
CPU time 3.21 seconds
Started Apr 25 04:07:22 PM PDT 24
Finished Apr 25 04:07:25 PM PDT 24
Peak memory 218108 kb
Host smart-2a2ad799-ffcb-4e8b-bf74-d183a61b94b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5329463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.5329463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.1039473944
Short name T729
Test name
Test status
Simulation time 95343913 ps
CPU time 1.41 seconds
Started Apr 25 04:07:20 PM PDT 24
Finished Apr 25 04:07:22 PM PDT 24
Peak memory 218228 kb
Host smart-f4dda21c-843f-4191-b5e0-09bf82cb070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039473944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1039473944 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.2738658100
Short name T553
Test name
Test status
Simulation time 134700966170 ps
CPU time 823.86 seconds
Started Apr 25 04:06:57 PM PDT 24
Finished Apr 25 04:20:42 PM PDT 24
Peak memory 286796 kb
Host smart-54df12a8-1ba6-4bcc-948a-0fa3864a44df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738658100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.2738658100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.3276551554
Short name T219
Test name
Test status
Simulation time 25794622748 ps
CPU time 206.96 seconds
Started Apr 25 04:07:01 PM PDT 24
Finished Apr 25 04:10:28 PM PDT 24
Peak memory 239196 kb
Host smart-ac4cb270-6ef1-4a81-98a6-9e3fe109a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276551554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3276551554 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.417633171
Short name T989
Test name
Test status
Simulation time 3393639000 ps
CPU time 35.43 seconds
Started Apr 25 04:06:57 PM PDT 24
Finished Apr 25 04:07:33 PM PDT 24
Peak memory 222948 kb
Host smart-256a82de-d820-46ed-9543-27e051725321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417633171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.417633171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.214034459
Short name T480
Test name
Test status
Simulation time 60629794891 ps
CPU time 1837.2 seconds
Started Apr 25 04:07:20 PM PDT 24
Finished Apr 25 04:37:58 PM PDT 24
Peak memory 380664 kb
Host smart-1e3cdafa-a981-4dea-b62e-d81bad4c2393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=214034459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.214034459 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.3998739609
Short name T592
Test name
Test status
Simulation time 1712552437 ps
CPU time 6.19 seconds
Started Apr 25 04:07:11 PM PDT 24
Finished Apr 25 04:07:17 PM PDT 24
Peak memory 218188 kb
Host smart-394c5f7b-15cd-4e72-ab75-c89cb40ad37d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998739609 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.3998739609 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.2732010535
Short name T503
Test name
Test status
Simulation time 471069868 ps
CPU time 7.18 seconds
Started Apr 25 04:07:10 PM PDT 24
Finished Apr 25 04:07:17 PM PDT 24
Peak memory 218176 kb
Host smart-3fa6ed98-dfed-4ef9-b8f4-e49a6e207eda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732010535 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.2732010535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.2161823944
Short name T137
Test name
Test status
Simulation time 807901445669 ps
CPU time 2398.8 seconds
Started Apr 25 04:07:00 PM PDT 24
Finished Apr 25 04:46:59 PM PDT 24
Peak memory 392048 kb
Host smart-7e4ffefc-995a-48c8-b0ef-7478406af421
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2161823944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.2161823944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.563811503
Short name T444
Test name
Test status
Simulation time 254732099481 ps
CPU time 2051.5 seconds
Started Apr 25 04:07:01 PM PDT 24
Finished Apr 25 04:41:13 PM PDT 24
Peak memory 385692 kb
Host smart-9a67c951-d5a1-433a-8e8c-c44bc1aadbc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=563811503 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.563811503 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3152079613
Short name T630
Test name
Test status
Simulation time 792557519582 ps
CPU time 2125.89 seconds
Started Apr 25 04:07:01 PM PDT 24
Finished Apr 25 04:42:27 PM PDT 24
Peak memory 343164 kb
Host smart-1cf4597d-d684-4328-8561-8dac0a6507d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3152079613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3152079613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.3853513625
Short name T199
Test name
Test status
Simulation time 277921124507 ps
CPU time 1383.32 seconds
Started Apr 25 04:07:05 PM PDT 24
Finished Apr 25 04:30:09 PM PDT 24
Peak memory 301696 kb
Host smart-4cc3706e-e96d-4058-a832-247800fe19c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3853513625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.3853513625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.701384835
Short name T953
Test name
Test status
Simulation time 352026388725 ps
CPU time 5451.75 seconds
Started Apr 25 04:07:06 PM PDT 24
Finished Apr 25 05:37:59 PM PDT 24
Peak memory 647176 kb
Host smart-05f83c9b-7750-427d-af04-89288bfbd9ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=701384835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.701384835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.2047043633
Short name T620
Test name
Test status
Simulation time 155170131817 ps
CPU time 4136.41 seconds
Started Apr 25 04:07:10 PM PDT 24
Finished Apr 25 05:16:07 PM PDT 24
Peak memory 558160 kb
Host smart-965421a6-7e15-4d6a-9cab-107b17e16247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2047043633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.2047043633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.626449403
Short name T457
Test name
Test status
Simulation time 17204008 ps
CPU time 0.84 seconds
Started Apr 25 04:07:40 PM PDT 24
Finished Apr 25 04:07:41 PM PDT 24
Peak memory 217904 kb
Host smart-c35d62d3-2f3d-4bad-b0d5-dc31ca1a6a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626449403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.626449403 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.3399304801
Short name T970
Test name
Test status
Simulation time 2169986880 ps
CPU time 3.64 seconds
Started Apr 25 04:07:34 PM PDT 24
Finished Apr 25 04:07:38 PM PDT 24
Peak memory 218340 kb
Host smart-10a17907-a744-4ad7-a116-1d4561ef3f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399304801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3399304801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.1010997664
Short name T424
Test name
Test status
Simulation time 4949086557 ps
CPU time 191.78 seconds
Started Apr 25 04:07:32 PM PDT 24
Finished Apr 25 04:10:44 PM PDT 24
Peak memory 228288 kb
Host smart-2f09ffb2-21de-4311-803d-fd8eac65307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010997664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.1010997664 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.1122070744
Short name T932
Test name
Test status
Simulation time 5767350229 ps
CPU time 421.18 seconds
Started Apr 25 04:07:34 PM PDT 24
Finished Apr 25 04:14:36 PM PDT 24
Peak memory 253924 kb
Host smart-63b1664c-5bfa-4cfa-9e47-08f98d25bb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122070744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.1122070744 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.2051656877
Short name T806
Test name
Test status
Simulation time 9879908774 ps
CPU time 156.59 seconds
Started Apr 25 04:07:37 PM PDT 24
Finished Apr 25 04:10:14 PM PDT 24
Peak memory 250940 kb
Host smart-65ff6ab2-31f3-41e2-bdb2-8c2959692ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051656877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.2051656877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.4271709970
Short name T1055
Test name
Test status
Simulation time 1624410824 ps
CPU time 3.66 seconds
Started Apr 25 04:07:35 PM PDT 24
Finished Apr 25 04:07:39 PM PDT 24
Peak memory 218080 kb
Host smart-06a238e5-9e4f-4734-817e-2c9caf3c2b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271709970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.4271709970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2646044435
Short name T1004
Test name
Test status
Simulation time 102579740 ps
CPU time 1.21 seconds
Started Apr 25 04:07:33 PM PDT 24
Finished Apr 25 04:07:35 PM PDT 24
Peak memory 218148 kb
Host smart-717dc0a6-8aa6-4afa-ac1e-cac2f3683a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646044435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2646044435 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.2204712230
Short name T1061
Test name
Test status
Simulation time 297371287363 ps
CPU time 2596.91 seconds
Started Apr 25 04:07:24 PM PDT 24
Finished Apr 25 04:50:42 PM PDT 24
Peak memory 441676 kb
Host smart-3fc675ef-bd84-47eb-82c1-f5f129cad85b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204712230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_a
nd_output.2204712230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.2992055781
Short name T1007
Test name
Test status
Simulation time 3537342657 ps
CPU time 116.73 seconds
Started Apr 25 04:07:24 PM PDT 24
Finished Apr 25 04:09:21 PM PDT 24
Peak memory 232648 kb
Host smart-6cc200fc-5dd9-4cd8-b5c1-dc59428de9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992055781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.2992055781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.1219486881
Short name T565
Test name
Test status
Simulation time 7919785350 ps
CPU time 28.79 seconds
Started Apr 25 04:07:24 PM PDT 24
Finished Apr 25 04:07:53 PM PDT 24
Peak memory 226340 kb
Host smart-3f8b106e-58d6-415a-a36d-f157b87ba976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219486881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1219486881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.8714930
Short name T455
Test name
Test status
Simulation time 69405328619 ps
CPU time 1594.62 seconds
Started Apr 25 04:07:42 PM PDT 24
Finished Apr 25 04:34:17 PM PDT 24
Peak memory 388184 kb
Host smart-138fc91e-9cb8-430b-9672-984c9ff32afa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=8714930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.8714930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_stress_all_with_rand_reset.176839652
Short name T132
Test name
Test status
Simulation time 218015772446 ps
CPU time 1598.28 seconds
Started Apr 25 04:07:40 PM PDT 24
Finished Apr 25 04:34:19 PM PDT 24
Peak memory 285240 kb
Host smart-21181130-ec29-4ed1-aa8c-86e6e46863a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176839652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.176839652 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1974735232
Short name T1060
Test name
Test status
Simulation time 275608071 ps
CPU time 6.52 seconds
Started Apr 25 04:07:34 PM PDT 24
Finished Apr 25 04:07:41 PM PDT 24
Peak memory 219140 kb
Host smart-db1ff6c4-9a6d-47ee-abcb-50c15e810e8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974735232 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1974735232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1322308608
Short name T475
Test name
Test status
Simulation time 374317489 ps
CPU time 5.76 seconds
Started Apr 25 04:07:35 PM PDT 24
Finished Apr 25 04:07:41 PM PDT 24
Peak memory 218216 kb
Host smart-29bb47e4-7b58-4376-9993-a8e6c1568ddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322308608 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1322308608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.3286135491
Short name T941
Test name
Test status
Simulation time 82982727836 ps
CPU time 1946 seconds
Started Apr 25 04:07:32 PM PDT 24
Finished Apr 25 04:39:59 PM PDT 24
Peak memory 389148 kb
Host smart-6afd3f02-3220-4250-8d26-2b2a779237eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3286135491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.3286135491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.736572612
Short name T684
Test name
Test status
Simulation time 150786789480 ps
CPU time 2096.99 seconds
Started Apr 25 04:07:30 PM PDT 24
Finished Apr 25 04:42:28 PM PDT 24
Peak memory 383848 kb
Host smart-474fa1b3-0973-4b88-9ed0-29be8a98b629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=736572612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.736572612 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.4020441817
Short name T900
Test name
Test status
Simulation time 99215250293 ps
CPU time 1744.22 seconds
Started Apr 25 04:07:30 PM PDT 24
Finished Apr 25 04:36:35 PM PDT 24
Peak memory 340108 kb
Host smart-54027fa2-b08a-467e-9a52-c75f24ad1465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4020441817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.4020441817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.3713871720
Short name T533
Test name
Test status
Simulation time 42891145093 ps
CPU time 1301.57 seconds
Started Apr 25 04:07:31 PM PDT 24
Finished Apr 25 04:29:13 PM PDT 24
Peak memory 300900 kb
Host smart-f93a8473-1725-4fef-8c9c-a50b71c84d42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3713871720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.3713871720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1410087064
Short name T224
Test name
Test status
Simulation time 250796869450 ps
CPU time 4517.08 seconds
Started Apr 25 04:07:30 PM PDT 24
Finished Apr 25 05:22:48 PM PDT 24
Peak memory 651616 kb
Host smart-9a2082ef-b351-438c-b7f4-c5608f1c1eb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1410087064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1410087064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.2352491302
Short name T450
Test name
Test status
Simulation time 220466090555 ps
CPU time 4163.73 seconds
Started Apr 25 04:07:35 PM PDT 24
Finished Apr 25 05:17:00 PM PDT 24
Peak memory 572772 kb
Host smart-c8e14585-d60b-48ca-9c40-585010fa0b77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2352491302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2352491302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.2028794608
Short name T755
Test name
Test status
Simulation time 18223120 ps
CPU time 0.81 seconds
Started Apr 25 04:08:10 PM PDT 24
Finished Apr 25 04:08:11 PM PDT 24
Peak memory 217880 kb
Host smart-171bdbf3-31fc-47c4-b07c-05711ee1fbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028794608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.2028794608 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.910072162
Short name T632
Test name
Test status
Simulation time 17633875471 ps
CPU time 128.21 seconds
Started Apr 25 04:07:58 PM PDT 24
Finished Apr 25 04:10:07 PM PDT 24
Peak memory 233772 kb
Host smart-80bd89f4-cb22-48ff-9adb-90e33b1a810f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910072162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.910072162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.3155590012
Short name T878
Test name
Test status
Simulation time 11555281144 ps
CPU time 1438.57 seconds
Started Apr 25 04:07:49 PM PDT 24
Finished Apr 25 04:31:49 PM PDT 24
Peak memory 242712 kb
Host smart-e74c6c14-5972-48ec-aa69-a3bffd980bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155590012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.3155590012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.839087044
Short name T872
Test name
Test status
Simulation time 23229744099 ps
CPU time 132.65 seconds
Started Apr 25 04:08:02 PM PDT 24
Finished Apr 25 04:10:15 PM PDT 24
Peak memory 242700 kb
Host smart-8b583200-277b-4616-b99d-3f3363340eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839087044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.839087044 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.3647718909
Short name T1040
Test name
Test status
Simulation time 52792142538 ps
CPU time 464.32 seconds
Started Apr 25 04:08:02 PM PDT 24
Finished Apr 25 04:15:47 PM PDT 24
Peak memory 265280 kb
Host smart-6c8a3166-6e79-419c-9d80-48d78b9cdc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647718909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3647718909 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.2053474222
Short name T453
Test name
Test status
Simulation time 578832163 ps
CPU time 4.19 seconds
Started Apr 25 04:08:02 PM PDT 24
Finished Apr 25 04:08:07 PM PDT 24
Peak memory 218096 kb
Host smart-98df02c9-d010-4246-84b6-78487a10a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053474222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.2053474222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.418137576
Short name T556
Test name
Test status
Simulation time 3510604636 ps
CPU time 22.07 seconds
Started Apr 25 04:08:05 PM PDT 24
Finished Apr 25 04:08:27 PM PDT 24
Peak memory 234616 kb
Host smart-103c15f9-05c1-4fe4-85f0-fa69a9718449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418137576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.418137576 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.764467957
Short name T404
Test name
Test status
Simulation time 71306160675 ps
CPU time 1745.97 seconds
Started Apr 25 04:07:45 PM PDT 24
Finished Apr 25 04:36:52 PM PDT 24
Peak memory 361852 kb
Host smart-d8172dbc-ac72-4622-a2dc-0bc1f29dffd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764467957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_an
d_output.764467957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1743504248
Short name T844
Test name
Test status
Simulation time 5463999434 ps
CPU time 407.27 seconds
Started Apr 25 04:07:45 PM PDT 24
Finished Apr 25 04:14:33 PM PDT 24
Peak memory 252468 kb
Host smart-8cd289b3-6a8d-4355-a887-814b9a4a22cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743504248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1743504248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.2678217812
Short name T716
Test name
Test status
Simulation time 4409276543 ps
CPU time 45.45 seconds
Started Apr 25 04:07:45 PM PDT 24
Finished Apr 25 04:08:31 PM PDT 24
Peak memory 226368 kb
Host smart-59218daf-5860-4ac7-a4f2-7b7e4dba3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678217812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.2678217812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_stress_all.1063540272
Short name T460
Test name
Test status
Simulation time 27653958087 ps
CPU time 704.99 seconds
Started Apr 25 04:08:08 PM PDT 24
Finished Apr 25 04:19:54 PM PDT 24
Peak memory 312584 kb
Host smart-e064b008-5f6a-47b0-8064-8bb6a8ddad4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1063540272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.1063540272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3337035012
Short name T641
Test name
Test status
Simulation time 112175324 ps
CPU time 6.56 seconds
Started Apr 25 04:07:55 PM PDT 24
Finished Apr 25 04:08:02 PM PDT 24
Peak memory 218204 kb
Host smart-8f86c738-2e78-48de-9e77-1046a026713c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337035012 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3337035012 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2471845601
Short name T373
Test name
Test status
Simulation time 526702915 ps
CPU time 6.24 seconds
Started Apr 25 04:07:57 PM PDT 24
Finished Apr 25 04:08:04 PM PDT 24
Peak memory 218252 kb
Host smart-d511f7e9-35f5-4992-b6f9-15d20e7b0946
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471845601 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2471845601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.3205139995
Short name T789
Test name
Test status
Simulation time 275670244283 ps
CPU time 2348.56 seconds
Started Apr 25 04:07:49 PM PDT 24
Finished Apr 25 04:46:59 PM PDT 24
Peak memory 399132 kb
Host smart-6c362e18-f6e8-4cc4-92a6-6ecc58115ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3205139995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.3205139995 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.3595814315
Short name T642
Test name
Test status
Simulation time 22888804251 ps
CPU time 1769.99 seconds
Started Apr 25 04:07:45 PM PDT 24
Finished Apr 25 04:37:17 PM PDT 24
Peak memory 386896 kb
Host smart-35f8538c-2a83-4376-9fbf-b31ee3b6179f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3595814315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3595814315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.3238070920
Short name T753
Test name
Test status
Simulation time 33609657049 ps
CPU time 1479.91 seconds
Started Apr 25 04:07:51 PM PDT 24
Finished Apr 25 04:32:32 PM PDT 24
Peak memory 332656 kb
Host smart-f0252ca9-346b-48b1-aac5-dbc2db8178f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3238070920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.3238070920 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.553701786
Short name T351
Test name
Test status
Simulation time 40101949712 ps
CPU time 1123.38 seconds
Started Apr 25 04:07:51 PM PDT 24
Finished Apr 25 04:26:36 PM PDT 24
Peak memory 298412 kb
Host smart-2a70b925-0e8f-4e12-afa3-440f34ac1549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=553701786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.553701786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.2569083737
Short name T1039
Test name
Test status
Simulation time 203643119744 ps
CPU time 4436.51 seconds
Started Apr 25 04:07:58 PM PDT 24
Finished Apr 25 05:21:55 PM PDT 24
Peak memory 579708 kb
Host smart-0b6f3c43-6d95-4a6e-8cec-26594ad58564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2569083737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2569083737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.2403148935
Short name T220
Test name
Test status
Simulation time 50115322 ps
CPU time 0.81 seconds
Started Apr 25 04:08:29 PM PDT 24
Finished Apr 25 04:08:30 PM PDT 24
Peak memory 217816 kb
Host smart-a3279f60-e87e-4f49-a533-9f58aad8bd3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403148935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.2403148935 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.3751679648
Short name T1052
Test name
Test status
Simulation time 73757162552 ps
CPU time 400.57 seconds
Started Apr 25 04:08:19 PM PDT 24
Finished Apr 25 04:15:01 PM PDT 24
Peak memory 250948 kb
Host smart-593b5e13-42c4-446e-bb0e-daa9cade0a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751679648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.3751679648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.2361454500
Short name T1049
Test name
Test status
Simulation time 45580985941 ps
CPU time 866.2 seconds
Started Apr 25 04:08:13 PM PDT 24
Finished Apr 25 04:22:40 PM PDT 24
Peak memory 235356 kb
Host smart-959c3389-955e-4c37-8450-d058dc38a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361454500 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.2361454500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_entropy_refresh.1378912529
Short name T541
Test name
Test status
Simulation time 26829471884 ps
CPU time 455.28 seconds
Started Apr 25 04:08:20 PM PDT 24
Finished Apr 25 04:15:56 PM PDT 24
Peak memory 252148 kb
Host smart-e70610b7-4dc2-445b-8c71-320807530998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378912529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.1378912529 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/36.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/36.kmac_error.3037348956
Short name T139
Test name
Test status
Simulation time 3609581305 ps
CPU time 76.51 seconds
Started Apr 25 04:08:24 PM PDT 24
Finished Apr 25 04:09:41 PM PDT 24
Peak memory 242768 kb
Host smart-2925278f-08e6-4dc5-9b82-c27c89dcd4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037348956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3037348956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.1842943943
Short name T542
Test name
Test status
Simulation time 1228242045 ps
CPU time 4.42 seconds
Started Apr 25 04:08:25 PM PDT 24
Finished Apr 25 04:08:30 PM PDT 24
Peak memory 218100 kb
Host smart-6f7b6bc3-1647-454f-8fef-c4532960d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842943943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.1842943943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.2277454445
Short name T676
Test name
Test status
Simulation time 2067839385 ps
CPU time 231.92 seconds
Started Apr 25 04:08:10 PM PDT 24
Finished Apr 25 04:12:03 PM PDT 24
Peak memory 242688 kb
Host smart-8098ea38-04a5-48ff-9068-175aa7ed4602
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277454445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.2277454445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.1107607972
Short name T195
Test name
Test status
Simulation time 5895583752 ps
CPU time 489.18 seconds
Started Apr 25 04:08:10 PM PDT 24
Finished Apr 25 04:16:20 PM PDT 24
Peak memory 255076 kb
Host smart-2ee7542a-9fa4-4ac4-9cc4-04980b5da229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107607972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.1107607972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.2584601660
Short name T819
Test name
Test status
Simulation time 3396290393 ps
CPU time 85.45 seconds
Started Apr 25 04:08:10 PM PDT 24
Finished Apr 25 04:09:36 PM PDT 24
Peak memory 218260 kb
Host smart-90c1cd29-5cc8-4fd3-a732-4d04ada298cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584601660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.2584601660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all.49092430
Short name T375
Test name
Test status
Simulation time 17364869473 ps
CPU time 114.03 seconds
Started Apr 25 04:08:25 PM PDT 24
Finished Apr 25 04:10:20 PM PDT 24
Peak memory 242704 kb
Host smart-251b3322-12e2-40fa-8936-3a33619bc0f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=49092430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.49092430 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.1019388262
Short name T966
Test name
Test status
Simulation time 653713683 ps
CPU time 6.49 seconds
Started Apr 25 04:08:18 PM PDT 24
Finished Apr 25 04:08:26 PM PDT 24
Peak memory 218236 kb
Host smart-ab93d606-666f-472a-b96d-ffd2ec69709f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019388262 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.1019388262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.959281453
Short name T690
Test name
Test status
Simulation time 388916224 ps
CPU time 6.11 seconds
Started Apr 25 04:08:19 PM PDT 24
Finished Apr 25 04:08:26 PM PDT 24
Peak memory 219156 kb
Host smart-1142bc90-beed-4e66-a2f2-c650ed5371d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959281453 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.kmac_test_vectors_kmac_xof.959281453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.1425237454
Short name T1064
Test name
Test status
Simulation time 39600218130 ps
CPU time 1969.88 seconds
Started Apr 25 04:08:20 PM PDT 24
Finished Apr 25 04:41:11 PM PDT 24
Peak memory 387104 kb
Host smart-da472631-4ea5-4131-9f16-7ea08ecee309
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1425237454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.1425237454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.342371440
Short name T807
Test name
Test status
Simulation time 189030839762 ps
CPU time 2413.99 seconds
Started Apr 25 04:08:15 PM PDT 24
Finished Apr 25 04:48:30 PM PDT 24
Peak memory 382248 kb
Host smart-a1614bb6-9990-4c2d-9900-49b7408b560d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=342371440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.342371440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.4012681567
Short name T428
Test name
Test status
Simulation time 206909945661 ps
CPU time 1745.52 seconds
Started Apr 25 04:08:14 PM PDT 24
Finished Apr 25 04:37:20 PM PDT 24
Peak memory 339808 kb
Host smart-b97a0cb2-c7a9-4bbb-b7cc-7b61fc57acb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4012681567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.4012681567 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.4086857035
Short name T13
Test name
Test status
Simulation time 33850484597 ps
CPU time 1315.67 seconds
Started Apr 25 04:08:13 PM PDT 24
Finished Apr 25 04:30:10 PM PDT 24
Peak memory 303020 kb
Host smart-adc127f7-df22-48c4-a929-9a2951eacb7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4086857035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.4086857035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.1706406559
Short name T429
Test name
Test status
Simulation time 383365226352 ps
CPU time 5972.96 seconds
Started Apr 25 04:08:15 PM PDT 24
Finished Apr 25 05:47:50 PM PDT 24
Peak memory 683424 kb
Host smart-9dbbccf1-3564-4572-ba65-e6fa27e1b2fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1706406559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.1706406559 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.3197252361
Short name T222
Test name
Test status
Simulation time 445048959916 ps
CPU time 5179.25 seconds
Started Apr 25 04:08:18 PM PDT 24
Finished Apr 25 05:34:39 PM PDT 24
Peak memory 567168 kb
Host smart-a281a139-c8e4-4a75-ba80-9eaa81dc645f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3197252361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.3197252361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.324814671
Short name T886
Test name
Test status
Simulation time 27958928 ps
CPU time 0.87 seconds
Started Apr 25 04:08:58 PM PDT 24
Finished Apr 25 04:09:00 PM PDT 24
Peak memory 217892 kb
Host smart-bd801c04-0f97-4783-81d2-2b5decb5be18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324814671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.324814671 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.1809789873
Short name T809
Test name
Test status
Simulation time 11953554208 ps
CPU time 287.57 seconds
Started Apr 25 04:08:48 PM PDT 24
Finished Apr 25 04:13:36 PM PDT 24
Peak memory 246584 kb
Host smart-464c08a7-0dab-4e3c-943e-8bb18068194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809789873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.1809789873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.4039219152
Short name T150
Test name
Test status
Simulation time 5541327837 ps
CPU time 288.48 seconds
Started Apr 25 04:08:38 PM PDT 24
Finished Apr 25 04:13:27 PM PDT 24
Peak memory 237508 kb
Host smart-0d8a8230-653a-4ec0-ad68-067ca32ad50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039219152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.4039219152 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.2667559336
Short name T304
Test name
Test status
Simulation time 9567383737 ps
CPU time 229.56 seconds
Started Apr 25 04:08:48 PM PDT 24
Finished Apr 25 04:12:38 PM PDT 24
Peak memory 240772 kb
Host smart-1cbf2425-9435-49ee-b1a6-4cc2da35e1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667559336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.2667559336 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.4146225603
Short name T298
Test name
Test status
Simulation time 18362643532 ps
CPU time 125.34 seconds
Started Apr 25 04:08:49 PM PDT 24
Finished Apr 25 04:10:54 PM PDT 24
Peak memory 252340 kb
Host smart-bf92681b-8115-4acc-b147-5f97aa80b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146225603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.4146225603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1823582673
Short name T107
Test name
Test status
Simulation time 883443715 ps
CPU time 1.75 seconds
Started Apr 25 04:08:48 PM PDT 24
Finished Apr 25 04:08:50 PM PDT 24
Peak memory 218016 kb
Host smart-4705a85f-68ed-4564-8623-89e32602334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823582673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1823582673 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.402656625
Short name T1063
Test name
Test status
Simulation time 81978586 ps
CPU time 1.35 seconds
Started Apr 25 04:08:53 PM PDT 24
Finished Apr 25 04:08:55 PM PDT 24
Peak memory 218104 kb
Host smart-e2252ab8-b511-4e04-8f16-66625a8ac187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402656625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.402656625 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.378646752
Short name T509
Test name
Test status
Simulation time 8594988384 ps
CPU time 512.44 seconds
Started Apr 25 04:08:39 PM PDT 24
Finished Apr 25 04:17:12 PM PDT 24
Peak memory 261380 kb
Host smart-4f199176-5adc-42ee-a4a2-066a6fa83cec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378646752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_an
d_output.378646752 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.747280912
Short name T1054
Test name
Test status
Simulation time 1505569066 ps
CPU time 130.84 seconds
Started Apr 25 04:08:39 PM PDT 24
Finished Apr 25 04:10:50 PM PDT 24
Peak memory 230768 kb
Host smart-0a592763-8a65-45e0-b618-0cfdf3244175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747280912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.747280912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.3859666220
Short name T1027
Test name
Test status
Simulation time 13609692421 ps
CPU time 88.63 seconds
Started Apr 25 04:08:37 PM PDT 24
Finished Apr 25 04:10:07 PM PDT 24
Peak memory 226300 kb
Host smart-de259a79-fd05-480e-b883-e0dcfa04fa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859666220 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3859666220 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_stress_all.2447035676
Short name T763
Test name
Test status
Simulation time 47791467070 ps
CPU time 1429.94 seconds
Started Apr 25 04:08:54 PM PDT 24
Finished Apr 25 04:32:44 PM PDT 24
Peak memory 332616 kb
Host smart-12ece486-7a1e-489f-bb50-95ea3b0adf8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2447035676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2447035676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_stress_all/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.1612647118
Short name T289
Test name
Test status
Simulation time 1053600089 ps
CPU time 6.28 seconds
Started Apr 25 04:08:42 PM PDT 24
Finished Apr 25 04:08:49 PM PDT 24
Peak memory 218220 kb
Host smart-d9f3805e-9721-4a12-85ec-2ab2063d5b57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612647118 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.kmac_test_vectors_kmac.1612647118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.3458865404
Short name T340
Test name
Test status
Simulation time 443411704 ps
CPU time 6.56 seconds
Started Apr 25 04:08:48 PM PDT 24
Finished Apr 25 04:08:55 PM PDT 24
Peak memory 218260 kb
Host smart-39b2f177-f93d-4baf-92b3-0b84af805f09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458865404 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.3458865404 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.3718888679
Short name T614
Test name
Test status
Simulation time 69808638444 ps
CPU time 2037.99 seconds
Started Apr 25 04:08:42 PM PDT 24
Finished Apr 25 04:42:41 PM PDT 24
Peak memory 392956 kb
Host smart-3f3653b8-ca60-40b8-afed-7e572a3b8730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3718888679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.3718888679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.35938347
Short name T301
Test name
Test status
Simulation time 19352600989 ps
CPU time 1946.96 seconds
Started Apr 25 04:08:37 PM PDT 24
Finished Apr 25 04:41:04 PM PDT 24
Peak memory 388024 kb
Host smart-1d04f8ba-ddf5-4470-966d-ddfe62c0f87c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=35938347 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.35938347 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.2228637848
Short name T354
Test name
Test status
Simulation time 15140306171 ps
CPU time 1490.9 seconds
Started Apr 25 04:08:43 PM PDT 24
Finished Apr 25 04:33:35 PM PDT 24
Peak memory 330884 kb
Host smart-0251f950-6051-458c-8901-5a9dedd260de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2228637848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.2228637848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.689425401
Short name T225
Test name
Test status
Simulation time 11198221761 ps
CPU time 1142.75 seconds
Started Apr 25 04:08:42 PM PDT 24
Finished Apr 25 04:27:46 PM PDT 24
Peak memory 297584 kb
Host smart-cce847e4-f95e-43d6-af1e-3a2eb0ed3ef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=689425401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.689425401 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.3506232300
Short name T709
Test name
Test status
Simulation time 3664810347639 ps
CPU time 5983.44 seconds
Started Apr 25 04:08:42 PM PDT 24
Finished Apr 25 05:48:27 PM PDT 24
Peak memory 640996 kb
Host smart-6c24b922-accd-44b3-ad95-eac424e0a861
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3506232300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.3506232300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3525652029
Short name T934
Test name
Test status
Simulation time 1516680877644 ps
CPU time 4672.23 seconds
Started Apr 25 04:08:44 PM PDT 24
Finished Apr 25 05:26:37 PM PDT 24
Peak memory 570656 kb
Host smart-0b64a045-0710-4d59-8492-fb66d8d9e50f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3525652029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3525652029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.1324153827
Short name T938
Test name
Test status
Simulation time 31614155 ps
CPU time 0.81 seconds
Started Apr 25 04:09:21 PM PDT 24
Finished Apr 25 04:09:23 PM PDT 24
Peak memory 217908 kb
Host smart-f6e93f87-a8e2-4c6f-aa1a-64df2f51c42b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324153827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1324153827 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.1188367589
Short name T336
Test name
Test status
Simulation time 4934968741 ps
CPU time 336.47 seconds
Started Apr 25 04:09:10 PM PDT 24
Finished Apr 25 04:14:47 PM PDT 24
Peak memory 249456 kb
Host smart-0788b3a4-bca0-4b17-8056-19ad1ac6a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188367589 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.1188367589 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.2278932069
Short name T983
Test name
Test status
Simulation time 3725326109 ps
CPU time 103.07 seconds
Started Apr 25 04:09:05 PM PDT 24
Finished Apr 25 04:10:49 PM PDT 24
Peak memory 234536 kb
Host smart-716c60f8-b90f-4298-ab56-a2152ad33f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278932069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.2278932069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.2815859107
Short name T451
Test name
Test status
Simulation time 4411352512 ps
CPU time 11.38 seconds
Started Apr 25 04:09:16 PM PDT 24
Finished Apr 25 04:09:28 PM PDT 24
Peak memory 236196 kb
Host smart-53abeca9-3161-48e2-bb9d-855a415ab39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815859107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2815859107 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.1539588340
Short name T408
Test name
Test status
Simulation time 14460583761 ps
CPU time 117.56 seconds
Started Apr 25 04:09:16 PM PDT 24
Finished Apr 25 04:11:15 PM PDT 24
Peak memory 242820 kb
Host smart-776115b4-1e71-499b-9896-23c6b05318bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539588340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.1539588340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.531895646
Short name T367
Test name
Test status
Simulation time 5002750758 ps
CPU time 6.58 seconds
Started Apr 25 04:09:18 PM PDT 24
Finished Apr 25 04:09:25 PM PDT 24
Peak memory 218064 kb
Host smart-eb5b4bca-a8b0-44e5-9034-3c469f256049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531895646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.531895646 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.3111448289
Short name T23
Test name
Test status
Simulation time 534275748 ps
CPU time 1.52 seconds
Started Apr 25 04:09:18 PM PDT 24
Finished Apr 25 04:09:20 PM PDT 24
Peak memory 218112 kb
Host smart-b2c52099-1b78-4e98-822f-37e46ba53134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111448289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3111448289 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.3686142702
Short name T520
Test name
Test status
Simulation time 138529636327 ps
CPU time 1772.67 seconds
Started Apr 25 04:09:04 PM PDT 24
Finished Apr 25 04:38:37 PM PDT 24
Peak memory 358388 kb
Host smart-5855e5d8-966e-4317-ba6a-6974ab35695f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686142702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.3686142702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.1780460695
Short name T575
Test name
Test status
Simulation time 6223920984 ps
CPU time 264.79 seconds
Started Apr 25 04:09:04 PM PDT 24
Finished Apr 25 04:13:30 PM PDT 24
Peak memory 242672 kb
Host smart-92ced5a2-5562-469a-9232-7bc311be30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780460695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.1780460695 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.3955162106
Short name T668
Test name
Test status
Simulation time 3274183507 ps
CPU time 26.06 seconds
Started Apr 25 04:08:57 PM PDT 24
Finished Apr 25 04:09:24 PM PDT 24
Peak memory 218516 kb
Host smart-307864a7-bbdf-4230-a81e-44fdcf293af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955162106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3955162106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.972478234
Short name T821
Test name
Test status
Simulation time 10110439752 ps
CPU time 829.48 seconds
Started Apr 25 04:09:17 PM PDT 24
Finished Apr 25 04:23:07 PM PDT 24
Peak memory 325648 kb
Host smart-95016d6d-abf0-48be-a776-bed73ee4c8d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=972478234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.972478234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_stress_all_with_rand_reset.2335295418
Short name T1014
Test name
Test status
Simulation time 52182407445 ps
CPU time 1607.63 seconds
Started Apr 25 04:09:16 PM PDT 24
Finished Apr 25 04:36:05 PM PDT 24
Peak memory 336728 kb
Host smart-e86f3eea-e858-4f98-ac49-58c114e16e51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2335295418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all_with_rand_reset.2335295418 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.4214582772
Short name T891
Test name
Test status
Simulation time 639171537 ps
CPU time 6.45 seconds
Started Apr 25 04:09:10 PM PDT 24
Finished Apr 25 04:09:17 PM PDT 24
Peak memory 218268 kb
Host smart-6ec75c8b-a683-455a-8e76-d3becafc63fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214582772 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.4214582772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.2439914035
Short name T745
Test name
Test status
Simulation time 753384251 ps
CPU time 6.18 seconds
Started Apr 25 04:09:09 PM PDT 24
Finished Apr 25 04:09:16 PM PDT 24
Peak memory 218132 kb
Host smart-81ee3430-ffe4-4367-842d-b8dc715bef0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439914035 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.2439914035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1794031744
Short name T1043
Test name
Test status
Simulation time 44856255459 ps
CPU time 2020.89 seconds
Started Apr 25 04:09:05 PM PDT 24
Finished Apr 25 04:42:46 PM PDT 24
Peak memory 404060 kb
Host smart-e89e55c1-c209-47e8-8437-180a98d74d72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1794031744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1794031744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.3545598290
Short name T394
Test name
Test status
Simulation time 243933992814 ps
CPU time 2083.56 seconds
Started Apr 25 04:09:04 PM PDT 24
Finished Apr 25 04:43:48 PM PDT 24
Peak memory 381644 kb
Host smart-2a0acc78-7428-499c-9dfc-bf20f476ec99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3545598290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.3545598290 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.3444638400
Short name T477
Test name
Test status
Simulation time 41927290353 ps
CPU time 1456.68 seconds
Started Apr 25 04:09:07 PM PDT 24
Finished Apr 25 04:33:24 PM PDT 24
Peak memory 336600 kb
Host smart-1c76b57d-e274-4468-9549-2fc30c0e4a55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3444638400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.3444638400 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.1570710023
Short name T846
Test name
Test status
Simulation time 10573288362 ps
CPU time 1047.58 seconds
Started Apr 25 04:09:05 PM PDT 24
Finished Apr 25 04:26:34 PM PDT 24
Peak memory 297928 kb
Host smart-efe5e6c4-c2f4-4b98-b747-9b870c6b41b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1570710023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.1570710023 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.2566052457
Short name T312
Test name
Test status
Simulation time 767091326841 ps
CPU time 5271.21 seconds
Started Apr 25 04:09:09 PM PDT 24
Finished Apr 25 05:37:01 PM PDT 24
Peak memory 654628 kb
Host smart-60b2778f-56c6-45e0-b2cb-ae1c2c80501c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2566052457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.2566052457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.3311007448
Short name T300
Test name
Test status
Simulation time 202184863169 ps
CPU time 3882.67 seconds
Started Apr 25 04:09:09 PM PDT 24
Finished Apr 25 05:13:53 PM PDT 24
Peak memory 571024 kb
Host smart-41b02019-8dd5-4b85-86bd-70ab805fe534
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3311007448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.3311007448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.3778395749
Short name T832
Test name
Test status
Simulation time 17444205 ps
CPU time 0.82 seconds
Started Apr 25 04:09:38 PM PDT 24
Finished Apr 25 04:09:40 PM PDT 24
Peak memory 217916 kb
Host smart-8e9dc1ce-ecbd-492d-b8bb-c2fc13d8da20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778395749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.3778395749 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.382906022
Short name T483
Test name
Test status
Simulation time 45324572121 ps
CPU time 177.07 seconds
Started Apr 25 04:09:33 PM PDT 24
Finished Apr 25 04:12:31 PM PDT 24
Peak memory 239172 kb
Host smart-9f8ab45d-a37d-486b-a3df-4cd318f059dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382906022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.382906022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.424639804
Short name T505
Test name
Test status
Simulation time 472886963 ps
CPU time 43.76 seconds
Started Apr 25 04:09:26 PM PDT 24
Finished Apr 25 04:10:11 PM PDT 24
Peak memory 226368 kb
Host smart-6ae276ca-2494-4567-b95d-e38a9256e918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424639804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.424639804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.2528746100
Short name T449
Test name
Test status
Simulation time 47537417860 ps
CPU time 269.96 seconds
Started Apr 25 04:09:33 PM PDT 24
Finished Apr 25 04:14:03 PM PDT 24
Peak memory 243748 kb
Host smart-ac657bdd-ddd3-4156-9239-cb2bba460c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528746100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.2528746100 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.2960419040
Short name T210
Test name
Test status
Simulation time 5345782239 ps
CPU time 34.11 seconds
Started Apr 25 04:09:33 PM PDT 24
Finished Apr 25 04:10:08 PM PDT 24
Peak memory 242420 kb
Host smart-b9e23843-66d6-46e5-a7a2-7c488a3befae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960419040 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.2960419040 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.1821225238
Short name T281
Test name
Test status
Simulation time 1075400404 ps
CPU time 6.2 seconds
Started Apr 25 04:09:33 PM PDT 24
Finished Apr 25 04:09:40 PM PDT 24
Peak memory 218084 kb
Host smart-5c53289e-2127-493d-ba21-ab9bc00d3e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821225238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.1821225238 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.1065386390
Short name T70
Test name
Test status
Simulation time 107618772 ps
CPU time 1.28 seconds
Started Apr 25 04:09:40 PM PDT 24
Finished Apr 25 04:09:42 PM PDT 24
Peak memory 218192 kb
Host smart-b15ef46c-9114-43ca-8392-9514c744867c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065386390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1065386390 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.799340494
Short name T738
Test name
Test status
Simulation time 19021496156 ps
CPU time 345.6 seconds
Started Apr 25 04:09:23 PM PDT 24
Finished Apr 25 04:15:09 PM PDT 24
Peak memory 249780 kb
Host smart-cd71a087-37cd-467c-b080-d41ede56795d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799340494 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_an
d_output.799340494 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.1881245277
Short name T532
Test name
Test status
Simulation time 74052206357 ps
CPU time 494.05 seconds
Started Apr 25 04:09:28 PM PDT 24
Finished Apr 25 04:17:42 PM PDT 24
Peak memory 253828 kb
Host smart-417a08d0-8ea4-4c22-9cca-9b4a2935a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881245277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1881245277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.4148531014
Short name T902
Test name
Test status
Simulation time 438662785 ps
CPU time 16.21 seconds
Started Apr 25 04:09:23 PM PDT 24
Finished Apr 25 04:09:40 PM PDT 24
Peak memory 225712 kb
Host smart-30825263-b125-4946-a0e1-7b586e5d1512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148531014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.4148531014 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.1608183306
Short name T958
Test name
Test status
Simulation time 7619463467 ps
CPU time 342.6 seconds
Started Apr 25 04:09:38 PM PDT 24
Finished Apr 25 04:15:22 PM PDT 24
Peak memory 250988 kb
Host smart-00a45bb4-56c3-4694-bb55-2129fc21f22a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1608183306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.1608183306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.4111424944
Short name T803
Test name
Test status
Simulation time 208294049 ps
CPU time 5.94 seconds
Started Apr 25 04:09:33 PM PDT 24
Finished Apr 25 04:09:40 PM PDT 24
Peak memory 218260 kb
Host smart-7c790d72-0dbb-46e2-b98a-9e8df787fa55
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111424944 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.kmac_test_vectors_kmac.4111424944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2961398365
Short name T435
Test name
Test status
Simulation time 901273284 ps
CPU time 6.46 seconds
Started Apr 25 04:09:37 PM PDT 24
Finished Apr 25 04:09:44 PM PDT 24
Peak memory 218276 kb
Host smart-da6fed03-9a45-4363-abba-a538ac927a2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961398365 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2961398365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2539346600
Short name T865
Test name
Test status
Simulation time 165107008912 ps
CPU time 1936.22 seconds
Started Apr 25 04:09:27 PM PDT 24
Finished Apr 25 04:41:44 PM PDT 24
Peak memory 386492 kb
Host smart-26094f5a-a2b5-4fb2-b182-5362e212e3fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2539346600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2539346600 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.926885850
Short name T559
Test name
Test status
Simulation time 247900817843 ps
CPU time 2207.44 seconds
Started Apr 25 04:09:28 PM PDT 24
Finished Apr 25 04:46:16 PM PDT 24
Peak memory 388704 kb
Host smart-f36e66eb-c53d-4242-bf97-9838b6b9d206
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=926885850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.926885850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.551353492
Short name T406
Test name
Test status
Simulation time 102479499757 ps
CPU time 1737.58 seconds
Started Apr 25 04:09:31 PM PDT 24
Finished Apr 25 04:38:29 PM PDT 24
Peak memory 348856 kb
Host smart-5aeb0252-8c27-4e79-99f9-e58a3965edb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=551353492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.551353492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.1450764318
Short name T389
Test name
Test status
Simulation time 210011765050 ps
CPU time 1175.9 seconds
Started Apr 25 04:09:27 PM PDT 24
Finished Apr 25 04:29:04 PM PDT 24
Peak memory 298744 kb
Host smart-8ad39a51-2e30-4e32-b364-2e7f67862398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1450764318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1450764318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.2081120737
Short name T359
Test name
Test status
Simulation time 260353127476 ps
CPU time 5580.36 seconds
Started Apr 25 04:09:28 PM PDT 24
Finished Apr 25 05:42:30 PM PDT 24
Peak memory 655184 kb
Host smart-255a78ff-2f8c-428c-9842-5f42986a5442
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2081120737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.2081120737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.1495613935
Short name T771
Test name
Test status
Simulation time 1837599872921 ps
CPU time 5254.16 seconds
Started Apr 25 04:09:34 PM PDT 24
Finished Apr 25 05:37:09 PM PDT 24
Peak memory 574784 kb
Host smart-59faa908-6f79-4d79-a5c1-2eb781264700
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1495613935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.1495613935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.1386799794
Short name T827
Test name
Test status
Simulation time 15322894 ps
CPU time 0.84 seconds
Started Apr 25 03:57:00 PM PDT 24
Finished Apr 25 03:57:02 PM PDT 24
Peak memory 217900 kb
Host smart-3528a2af-9e9a-4d7d-8e10-23288091d041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386799794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1386799794 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3712477069
Short name T439
Test name
Test status
Simulation time 1032821728 ps
CPU time 28.48 seconds
Started Apr 25 03:56:49 PM PDT 24
Finished Apr 25 03:57:18 PM PDT 24
Peak memory 226324 kb
Host smart-bd441876-ffcb-4f57-90c5-1762b048e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712477069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3712477069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.3950456284
Short name T141
Test name
Test status
Simulation time 2743488410 ps
CPU time 34.88 seconds
Started Apr 25 03:56:52 PM PDT 24
Finished Apr 25 03:57:27 PM PDT 24
Peak memory 224728 kb
Host smart-f3eb0830-9d94-4d1f-ab89-fd995fd281f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950456284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.3950456284 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.1324209679
Short name T547
Test name
Test status
Simulation time 6844342383 ps
CPU time 162.57 seconds
Started Apr 25 03:56:32 PM PDT 24
Finished Apr 25 03:59:16 PM PDT 24
Peak memory 226908 kb
Host smart-a869b8d1-c41b-435e-81be-8135c44ef9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324209679 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.1324209679 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.598937772
Short name T6
Test name
Test status
Simulation time 150163636 ps
CPU time 5.44 seconds
Started Apr 25 03:56:56 PM PDT 24
Finished Apr 25 03:57:03 PM PDT 24
Peak memory 226128 kb
Host smart-06158dac-4273-4ba0-ad98-a9a43dfb4a72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=598937772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.598937772 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.2045722302
Short name T322
Test name
Test status
Simulation time 73207819 ps
CPU time 1.05 seconds
Started Apr 25 03:56:57 PM PDT 24
Finished Apr 25 03:56:59 PM PDT 24
Peak memory 221600 kb
Host smart-216d5b95-74b0-4c0b-a95a-cbd1e94ec545
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2045722302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2045722302 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.93042604
Short name T1019
Test name
Test status
Simulation time 10756563746 ps
CPU time 34.1 seconds
Started Apr 25 03:56:58 PM PDT 24
Finished Apr 25 03:57:33 PM PDT 24
Peak memory 218292 kb
Host smart-60b1bb5c-c9ff-4224-9e5f-7d009f276860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93042604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.93042604 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.2649420148
Short name T895
Test name
Test status
Simulation time 1396620806 ps
CPU time 61.94 seconds
Started Apr 25 03:56:53 PM PDT 24
Finished Apr 25 03:57:56 PM PDT 24
Peak memory 241880 kb
Host smart-99b9b903-fdd9-4ace-92f3-fcdc21606b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649420148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.2649420148 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.679447762
Short name T784
Test name
Test status
Simulation time 8662491624 ps
CPU time 144.02 seconds
Started Apr 25 03:56:58 PM PDT 24
Finished Apr 25 03:59:22 PM PDT 24
Peak memory 251916 kb
Host smart-6b591a2c-8f0f-49c4-8ef1-7f263e149ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679447762 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.679447762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.3300818728
Short name T358
Test name
Test status
Simulation time 111971170 ps
CPU time 1.52 seconds
Started Apr 25 03:56:57 PM PDT 24
Finished Apr 25 03:56:59 PM PDT 24
Peak memory 226208 kb
Host smart-b0cab5d4-7385-41f7-8461-1776f3469784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300818728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.3300818728 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.790153448
Short name T523
Test name
Test status
Simulation time 152224244361 ps
CPU time 2641.29 seconds
Started Apr 25 03:56:36 PM PDT 24
Finished Apr 25 04:40:38 PM PDT 24
Peak memory 439120 kb
Host smart-8e495f25-32d3-47c8-862a-985ec1389817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790153448 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and
_output.790153448 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.1903709884
Short name T318
Test name
Test status
Simulation time 1636834797 ps
CPU time 14.63 seconds
Started Apr 25 03:56:59 PM PDT 24
Finished Apr 25 03:57:15 PM PDT 24
Peak memory 226520 kb
Host smart-d04cec28-bd95-4e71-bff5-1f3f37dbf201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903709884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1903709884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.2116104224
Short name T20
Test name
Test status
Simulation time 7906456182 ps
CPU time 111.36 seconds
Started Apr 25 03:57:05 PM PDT 24
Finished Apr 25 03:58:57 PM PDT 24
Peak memory 290676 kb
Host smart-51a2cdfd-7958-45af-b25a-3be116001035
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116104224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.2116104224 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2130439271
Short name T572
Test name
Test status
Simulation time 31990003022 ps
CPU time 179.23 seconds
Started Apr 25 03:56:37 PM PDT 24
Finished Apr 25 03:59:37 PM PDT 24
Peak memory 237184 kb
Host smart-91f2f056-f93a-4e46-bd30-8b55bcdd1377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130439271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2130439271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.4048642620
Short name T502
Test name
Test status
Simulation time 2675574679 ps
CPU time 53.18 seconds
Started Apr 25 03:56:35 PM PDT 24
Finished Apr 25 03:57:30 PM PDT 24
Peak memory 220876 kb
Host smart-732ef3eb-ea21-4e28-99aa-ce58a43bb36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048642620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.4048642620 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.3120961022
Short name T39
Test name
Test status
Simulation time 60641941192 ps
CPU time 580.04 seconds
Started Apr 25 03:56:59 PM PDT 24
Finished Apr 25 04:06:39 PM PDT 24
Peak memory 296136 kb
Host smart-0d969c79-e971-4266-826f-2dad35dbcf90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3120961022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.3120961022 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.3430947593
Short name T796
Test name
Test status
Simulation time 807282706 ps
CPU time 5.71 seconds
Started Apr 25 03:56:50 PM PDT 24
Finished Apr 25 03:56:57 PM PDT 24
Peak memory 218256 kb
Host smart-eb46e628-7728-4740-bae2-196dac8284a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430947593 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.kmac_test_vectors_kmac.3430947593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.926445523
Short name T433
Test name
Test status
Simulation time 709205398 ps
CPU time 6.17 seconds
Started Apr 25 03:56:50 PM PDT 24
Finished Apr 25 03:56:57 PM PDT 24
Peak memory 218232 kb
Host smart-f8a78afd-addf-4ac4-80f0-826463d78f41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926445523 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.kmac_test_vectors_kmac_xof.926445523 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.4062170989
Short name T775
Test name
Test status
Simulation time 28072789044 ps
CPU time 1900.41 seconds
Started Apr 25 03:56:37 PM PDT 24
Finished Apr 25 04:28:19 PM PDT 24
Peak memory 396288 kb
Host smart-cbbf1fc9-a706-470d-b36f-593d70e4acfe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4062170989 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.4062170989 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.442217867
Short name T274
Test name
Test status
Simulation time 39284412466 ps
CPU time 2035.76 seconds
Started Apr 25 03:56:41 PM PDT 24
Finished Apr 25 04:30:38 PM PDT 24
Peak memory 388116 kb
Host smart-001cf285-646a-4d24-aa55-e47aee9d869d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=442217867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.442217867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.2251356924
Short name T702
Test name
Test status
Simulation time 30860999015 ps
CPU time 1533.41 seconds
Started Apr 25 03:56:48 PM PDT 24
Finished Apr 25 04:22:22 PM PDT 24
Peak memory 335540 kb
Host smart-a1758a38-756b-453f-bd33-c31d81e87b21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2251356924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2251356924 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3385280115
Short name T513
Test name
Test status
Simulation time 100614550735 ps
CPU time 1355.72 seconds
Started Apr 25 03:56:48 PM PDT 24
Finished Apr 25 04:19:24 PM PDT 24
Peak memory 301568 kb
Host smart-197629a8-a68f-4874-b6dc-812a9a219c04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3385280115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3385280115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.1381830044
Short name T1026
Test name
Test status
Simulation time 896935795607 ps
CPU time 5277.29 seconds
Started Apr 25 03:56:48 PM PDT 24
Finished Apr 25 05:24:46 PM PDT 24
Peak memory 639220 kb
Host smart-fe78ea51-858b-4037-9690-fd861062c2c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1381830044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1381830044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.1143814352
Short name T1071
Test name
Test status
Simulation time 372956697908 ps
CPU time 4739.34 seconds
Started Apr 25 03:56:47 PM PDT 24
Finished Apr 25 05:15:47 PM PDT 24
Peak memory 566792 kb
Host smart-d2581d18-f650-432d-ad90-99977c95d269
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1143814352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1143814352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2688244933
Short name T971
Test name
Test status
Simulation time 14727057 ps
CPU time 0.86 seconds
Started Apr 25 04:10:09 PM PDT 24
Finished Apr 25 04:10:10 PM PDT 24
Peak memory 217892 kb
Host smart-450bfd1c-5b26-4afe-b8e6-3ef0333890a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688244933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2688244933 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.1870103323
Short name T890
Test name
Test status
Simulation time 4631442531 ps
CPU time 83.55 seconds
Started Apr 25 04:10:02 PM PDT 24
Finished Apr 25 04:11:27 PM PDT 24
Peak memory 232248 kb
Host smart-94011a7f-d46e-4e31-982c-3faaa88c50f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870103323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.1870103323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.2476850966
Short name T736
Test name
Test status
Simulation time 6903513933 ps
CPU time 639.69 seconds
Started Apr 25 04:09:45 PM PDT 24
Finished Apr 25 04:20:25 PM PDT 24
Peak memory 242052 kb
Host smart-97b6bb06-8066-4515-91e8-47b25293ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476850966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.2476850966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.1467561782
Short name T78
Test name
Test status
Simulation time 2795980280 ps
CPU time 72.93 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 04:11:15 PM PDT 24
Peak memory 229448 kb
Host smart-e2538d8f-6a2f-499e-8554-2236ccfdb4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467561782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.1467561782 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3111854515
Short name T63
Test name
Test status
Simulation time 28752191224 ps
CPU time 153.78 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 04:12:35 PM PDT 24
Peak memory 242672 kb
Host smart-c58d1be7-ed70-410a-a310-70cbfa7a9a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111854515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3111854515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.356539315
Short name T59
Test name
Test status
Simulation time 3484602072 ps
CPU time 6.62 seconds
Started Apr 25 04:09:59 PM PDT 24
Finished Apr 25 04:10:06 PM PDT 24
Peak memory 218244 kb
Host smart-b5926f81-6ce0-45d8-a06a-b0068d8f2df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356539315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.356539315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.1560802723
Short name T29
Test name
Test status
Simulation time 72121067 ps
CPU time 1.72 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 04:10:04 PM PDT 24
Peak memory 218216 kb
Host smart-1fe6a3e5-7200-4bcb-aaf9-d6d45eda2d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560802723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1560802723 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.1514343512
Short name T583
Test name
Test status
Simulation time 157447795330 ps
CPU time 2579.18 seconds
Started Apr 25 04:09:46 PM PDT 24
Finished Apr 25 04:52:46 PM PDT 24
Peak memory 443072 kb
Host smart-19707325-0df8-4873-831e-541cf5e9bedf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514343512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_a
nd_output.1514343512 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.1860138396
Short name T348
Test name
Test status
Simulation time 9173057172 ps
CPU time 409.13 seconds
Started Apr 25 04:09:44 PM PDT 24
Finished Apr 25 04:16:34 PM PDT 24
Peak memory 250216 kb
Host smart-5af1fef5-6fe3-4f6e-9e1b-cdb5fb519643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860138396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1860138396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1361602002
Short name T228
Test name
Test status
Simulation time 941443103 ps
CPU time 20.44 seconds
Started Apr 25 04:09:39 PM PDT 24
Finished Apr 25 04:10:00 PM PDT 24
Peak memory 218300 kb
Host smart-927644d8-4791-4781-95bc-4c37c6526441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361602002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1361602002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.545249067
Short name T41
Test name
Test status
Simulation time 14384373557 ps
CPU time 307.32 seconds
Started Apr 25 04:10:08 PM PDT 24
Finished Apr 25 04:15:16 PM PDT 24
Peak memory 259852 kb
Host smart-db4c3951-555b-4de6-a23a-74ddb6647f9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=545249067 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.545249067 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.360230114
Short name T212
Test name
Test status
Simulation time 245814859 ps
CPU time 6.08 seconds
Started Apr 25 04:10:01 PM PDT 24
Finished Apr 25 04:10:08 PM PDT 24
Peak memory 218172 kb
Host smart-701f099b-5939-4ab5-843f-f9ee7b923163
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360230114 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.360230114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.681032078
Short name T1077
Test name
Test status
Simulation time 175275900 ps
CPU time 5.73 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 04:10:07 PM PDT 24
Peak memory 218204 kb
Host smart-2be867e5-f973-4e52-8039-732a6257022b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681032078 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.kmac_test_vectors_kmac_xof.681032078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.1544291744
Short name T940
Test name
Test status
Simulation time 401816643019 ps
CPU time 2450.72 seconds
Started Apr 25 04:09:50 PM PDT 24
Finished Apr 25 04:50:41 PM PDT 24
Peak memory 393368 kb
Host smart-7d0ef3ca-9553-4fc9-afcd-6d890d5611d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1544291744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.1544291744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.1298460018
Short name T303
Test name
Test status
Simulation time 72376790653 ps
CPU time 1840.47 seconds
Started Apr 25 04:09:50 PM PDT 24
Finished Apr 25 04:40:31 PM PDT 24
Peak memory 390600 kb
Host smart-8d4f8cbd-faba-4ccf-8a35-434212e59386
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1298460018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.1298460018 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.137778950
Short name T469
Test name
Test status
Simulation time 52604112150 ps
CPU time 1737.29 seconds
Started Apr 25 04:09:59 PM PDT 24
Finished Apr 25 04:38:58 PM PDT 24
Peak memory 340240 kb
Host smart-f964b900-6ae2-4a68-8590-94b38bbf8e4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=137778950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.137778950 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.1805529461
Short name T646
Test name
Test status
Simulation time 34680287910 ps
CPU time 1379.01 seconds
Started Apr 25 04:09:59 PM PDT 24
Finished Apr 25 04:32:59 PM PDT 24
Peak memory 299180 kb
Host smart-4ac0b75c-f86c-4d89-ae24-a1e809eba3c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1805529461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.1805529461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.2562900642
Short name T856
Test name
Test status
Simulation time 554611520894 ps
CPU time 5248.86 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 05:37:30 PM PDT 24
Peak memory 648548 kb
Host smart-62761a28-7a50-46ea-88e4-23bc8a85320d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2562900642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.2562900642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.4162495227
Short name T847
Test name
Test status
Simulation time 288033110083 ps
CPU time 4126.11 seconds
Started Apr 25 04:10:00 PM PDT 24
Finished Apr 25 05:18:48 PM PDT 24
Peak memory 563964 kb
Host smart-c1caba94-b25b-4843-b0eb-83a627eb8ad4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4162495227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.4162495227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.4130447538
Short name T988
Test name
Test status
Simulation time 56708520 ps
CPU time 0.87 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:10:25 PM PDT 24
Peak memory 217912 kb
Host smart-6e4ff846-9d82-4e6e-9895-712c42f33cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130447538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.4130447538 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.1975375407
Short name T430
Test name
Test status
Simulation time 28494103840 ps
CPU time 153.37 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:12:59 PM PDT 24
Peak memory 236416 kb
Host smart-7512e064-bd45-4945-b783-42a19e475db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975375407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.1975375407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.1661448932
Short name T527
Test name
Test status
Simulation time 65858044701 ps
CPU time 1691.56 seconds
Started Apr 25 04:10:16 PM PDT 24
Finished Apr 25 04:38:28 PM PDT 24
Peak memory 239180 kb
Host smart-018d7366-2fe3-4366-b4d9-a441c657dbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661448932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1661448932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1236919003
Short name T603
Test name
Test status
Simulation time 74970330347 ps
CPU time 364.63 seconds
Started Apr 25 04:10:17 PM PDT 24
Finished Apr 25 04:16:22 PM PDT 24
Peak memory 249900 kb
Host smart-a57dbba0-3584-452d-94d3-d5474fa78377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236919003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1236919003 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.2644612876
Short name T1034
Test name
Test status
Simulation time 3929091608 ps
CPU time 108.01 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:12:13 PM PDT 24
Peak memory 242792 kb
Host smart-ed96c7a5-4a51-465e-85ba-7c4c7810cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644612876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2644612876 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.2568950576
Short name T687
Test name
Test status
Simulation time 74364466 ps
CPU time 1.17 seconds
Started Apr 25 04:10:16 PM PDT 24
Finished Apr 25 04:10:18 PM PDT 24
Peak memory 218040 kb
Host smart-511bc6cb-b12e-4e42-9bcc-f820980c2dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568950576 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.2568950576 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.4251367247
Short name T899
Test name
Test status
Simulation time 3348907521 ps
CPU time 28.74 seconds
Started Apr 25 04:10:18 PM PDT 24
Finished Apr 25 04:10:47 PM PDT 24
Peak memory 235324 kb
Host smart-171a2647-af5b-4df4-97e2-cdc16bd412d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251367247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.4251367247 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.1860270593
Short name T346
Test name
Test status
Simulation time 123737568490 ps
CPU time 1898.87 seconds
Started Apr 25 04:10:11 PM PDT 24
Finished Apr 25 04:41:51 PM PDT 24
Peak memory 360224 kb
Host smart-02f9dc1b-badc-4f4a-91b9-e260e1189638
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860270593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a
nd_output.1860270593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.1430177967
Short name T325
Test name
Test status
Simulation time 53954680961 ps
CPU time 323.98 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 04:15:48 PM PDT 24
Peak memory 246656 kb
Host smart-faf0bb57-e7ab-4644-83a2-56cc9ef07cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430177967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1430177967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.2077757341
Short name T978
Test name
Test status
Simulation time 29056422616 ps
CPU time 81.94 seconds
Started Apr 25 04:10:10 PM PDT 24
Finished Apr 25 04:11:33 PM PDT 24
Peak memory 226344 kb
Host smart-b6c97fd5-0583-442e-9c8b-8eb6f25f3dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077757341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.2077757341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.3096091352
Short name T40
Test name
Test status
Simulation time 22578402720 ps
CPU time 1628.63 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 04:37:33 PM PDT 24
Peak memory 406860 kb
Host smart-2ccbfa94-57b8-4251-9974-24e9fe4eea31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3096091352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.3096091352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.973458155
Short name T584
Test name
Test status
Simulation time 382211593 ps
CPU time 6.48 seconds
Started Apr 25 04:10:16 PM PDT 24
Finished Apr 25 04:10:23 PM PDT 24
Peak memory 218256 kb
Host smart-0babb513-6005-4ecf-9a37-5a638dd87de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973458155 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_test_vectors_kmac.973458155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.3760333445
Short name T400
Test name
Test status
Simulation time 631524001 ps
CPU time 6.62 seconds
Started Apr 25 04:10:22 PM PDT 24
Finished Apr 25 04:10:29 PM PDT 24
Peak memory 218268 kb
Host smart-216494a4-36ca-4b54-b401-e4bf7c0172aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760333445 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.3760333445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.4249061513
Short name T670
Test name
Test status
Simulation time 109518439585 ps
CPU time 2230.5 seconds
Started Apr 25 04:10:22 PM PDT 24
Finished Apr 25 04:47:33 PM PDT 24
Peak memory 392768 kb
Host smart-b3c86fb6-31a4-4e53-9398-6495e1b5365d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4249061513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.4249061513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.3256701741
Short name T211
Test name
Test status
Simulation time 81456834022 ps
CPU time 2039.95 seconds
Started Apr 25 04:10:21 PM PDT 24
Finished Apr 25 04:44:22 PM PDT 24
Peak memory 385848 kb
Host smart-1a2ff2d0-523f-4bce-beef-1734fea473d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3256701741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3256701741 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.3247636874
Short name T486
Test name
Test status
Simulation time 48042825988 ps
CPU time 1751.5 seconds
Started Apr 25 04:10:15 PM PDT 24
Finished Apr 25 04:39:28 PM PDT 24
Peak memory 342660 kb
Host smart-e3548478-9c1c-4ed3-a706-193663fa6eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3247636874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.3247636874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.819096719
Short name T975
Test name
Test status
Simulation time 41931325993 ps
CPU time 1171.48 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 04:29:55 PM PDT 24
Peak memory 298996 kb
Host smart-cc4c9f55-d37c-4fb8-88b8-93627b3e3f64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=819096719 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.819096719 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.857664335
Short name T283
Test name
Test status
Simulation time 285851943352 ps
CPU time 4622.23 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 05:27:26 PM PDT 24
Peak memory 664808 kb
Host smart-08e13a3b-c67b-46f6-837c-170efc439873
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=857664335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.857664335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2344869532
Short name T337
Test name
Test status
Simulation time 57660981498 ps
CPU time 4388.24 seconds
Started Apr 25 04:10:18 PM PDT 24
Finished Apr 25 05:23:27 PM PDT 24
Peak memory 574792 kb
Host smart-23a95407-b4b4-432a-9394-f8e12cc48a4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2344869532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2344869532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.1422129365
Short name T867
Test name
Test status
Simulation time 21387709 ps
CPU time 0.81 seconds
Started Apr 25 04:10:46 PM PDT 24
Finished Apr 25 04:10:47 PM PDT 24
Peak memory 217876 kb
Host smart-97b68e05-5016-4f8f-ad54-660e87bada26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422129365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.1422129365 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.3575788042
Short name T669
Test name
Test status
Simulation time 20795382073 ps
CPU time 312.39 seconds
Started Apr 25 04:10:34 PM PDT 24
Finished Apr 25 04:15:47 PM PDT 24
Peak memory 247564 kb
Host smart-d450e823-b9d4-4ea8-ace1-1fc224ca6c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575788042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.3575788042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.973096094
Short name T440
Test name
Test status
Simulation time 11758768643 ps
CPU time 532.05 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:19:17 PM PDT 24
Peak memory 233656 kb
Host smart-842bc1b0-0480-42dd-9379-63d21cd8d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973096094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.973096094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2882560399
Short name T74
Test name
Test status
Simulation time 8829790755 ps
CPU time 217.15 seconds
Started Apr 25 04:10:38 PM PDT 24
Finished Apr 25 04:14:16 PM PDT 24
Peak memory 241116 kb
Host smart-15e617cb-235d-4efb-a614-e8f78db2a075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882560399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2882560399 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.3012447829
Short name T683
Test name
Test status
Simulation time 39944014149 ps
CPU time 344.03 seconds
Started Apr 25 04:10:38 PM PDT 24
Finished Apr 25 04:16:23 PM PDT 24
Peak memory 259188 kb
Host smart-198040f3-96b3-4d09-9b8a-d03c1104a338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012447829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.3012447829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1825662913
Short name T772
Test name
Test status
Simulation time 888952245 ps
CPU time 5.31 seconds
Started Apr 25 04:10:39 PM PDT 24
Finished Apr 25 04:10:45 PM PDT 24
Peak memory 218132 kb
Host smart-adac51bc-2730-40d0-a465-c6c4182110e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825662913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1825662913 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.2255116670
Short name T65
Test name
Test status
Simulation time 44884616 ps
CPU time 1.38 seconds
Started Apr 25 04:10:44 PM PDT 24
Finished Apr 25 04:10:47 PM PDT 24
Peak memory 218240 kb
Host smart-1ead31f2-c321-4e2a-b8ca-a0629947b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255116670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.2255116670 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.3034573181
Short name T577
Test name
Test status
Simulation time 58884887828 ps
CPU time 1505.33 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 04:35:29 PM PDT 24
Peak memory 327528 kb
Host smart-f77a85a1-59c2-40fa-83d1-12017abbdff7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034573181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.3034573181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.534432484
Short name T255
Test name
Test status
Simulation time 20959756063 ps
CPU time 279.3 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:15:04 PM PDT 24
Peak memory 240124 kb
Host smart-bcdf3f98-78de-47cc-a33a-f9dff68ea552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534432484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.534432484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.126917266
Short name T517
Test name
Test status
Simulation time 419474444 ps
CPU time 14.84 seconds
Started Apr 25 04:10:22 PM PDT 24
Finished Apr 25 04:10:38 PM PDT 24
Peak memory 225864 kb
Host smart-db089dfb-6397-45b7-9613-b12205115f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126917266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.126917266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.2572692500
Short name T861
Test name
Test status
Simulation time 3287669527 ps
CPU time 5.99 seconds
Started Apr 25 04:10:36 PM PDT 24
Finished Apr 25 04:10:42 PM PDT 24
Peak memory 218264 kb
Host smart-627ab6f9-2ec8-45a7-8f06-b897cfaaba86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572692500 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.2572692500 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1341197466
Short name T473
Test name
Test status
Simulation time 351942883 ps
CPU time 6.84 seconds
Started Apr 25 04:10:34 PM PDT 24
Finished Apr 25 04:10:42 PM PDT 24
Peak memory 218208 kb
Host smart-914bc214-e37f-49f7-b831-f55d4a1a141b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341197466 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1341197466 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.564598985
Short name T425
Test name
Test status
Simulation time 278338848142 ps
CPU time 2139.73 seconds
Started Apr 25 04:10:24 PM PDT 24
Finished Apr 25 04:46:05 PM PDT 24
Peak memory 411092 kb
Host smart-83589e07-737a-411c-9ea8-b679a226b1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=564598985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.564598985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.1873192645
Short name T226
Test name
Test status
Simulation time 775897811487 ps
CPU time 2165.56 seconds
Started Apr 25 04:10:23 PM PDT 24
Finished Apr 25 04:46:30 PM PDT 24
Peak memory 389156 kb
Host smart-748921c4-cdf9-4d71-af0f-e95ba66bdc62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1873192645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.1873192645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.3549943521
Short name T116
Test name
Test status
Simulation time 139766410055 ps
CPU time 1703.31 seconds
Started Apr 25 04:10:28 PM PDT 24
Finished Apr 25 04:38:51 PM PDT 24
Peak memory 337992 kb
Host smart-3f5b3ff4-9387-4e2b-a546-b140eaf1ae3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3549943521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.3549943521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.4026868581
Short name T1029
Test name
Test status
Simulation time 33080437370 ps
CPU time 1160.18 seconds
Started Apr 25 04:10:33 PM PDT 24
Finished Apr 25 04:29:54 PM PDT 24
Peak memory 296232 kb
Host smart-be99a86c-d1a8-4456-b7a3-76d2b0437588
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4026868581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.4026868581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3162782375
Short name T1036
Test name
Test status
Simulation time 1143936276052 ps
CPU time 5472.33 seconds
Started Apr 25 04:10:34 PM PDT 24
Finished Apr 25 05:41:48 PM PDT 24
Peak memory 668320 kb
Host smart-611de9dd-fde0-4dfd-98f8-bc4004e7c3e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3162782375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3162782375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.589198848
Short name T917
Test name
Test status
Simulation time 938366458713 ps
CPU time 4441.67 seconds
Started Apr 25 04:10:33 PM PDT 24
Finished Apr 25 05:24:36 PM PDT 24
Peak memory 576560 kb
Host smart-782fd8a1-8f0d-442d-ac0f-9ced1975b9ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=589198848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.589198848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.1222486529
Short name T626
Test name
Test status
Simulation time 19523142 ps
CPU time 0.83 seconds
Started Apr 25 04:10:58 PM PDT 24
Finished Apr 25 04:11:00 PM PDT 24
Peak memory 217920 kb
Host smart-57eea167-bd78-4263-905f-5111febf2623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222486529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.1222486529 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.2864521687
Short name T703
Test name
Test status
Simulation time 66799157085 ps
CPU time 448.99 seconds
Started Apr 25 04:11:00 PM PDT 24
Finished Apr 25 04:18:30 PM PDT 24
Peak memory 252584 kb
Host smart-0b9b930f-9111-4d2a-bfc5-f14c188f9bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864521687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2864521687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.1327175388
Short name T117
Test name
Test status
Simulation time 138480169134 ps
CPU time 1101.06 seconds
Started Apr 25 04:10:44 PM PDT 24
Finished Apr 25 04:29:06 PM PDT 24
Peak memory 237332 kb
Host smart-efacd6ea-ce64-4951-9175-361c7aefdf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327175388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.1327175388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1715114684
Short name T1074
Test name
Test status
Simulation time 14152850956 ps
CPU time 260.65 seconds
Started Apr 25 04:10:56 PM PDT 24
Finished Apr 25 04:15:17 PM PDT 24
Peak memory 245600 kb
Host smart-8950ca42-d187-415d-b688-2b6d94c3bd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715114684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1715114684 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_key_error.2474461928
Short name T997
Test name
Test status
Simulation time 3720133073 ps
CPU time 5.38 seconds
Started Apr 25 04:10:54 PM PDT 24
Finished Apr 25 04:11:00 PM PDT 24
Peak memory 218172 kb
Host smart-43510582-0bb8-4b02-9a65-51a965c2b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474461928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2474461928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.815587096
Short name T27
Test name
Test status
Simulation time 171121144 ps
CPU time 1.59 seconds
Started Apr 25 04:10:58 PM PDT 24
Finished Apr 25 04:11:00 PM PDT 24
Peak memory 226004 kb
Host smart-3ad084f2-51cb-4d35-87dd-d5563c3b2ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815587096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.815587096 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.3721382748
Short name T540
Test name
Test status
Simulation time 20163219801 ps
CPU time 514.56 seconds
Started Apr 25 04:10:43 PM PDT 24
Finished Apr 25 04:19:18 PM PDT 24
Peak memory 267436 kb
Host smart-25a69438-e18e-4475-a4ca-851b20e6acc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721382748 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.3721382748 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.2008293245
Short name T488
Test name
Test status
Simulation time 12208681942 ps
CPU time 414.56 seconds
Started Apr 25 04:10:45 PM PDT 24
Finished Apr 25 04:17:40 PM PDT 24
Peak memory 252684 kb
Host smart-99873f90-b9f3-4669-8761-dc29482a3c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008293245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2008293245 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1302289488
Short name T1058
Test name
Test status
Simulation time 13017368268 ps
CPU time 53.83 seconds
Started Apr 25 04:10:43 PM PDT 24
Finished Apr 25 04:11:37 PM PDT 24
Peak memory 226360 kb
Host smart-27985c78-83d4-4bac-9910-4d31cd4fe2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302289488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1302289488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.3492944396
Short name T802
Test name
Test status
Simulation time 192912780731 ps
CPU time 1739.86 seconds
Started Apr 25 04:10:54 PM PDT 24
Finished Apr 25 04:39:55 PM PDT 24
Peak memory 374684 kb
Host smart-81d50fe1-d5ae-4be0-8c05-ec573f6f7cce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3492944396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3492944396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.643615150
Short name T950
Test name
Test status
Simulation time 240213413 ps
CPU time 6.45 seconds
Started Apr 25 04:10:54 PM PDT 24
Finished Apr 25 04:11:01 PM PDT 24
Peak memory 218168 kb
Host smart-65593d53-8788-4506-b7d4-447156a3784c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643615150 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.kmac_test_vectors_kmac.643615150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.2982664287
Short name T580
Test name
Test status
Simulation time 516994096 ps
CPU time 6.71 seconds
Started Apr 25 04:10:58 PM PDT 24
Finished Apr 25 04:11:05 PM PDT 24
Peak memory 217928 kb
Host smart-15fca51c-3ebd-4b97-8675-a859fbb6669a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982664287 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.2982664287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.3769922155
Short name T399
Test name
Test status
Simulation time 486298779354 ps
CPU time 2401.13 seconds
Started Apr 25 04:10:48 PM PDT 24
Finished Apr 25 04:50:51 PM PDT 24
Peak memory 409060 kb
Host smart-d67d7111-f2e0-499e-849a-e7a172e342c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3769922155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.3769922155 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.449903969
Short name T539
Test name
Test status
Simulation time 316803574756 ps
CPU time 2253.29 seconds
Started Apr 25 04:10:51 PM PDT 24
Finished Apr 25 04:48:25 PM PDT 24
Peak memory 393564 kb
Host smart-f56573bc-0944-47bf-b806-6ff6f75e9592
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=449903969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.449903969 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.3159456594
Short name T536
Test name
Test status
Simulation time 20804629683 ps
CPU time 1405.76 seconds
Started Apr 25 04:10:48 PM PDT 24
Finished Apr 25 04:34:14 PM PDT 24
Peak memory 343368 kb
Host smart-49d52ef8-eac4-4dfd-a3d6-a40f41d999f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3159456594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.3159456594 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.2749068682
Short name T804
Test name
Test status
Simulation time 135145240824 ps
CPU time 1264.12 seconds
Started Apr 25 04:10:48 PM PDT 24
Finished Apr 25 04:31:53 PM PDT 24
Peak memory 303820 kb
Host smart-18480ddc-2cf1-4349-919a-ce08abd5b0ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2749068682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.2749068682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.3136059638
Short name T634
Test name
Test status
Simulation time 59254485513 ps
CPU time 4852.86 seconds
Started Apr 25 04:10:51 PM PDT 24
Finished Apr 25 05:31:45 PM PDT 24
Peak memory 638816 kb
Host smart-18755bab-4ce5-41ca-9029-4ae994b7ac2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3136059638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.3136059638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.97698907
Short name T972
Test name
Test status
Simulation time 194683411370 ps
CPU time 4569.01 seconds
Started Apr 25 04:10:54 PM PDT 24
Finished Apr 25 05:27:05 PM PDT 24
Peak memory 574968 kb
Host smart-d7c39585-7041-4c3b-97bb-921f1536bf1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=97698907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.97698907 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.2244819852
Short name T479
Test name
Test status
Simulation time 23427833 ps
CPU time 0.94 seconds
Started Apr 25 04:11:21 PM PDT 24
Finished Apr 25 04:11:22 PM PDT 24
Peak memory 217852 kb
Host smart-9b928716-d289-4ad0-9040-947f5d0c382d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244819852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2244819852 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3348294249
Short name T833
Test name
Test status
Simulation time 2767906434 ps
CPU time 152.18 seconds
Started Apr 25 04:11:11 PM PDT 24
Finished Apr 25 04:13:43 PM PDT 24
Peak memory 238212 kb
Host smart-995ce479-53b8-4717-883f-652501c64da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348294249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3348294249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.2399408930
Short name T529
Test name
Test status
Simulation time 8023550286 ps
CPU time 277.66 seconds
Started Apr 25 04:11:04 PM PDT 24
Finished Apr 25 04:15:42 PM PDT 24
Peak memory 229040 kb
Host smart-0c1dc232-7d33-400a-840a-367ec108f95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399408930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.2399408930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.2699286184
Short name T967
Test name
Test status
Simulation time 787888090 ps
CPU time 19.52 seconds
Started Apr 25 04:11:10 PM PDT 24
Finished Apr 25 04:11:30 PM PDT 24
Peak memory 221844 kb
Host smart-1ac3ba5e-e471-42ca-ae6a-28b5cd001d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699286184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.2699286184 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.259950888
Short name T795
Test name
Test status
Simulation time 5531453625 ps
CPU time 466.93 seconds
Started Apr 25 04:11:15 PM PDT 24
Finished Apr 25 04:19:02 PM PDT 24
Peak memory 274440 kb
Host smart-b553a820-2468-4c25-9b85-4b6475cf2536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259950888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.259950888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2945929997
Short name T288
Test name
Test status
Simulation time 1003330175 ps
CPU time 5.81 seconds
Started Apr 25 04:11:16 PM PDT 24
Finished Apr 25 04:11:22 PM PDT 24
Peak memory 218136 kb
Host smart-3b37934d-2562-4866-929f-a3b3db028fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945929997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2945929997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.3983973527
Short name T25
Test name
Test status
Simulation time 289425860 ps
CPU time 5.61 seconds
Started Apr 25 04:11:15 PM PDT 24
Finished Apr 25 04:11:21 PM PDT 24
Peak memory 226348 kb
Host smart-1c0a5954-8629-40fb-a373-b13309417076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983973527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.3983973527 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.466154203
Short name T635
Test name
Test status
Simulation time 223441038759 ps
CPU time 1862.14 seconds
Started Apr 25 04:11:00 PM PDT 24
Finished Apr 25 04:42:03 PM PDT 24
Peak memory 377148 kb
Host smart-f3f7ae49-6726-467c-b9df-f8b8d7f10b72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466154203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_an
d_output.466154203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_sideload.2274793425
Short name T816
Test name
Test status
Simulation time 59072668206 ps
CPU time 355.08 seconds
Started Apr 25 04:10:59 PM PDT 24
Finished Apr 25 04:16:55 PM PDT 24
Peak memory 245756 kb
Host smart-8fa166d7-7326-40b9-b394-74e5646ed44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274793425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.2274793425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_sideload/latest

Test location /workspace/coverage/default/44.kmac_smoke.2030280583
Short name T443
Test name
Test status
Simulation time 6352061660 ps
CPU time 43.09 seconds
Started Apr 25 04:11:01 PM PDT 24
Finished Apr 25 04:11:45 PM PDT 24
Peak memory 221028 kb
Host smart-8dc3c83e-190d-40a5-9966-e0a63ee53a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030280583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.2030280583 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_smoke/latest

Test location /workspace/coverage/default/44.kmac_stress_all.4292986744
Short name T332
Test name
Test status
Simulation time 12858654739 ps
CPU time 1278.29 seconds
Started Apr 25 04:11:19 PM PDT 24
Finished Apr 25 04:32:38 PM PDT 24
Peak memory 373144 kb
Host smart-ab62d525-e57e-4d7c-95e2-69784f3884e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4292986744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.4292986744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.2165538269
Short name T198
Test name
Test status
Simulation time 774520857 ps
CPU time 7.22 seconds
Started Apr 25 04:11:05 PM PDT 24
Finished Apr 25 04:11:13 PM PDT 24
Peak memory 218272 kb
Host smart-f2463fc3-7411-4392-9908-ac8af6eb0ce8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165538269 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.2165538269 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.2385356399
Short name T342
Test name
Test status
Simulation time 759467980 ps
CPU time 6.87 seconds
Started Apr 25 04:11:11 PM PDT 24
Finished Apr 25 04:11:18 PM PDT 24
Peak memory 218212 kb
Host smart-fac5e101-dd21-4040-9359-f093cadf75bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385356399 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.kmac_test_vectors_kmac_xof.2385356399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.2948178353
Short name T761
Test name
Test status
Simulation time 43670140578 ps
CPU time 1854.93 seconds
Started Apr 25 04:11:04 PM PDT 24
Finished Apr 25 04:41:59 PM PDT 24
Peak memory 398492 kb
Host smart-0356fd51-251b-4953-8a46-1288831d620b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2948178353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.2948178353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.2782912268
Short name T831
Test name
Test status
Simulation time 380531167818 ps
CPU time 2169.95 seconds
Started Apr 25 04:11:05 PM PDT 24
Finished Apr 25 04:47:16 PM PDT 24
Peak memory 385144 kb
Host smart-597dc28b-c82b-4a8a-86ec-5f9e9ab71606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2782912268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2782912268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.528475444
Short name T548
Test name
Test status
Simulation time 198589858447 ps
CPU time 1579.88 seconds
Started Apr 25 04:11:05 PM PDT 24
Finished Apr 25 04:37:26 PM PDT 24
Peak memory 340632 kb
Host smart-b3c77e2a-1faa-466a-a020-d79ebebcc9e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=528475444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.528475444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1093844829
Short name T964
Test name
Test status
Simulation time 10917637130 ps
CPU time 1220.54 seconds
Started Apr 25 04:11:06 PM PDT 24
Finished Apr 25 04:31:27 PM PDT 24
Peak memory 298548 kb
Host smart-cef1133a-29c1-4551-b8ff-ead52f3fb3a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1093844829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1093844829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.2475424438
Short name T233
Test name
Test status
Simulation time 737415153080 ps
CPU time 5246.42 seconds
Started Apr 25 04:11:05 PM PDT 24
Finished Apr 25 05:38:32 PM PDT 24
Peak memory 650424 kb
Host smart-d9ed94cc-0993-4c7e-bb97-a8098c559af9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2475424438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.2475424438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2275874839
Short name T383
Test name
Test status
Simulation time 229012632018 ps
CPU time 3890.33 seconds
Started Apr 25 04:11:04 PM PDT 24
Finished Apr 25 05:15:55 PM PDT 24
Peak memory 573772 kb
Host smart-5418b5ff-7b2f-4a2d-bc48-1ef9df2f7f6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2275874839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2275874839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.699693429
Short name T857
Test name
Test status
Simulation time 118553788 ps
CPU time 0.84 seconds
Started Apr 25 04:11:39 PM PDT 24
Finished Apr 25 04:11:41 PM PDT 24
Peak memory 217888 kb
Host smart-fdeeae3f-3cb6-49a0-a438-fe3d6f54aba7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699693429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.699693429 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.3193498786
Short name T830
Test name
Test status
Simulation time 1537742793 ps
CPU time 83.45 seconds
Started Apr 25 04:11:33 PM PDT 24
Finished Apr 25 04:12:57 PM PDT 24
Peak memory 230720 kb
Host smart-a03ca5fc-c0ad-4b3c-843d-78fd11fc7b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193498786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.3193498786 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.2615189515
Short name T733
Test name
Test status
Simulation time 9630868475 ps
CPU time 434.73 seconds
Started Apr 25 04:11:21 PM PDT 24
Finished Apr 25 04:18:37 PM PDT 24
Peak memory 242688 kb
Host smart-c11137f2-2835-4137-b2ab-72ed92771270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615189515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.2615189515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_entropy_refresh.1243870967
Short name T792
Test name
Test status
Simulation time 1907475214 ps
CPU time 43.17 seconds
Started Apr 25 04:11:33 PM PDT 24
Finished Apr 25 04:12:17 PM PDT 24
Peak memory 226292 kb
Host smart-1cde9f24-e152-49b3-bfd2-a32a4d4b33dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243870967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1243870967 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/45.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/45.kmac_error.3739757325
Short name T1066
Test name
Test status
Simulation time 2634741009 ps
CPU time 39.04 seconds
Started Apr 25 04:11:37 PM PDT 24
Finished Apr 25 04:12:17 PM PDT 24
Peak memory 242256 kb
Host smart-fe98d174-a373-46bb-8e75-8fdc83d7c683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739757325 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.3739757325 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.1691813021
Short name T562
Test name
Test status
Simulation time 2853220342 ps
CPU time 4.75 seconds
Started Apr 25 04:11:33 PM PDT 24
Finished Apr 25 04:11:38 PM PDT 24
Peak memory 218208 kb
Host smart-d40048e0-a466-44d3-9579-a81173227c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691813021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.1691813021 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.3205995647
Short name T868
Test name
Test status
Simulation time 16613783189 ps
CPU time 1641.24 seconds
Started Apr 25 04:11:22 PM PDT 24
Finished Apr 25 04:38:44 PM PDT 24
Peak memory 377940 kb
Host smart-860befb5-bf3b-4e80-8045-69dafc9237c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205995647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.3205995647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.1848542146
Short name T650
Test name
Test status
Simulation time 16210502026 ps
CPU time 196.53 seconds
Started Apr 25 04:11:22 PM PDT 24
Finished Apr 25 04:14:39 PM PDT 24
Peak memory 240448 kb
Host smart-1c272774-8ce2-447e-a3f7-43917ce61d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848542146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.1848542146 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.843849659
Short name T578
Test name
Test status
Simulation time 1517786217 ps
CPU time 11.07 seconds
Started Apr 25 04:11:23 PM PDT 24
Finished Apr 25 04:11:34 PM PDT 24
Peak memory 224696 kb
Host smart-fdf422bb-f6d4-4d72-9856-1f34dc1903bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843849659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.843849659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.3616808955
Short name T171
Test name
Test status
Simulation time 3338685238 ps
CPU time 16.01 seconds
Started Apr 25 04:11:33 PM PDT 24
Finished Apr 25 04:11:49 PM PDT 24
Peak memory 226408 kb
Host smart-1e3f66d7-f73c-405f-b58f-7e83035eef06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3616808955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.3616808955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_stress_all_with_rand_reset.269294553
Short name T129
Test name
Test status
Simulation time 20848988376 ps
CPU time 884.95 seconds
Started Apr 25 04:11:34 PM PDT 24
Finished Apr 25 04:26:19 PM PDT 24
Peak memory 323636 kb
Host smart-242362c1-24cf-4fd7-875d-07df548d70c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=269294553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.269294553 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.4101325953
Short name T673
Test name
Test status
Simulation time 276771968 ps
CPU time 6.98 seconds
Started Apr 25 04:11:27 PM PDT 24
Finished Apr 25 04:11:34 PM PDT 24
Peak memory 218216 kb
Host smart-2ab06928-7d11-4944-ba98-5eddb6e50966
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101325953 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.4101325953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.2181450643
Short name T214
Test name
Test status
Simulation time 484676778 ps
CPU time 6.61 seconds
Started Apr 25 04:11:26 PM PDT 24
Finished Apr 25 04:11:33 PM PDT 24
Peak memory 218244 kb
Host smart-2515a591-be62-43e6-9cff-0202de3cd526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181450643 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.2181450643 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2124465985
Short name T682
Test name
Test status
Simulation time 264892358707 ps
CPU time 2414.18 seconds
Started Apr 25 04:11:20 PM PDT 24
Finished Apr 25 04:51:35 PM PDT 24
Peak memory 393636 kb
Host smart-31c2b3b7-7cf7-4729-8828-7dc05989362d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2124465985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2124465985 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.1116518084
Short name T138
Test name
Test status
Simulation time 97071721387 ps
CPU time 2270.12 seconds
Started Apr 25 04:11:21 PM PDT 24
Finished Apr 25 04:49:12 PM PDT 24
Peak memory 391480 kb
Host smart-883c4135-445b-4092-b4db-da7f8bbcc948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1116518084 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.1116518084 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.2049012839
Short name T208
Test name
Test status
Simulation time 437726584785 ps
CPU time 1810.74 seconds
Started Apr 25 04:11:23 PM PDT 24
Finished Apr 25 04:41:34 PM PDT 24
Peak memory 340952 kb
Host smart-cbeb9802-ea2d-4382-8505-b653f6608e84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2049012839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.2049012839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.698517027
Short name T508
Test name
Test status
Simulation time 12347510425 ps
CPU time 1255.98 seconds
Started Apr 25 04:11:26 PM PDT 24
Finished Apr 25 04:32:23 PM PDT 24
Peak memory 302624 kb
Host smart-f41febd8-ad22-4503-ac85-f19599ac0d2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=698517027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.698517027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1515934631
Short name T36
Test name
Test status
Simulation time 302622997031 ps
CPU time 4600.37 seconds
Started Apr 25 04:11:27 PM PDT 24
Finished Apr 25 05:28:08 PM PDT 24
Peak memory 663348 kb
Host smart-48d789e1-8a40-4e9f-be25-111980edcd82
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1515934631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1515934631 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.4156997002
Short name T1025
Test name
Test status
Simulation time 67315766598 ps
CPU time 4081.32 seconds
Started Apr 25 04:11:26 PM PDT 24
Finished Apr 25 05:19:29 PM PDT 24
Peak memory 587792 kb
Host smart-55cef971-1033-4acb-8efa-20c99194b0e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4156997002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.4156997002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.367216288
Short name T398
Test name
Test status
Simulation time 26455547 ps
CPU time 0.8 seconds
Started Apr 25 04:11:59 PM PDT 24
Finished Apr 25 04:12:00 PM PDT 24
Peak memory 217900 kb
Host smart-42569806-e6e8-4eac-80bd-dbaddc4b37ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367216288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.367216288 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.669894470
Short name T896
Test name
Test status
Simulation time 17513831268 ps
CPU time 81 seconds
Started Apr 25 04:11:51 PM PDT 24
Finished Apr 25 04:13:12 PM PDT 24
Peak memory 231656 kb
Host smart-1a5be786-7328-4309-87bf-0af84f9aef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669894470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.669894470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.2396150423
Short name T149
Test name
Test status
Simulation time 6615221459 ps
CPU time 630.71 seconds
Started Apr 25 04:11:39 PM PDT 24
Finished Apr 25 04:22:10 PM PDT 24
Peak memory 241336 kb
Host smart-404ab626-a4bc-407d-ac9c-e99d57ad8f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396150423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2396150423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_error.1614801484
Short name T1035
Test name
Test status
Simulation time 17087980328 ps
CPU time 95.69 seconds
Started Apr 25 04:11:52 PM PDT 24
Finished Apr 25 04:13:28 PM PDT 24
Peak memory 242804 kb
Host smart-5a76e29a-2106-4e86-9447-c6b177cb0ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614801484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.1614801484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.2603917357
Short name T767
Test name
Test status
Simulation time 3658987323 ps
CPU time 4.82 seconds
Started Apr 25 04:11:53 PM PDT 24
Finished Apr 25 04:11:59 PM PDT 24
Peak memory 218192 kb
Host smart-cd75967c-4963-4bec-aaa8-5612f9d6b43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603917357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.2603917357 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.3927365175
Short name T34
Test name
Test status
Simulation time 62249924 ps
CPU time 1.39 seconds
Started Apr 25 04:11:59 PM PDT 24
Finished Apr 25 04:12:01 PM PDT 24
Peak memory 218292 kb
Host smart-9c509237-6a5a-4fab-af9c-98f32ec0343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927365175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3927365175 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.225976244
Short name T501
Test name
Test status
Simulation time 16309144506 ps
CPU time 587.79 seconds
Started Apr 25 04:11:38 PM PDT 24
Finished Apr 25 04:21:26 PM PDT 24
Peak memory 268660 kb
Host smart-b7b93b96-2b4e-4269-ac31-dd36db919304
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225976244 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_an
d_output.225976244 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.1871146981
Short name T201
Test name
Test status
Simulation time 2710846677 ps
CPU time 71.83 seconds
Started Apr 25 04:11:38 PM PDT 24
Finished Apr 25 04:12:51 PM PDT 24
Peak memory 228048 kb
Host smart-e4f7385f-616d-4da8-a35f-64b0fef74ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871146981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.1871146981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.1755859017
Short name T871
Test name
Test status
Simulation time 2875007363 ps
CPU time 29.99 seconds
Started Apr 25 04:11:39 PM PDT 24
Finished Apr 25 04:12:09 PM PDT 24
Peak memory 226328 kb
Host smart-57c87739-3228-4944-8efe-9e368cdacba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755859017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.1755859017 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.3247967868
Short name T636
Test name
Test status
Simulation time 29425801990 ps
CPU time 744.79 seconds
Started Apr 25 04:11:58 PM PDT 24
Finished Apr 25 04:24:23 PM PDT 24
Peak memory 324932 kb
Host smart-f5109828-b158-4ba8-a69e-d68624a31ff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3247967868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.3247967868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.3093503560
Short name T960
Test name
Test status
Simulation time 292618076 ps
CPU time 6.4 seconds
Started Apr 25 04:11:44 PM PDT 24
Finished Apr 25 04:11:51 PM PDT 24
Peak memory 218200 kb
Host smart-1085d8f9-f35b-499a-b43c-885ef476099a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093503560 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.3093503560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.4094923331
Short name T607
Test name
Test status
Simulation time 143046655 ps
CPU time 6.14 seconds
Started Apr 25 04:11:51 PM PDT 24
Finished Apr 25 04:11:57 PM PDT 24
Peak memory 218240 kb
Host smart-91f12d45-57a8-4429-9696-f2aafff3250e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094923331 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.4094923331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.921724653
Short name T522
Test name
Test status
Simulation time 176433549480 ps
CPU time 2177.41 seconds
Started Apr 25 04:11:41 PM PDT 24
Finished Apr 25 04:47:59 PM PDT 24
Peak memory 397568 kb
Host smart-ba1996e7-8a88-429a-aa29-0563f77d1811
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=921724653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.921724653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.236986556
Short name T633
Test name
Test status
Simulation time 76314098295 ps
CPU time 1870.62 seconds
Started Apr 25 04:11:40 PM PDT 24
Finished Apr 25 04:42:51 PM PDT 24
Peak memory 386076 kb
Host smart-2150ca65-a74d-4189-8e8f-2b092e1467df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=236986556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.236986556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.794205210
Short name T414
Test name
Test status
Simulation time 15507292333 ps
CPU time 1552.35 seconds
Started Apr 25 04:11:46 PM PDT 24
Finished Apr 25 04:37:39 PM PDT 24
Peak memory 341884 kb
Host smart-6a567436-7124-4355-9bde-8fe0324bc18d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=794205210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.794205210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.2846691613
Short name T956
Test name
Test status
Simulation time 144670069099 ps
CPU time 1290.29 seconds
Started Apr 25 04:11:43 PM PDT 24
Finished Apr 25 04:33:13 PM PDT 24
Peak memory 298388 kb
Host smart-b93ea667-5936-4e00-83c6-dfc6afd2ebe8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2846691613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.2846691613 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1890344424
Short name T855
Test name
Test status
Simulation time 119002095706 ps
CPU time 4596.19 seconds
Started Apr 25 04:11:41 PM PDT 24
Finished Apr 25 05:28:19 PM PDT 24
Peak memory 644884 kb
Host smart-7f7e4c3b-89e2-4b04-9b45-1bb0079e038a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1890344424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1890344424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1420246659
Short name T933
Test name
Test status
Simulation time 684002916941 ps
CPU time 4714.54 seconds
Started Apr 25 04:11:43 PM PDT 24
Finished Apr 25 05:30:19 PM PDT 24
Peak memory 569476 kb
Host smart-31e33632-0f8d-4dd1-9ef3-8bc90eb8462f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1420246659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1420246659 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.991901505
Short name T104
Test name
Test status
Simulation time 14937391 ps
CPU time 0.88 seconds
Started Apr 25 04:12:14 PM PDT 24
Finished Apr 25 04:12:16 PM PDT 24
Peak memory 217904 kb
Host smart-4492e8c6-58be-4083-8c40-0ab53a5be4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991901505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.991901505 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.3571602427
Short name T432
Test name
Test status
Simulation time 21931096071 ps
CPU time 150.73 seconds
Started Apr 25 04:12:08 PM PDT 24
Finished Apr 25 04:14:39 PM PDT 24
Peak memory 237792 kb
Host smart-46c5edda-ffa6-47ec-ad43-aae0fce38d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571602427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3571602427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.1911637755
Short name T598
Test name
Test status
Simulation time 14433890344 ps
CPU time 1506.48 seconds
Started Apr 25 04:12:04 PM PDT 24
Finished Apr 25 04:37:11 PM PDT 24
Peak memory 237208 kb
Host smart-00fb18c8-585f-4d83-998c-8c590a590cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911637755 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.1911637755 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_error.2824814363
Short name T115
Test name
Test status
Simulation time 919131586 ps
CPU time 27.2 seconds
Started Apr 25 04:12:10 PM PDT 24
Finished Apr 25 04:12:37 PM PDT 24
Peak memory 242632 kb
Host smart-1695e06a-6ae1-47b3-8659-2981db0ab340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824814363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2824814363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.1393983314
Short name T482
Test name
Test status
Simulation time 1976347308 ps
CPU time 6.21 seconds
Started Apr 25 04:12:09 PM PDT 24
Finished Apr 25 04:12:16 PM PDT 24
Peak memory 218068 kb
Host smart-af4d6505-b5e7-400f-a606-80e77a7210b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393983314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.1393983314 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.2967707323
Short name T77
Test name
Test status
Simulation time 75407483 ps
CPU time 1.58 seconds
Started Apr 25 04:12:07 PM PDT 24
Finished Apr 25 04:12:09 PM PDT 24
Peak memory 218088 kb
Host smart-fffa0881-1926-4bec-bfbd-a95208deb923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967707323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.2967707323 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.2278402998
Short name T800
Test name
Test status
Simulation time 4255308096 ps
CPU time 104.77 seconds
Started Apr 25 04:11:58 PM PDT 24
Finished Apr 25 04:13:44 PM PDT 24
Peak memory 236892 kb
Host smart-ce573290-9cf5-416e-b271-af1386240492
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278402998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a
nd_output.2278402998 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3397282065
Short name T829
Test name
Test status
Simulation time 2663084411 ps
CPU time 83.89 seconds
Started Apr 25 04:11:57 PM PDT 24
Finished Apr 25 04:13:21 PM PDT 24
Peak memory 229952 kb
Host smart-c047f4e2-7788-400a-b428-1a578f846baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397282065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3397282065 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3377549517
Short name T943
Test name
Test status
Simulation time 7753403141 ps
CPU time 85.23 seconds
Started Apr 25 04:11:58 PM PDT 24
Finished Apr 25 04:13:24 PM PDT 24
Peak memory 226268 kb
Host smart-904a0bd8-bf3f-469f-ad0b-e7a309ddc012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377549517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3377549517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.775609697
Short name T870
Test name
Test status
Simulation time 245698553037 ps
CPU time 1692.92 seconds
Started Apr 25 04:12:11 PM PDT 24
Finished Apr 25 04:40:26 PM PDT 24
Peak memory 378016 kb
Host smart-f6589a96-35ed-46a6-97b9-1223a6a0e18a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=775609697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.775609697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.2783726323
Short name T521
Test name
Test status
Simulation time 1067689372 ps
CPU time 6.79 seconds
Started Apr 25 04:12:11 PM PDT 24
Finished Apr 25 04:12:18 PM PDT 24
Peak memory 219188 kb
Host smart-2e64007c-7f7c-4023-b7d1-d8123023e0c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783726323 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.kmac_test_vectors_kmac.2783726323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.2537899610
Short name T507
Test name
Test status
Simulation time 186116174 ps
CPU time 6.27 seconds
Started Apr 25 04:12:09 PM PDT 24
Finished Apr 25 04:12:16 PM PDT 24
Peak memory 218184 kb
Host smart-6ac8c0c6-126f-4c01-bb15-bcc0a1cfb3cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537899610 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.2537899610 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.4184663031
Short name T907
Test name
Test status
Simulation time 50191256743 ps
CPU time 1781.26 seconds
Started Apr 25 04:12:06 PM PDT 24
Finished Apr 25 04:41:48 PM PDT 24
Peak memory 394516 kb
Host smart-5dbe0a24-7625-422f-bc9d-eac900500bbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4184663031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.4184663031 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.2737295189
Short name T1059
Test name
Test status
Simulation time 129727890090 ps
CPU time 2288.28 seconds
Started Apr 25 04:12:05 PM PDT 24
Finished Apr 25 04:50:14 PM PDT 24
Peak memory 397084 kb
Host smart-c4cfdbb0-47b7-40c6-8dc5-434846a4f8b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2737295189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.2737295189 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.1574319823
Short name T916
Test name
Test status
Simulation time 30152785247 ps
CPU time 1608.93 seconds
Started Apr 25 04:12:13 PM PDT 24
Finished Apr 25 04:39:03 PM PDT 24
Peak memory 342976 kb
Host smart-f0862726-bf7a-4287-a8f1-f10eb5f97815
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1574319823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.1574319823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.4130516527
Short name T757
Test name
Test status
Simulation time 61260059680 ps
CPU time 1230.73 seconds
Started Apr 25 04:12:07 PM PDT 24
Finished Apr 25 04:32:38 PM PDT 24
Peak memory 306432 kb
Host smart-a307b9c3-f618-4400-ab28-dd55f7b3829f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4130516527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.4130516527 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.3561542614
Short name T245
Test name
Test status
Simulation time 126398484141 ps
CPU time 4457.46 seconds
Started Apr 25 04:12:08 PM PDT 24
Finished Apr 25 05:26:26 PM PDT 24
Peak memory 654336 kb
Host smart-4aed63a6-5d9a-4080-83bc-6c8ed0c592fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3561542614 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.3561542614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.2792072939
Short name T980
Test name
Test status
Simulation time 229210217833 ps
CPU time 4764.63 seconds
Started Apr 25 04:12:07 PM PDT 24
Finished Apr 25 05:31:33 PM PDT 24
Peak memory 565036 kb
Host smart-156a8956-837e-4acd-b125-a78ef232e521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2792072939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.2792072939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.665277491
Short name T239
Test name
Test status
Simulation time 31168746 ps
CPU time 0.94 seconds
Started Apr 25 04:12:42 PM PDT 24
Finished Apr 25 04:12:44 PM PDT 24
Peak memory 217884 kb
Host smart-8be94310-69ed-4cf3-975e-1a0a31185c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665277491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.665277491 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1213023838
Short name T694
Test name
Test status
Simulation time 5611718924 ps
CPU time 94.85 seconds
Started Apr 25 04:12:34 PM PDT 24
Finished Apr 25 04:14:10 PM PDT 24
Peak memory 231360 kb
Host smart-6236b280-d149-4f4f-b105-ecd486bb7bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213023838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1213023838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.2814147406
Short name T277
Test name
Test status
Simulation time 10993541176 ps
CPU time 1085.32 seconds
Started Apr 25 04:12:17 PM PDT 24
Finished Apr 25 04:30:24 PM PDT 24
Peak memory 236820 kb
Host smart-34aecaab-520c-445d-9398-d19cbd3d8437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814147406 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2814147406 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.2603316596
Short name T498
Test name
Test status
Simulation time 2004452245 ps
CPU time 54.67 seconds
Started Apr 25 04:12:39 PM PDT 24
Finished Apr 25 04:13:34 PM PDT 24
Peak memory 227680 kb
Host smart-e21a767f-0bc0-40a9-805c-4b9dafeb22a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603316596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2603316596 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.2778920299
Short name T791
Test name
Test status
Simulation time 13881880524 ps
CPU time 346.2 seconds
Started Apr 25 04:12:41 PM PDT 24
Finished Apr 25 04:18:28 PM PDT 24
Peak memory 259124 kb
Host smart-913f19d3-78e8-47ca-a4b9-7bb8a633d1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778920299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2778920299 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.947167712
Short name T407
Test name
Test status
Simulation time 2219746434 ps
CPU time 5.44 seconds
Started Apr 25 04:12:41 PM PDT 24
Finished Apr 25 04:12:48 PM PDT 24
Peak memory 218084 kb
Host smart-f54bc13e-97f0-4680-99f0-27aa60cfdf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947167712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.947167712 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.432606233
Short name T464
Test name
Test status
Simulation time 128702863 ps
CPU time 4.53 seconds
Started Apr 25 04:12:41 PM PDT 24
Finished Apr 25 04:12:47 PM PDT 24
Peak memory 222612 kb
Host smart-8ab9bed7-a053-4a24-b0f4-3abbe14d6acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432606233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.432606233 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.1596391114
Short name T315
Test name
Test status
Simulation time 445493134702 ps
CPU time 2739.85 seconds
Started Apr 25 04:12:18 PM PDT 24
Finished Apr 25 04:57:59 PM PDT 24
Peak memory 465320 kb
Host smart-7b782dea-74cc-4a95-88a3-40586ba920ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596391114 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.1596391114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.3655570212
Short name T213
Test name
Test status
Simulation time 13628167983 ps
CPU time 397.04 seconds
Started Apr 25 04:12:17 PM PDT 24
Finished Apr 25 04:18:55 PM PDT 24
Peak memory 251588 kb
Host smart-6a5663eb-d6b2-4b95-bb08-9468950ed02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655570212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.3655570212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.3297814326
Short name T221
Test name
Test status
Simulation time 2366453408 ps
CPU time 15.2 seconds
Started Apr 25 04:12:12 PM PDT 24
Finished Apr 25 04:12:28 PM PDT 24
Peak memory 226396 kb
Host smart-ac77e167-6651-432b-8f93-c3421716ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297814326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3297814326 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.4132258566
Short name T543
Test name
Test status
Simulation time 13965045482 ps
CPU time 392.92 seconds
Started Apr 25 04:12:44 PM PDT 24
Finished Apr 25 04:19:18 PM PDT 24
Peak memory 275060 kb
Host smart-84cbe3af-8641-41b5-89c9-951044a271f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4132258566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.4132258566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3357687270
Short name T1038
Test name
Test status
Simulation time 939530675 ps
CPU time 6.25 seconds
Started Apr 25 04:12:35 PM PDT 24
Finished Apr 25 04:12:41 PM PDT 24
Peak memory 218208 kb
Host smart-99747181-ea02-4301-aa3e-690a3be6ee9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357687270 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3357687270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2150268294
Short name T335
Test name
Test status
Simulation time 218082175 ps
CPU time 6.2 seconds
Started Apr 25 04:12:34 PM PDT 24
Finished Apr 25 04:12:41 PM PDT 24
Peak memory 218236 kb
Host smart-d0bd1c7c-6065-4000-b887-75c26725c7a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150268294 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2150268294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.1544891881
Short name T994
Test name
Test status
Simulation time 253070638236 ps
CPU time 2114.54 seconds
Started Apr 25 04:12:17 PM PDT 24
Finished Apr 25 04:47:33 PM PDT 24
Peak memory 382820 kb
Host smart-ec51cd1c-5477-40a7-9cc5-878f91e4ffd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1544891881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.1544891881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.2305430905
Short name T788
Test name
Test status
Simulation time 24449849458 ps
CPU time 1928.07 seconds
Started Apr 25 04:12:23 PM PDT 24
Finished Apr 25 04:44:32 PM PDT 24
Peak memory 380064 kb
Host smart-7bfad0c5-b8d6-4afd-94b3-38bb6803d99a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2305430905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.2305430905 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.3098808622
Short name T423
Test name
Test status
Simulation time 142384003902 ps
CPU time 1929.86 seconds
Started Apr 25 04:12:24 PM PDT 24
Finished Apr 25 04:44:35 PM PDT 24
Peak memory 342616 kb
Host smart-7747b43b-244b-4472-8eed-94f5ab050a8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3098808622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3098808622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.3348736237
Short name T752
Test name
Test status
Simulation time 49898568097 ps
CPU time 1351.21 seconds
Started Apr 25 04:12:30 PM PDT 24
Finished Apr 25 04:35:02 PM PDT 24
Peak memory 301256 kb
Host smart-5b8ba450-5a60-4032-826a-ab05a5dba2bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3348736237 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.3348736237 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.1549573419
Short name T597
Test name
Test status
Simulation time 619017327861 ps
CPU time 5633.89 seconds
Started Apr 25 04:12:30 PM PDT 24
Finished Apr 25 05:46:25 PM PDT 24
Peak memory 653604 kb
Host smart-a600b274-42f6-4113-914c-0aee1563f827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1549573419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.1549573419 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.3333914661
Short name T929
Test name
Test status
Simulation time 1888708119734 ps
CPU time 5258.95 seconds
Started Apr 25 04:12:30 PM PDT 24
Finished Apr 25 05:40:10 PM PDT 24
Peak memory 571560 kb
Host smart-9b868712-e5fd-41d6-9d45-6f14d75671b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3333914661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.3333914661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.3341363047
Short name T327
Test name
Test status
Simulation time 13939023 ps
CPU time 0.84 seconds
Started Apr 25 04:13:00 PM PDT 24
Finished Apr 25 04:13:01 PM PDT 24
Peak memory 217916 kb
Host smart-f2c724d7-8add-4cd6-b7b6-758504f84bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341363047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3341363047 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.2096730072
Short name T1001
Test name
Test status
Simulation time 3156533176 ps
CPU time 54.25 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 04:13:49 PM PDT 24
Peak memory 228316 kb
Host smart-c9bae315-2024-4588-aa2b-0772e441a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096730072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.2096730072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.2147967963
Short name T267
Test name
Test status
Simulation time 13830453351 ps
CPU time 712.58 seconds
Started Apr 25 04:12:49 PM PDT 24
Finished Apr 25 04:24:42 PM PDT 24
Peak memory 234788 kb
Host smart-0c4050ce-8922-45df-9223-8e8afc25e058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147967963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2147967963 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3399936289
Short name T854
Test name
Test status
Simulation time 35109279427 ps
CPU time 246.83 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 04:17:01 PM PDT 24
Peak memory 242760 kb
Host smart-2c94881f-f11b-47d8-8c1d-01694913ed83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399936289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3399936289 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1302814232
Short name T1018
Test name
Test status
Simulation time 576529901 ps
CPU time 43.66 seconds
Started Apr 25 04:12:55 PM PDT 24
Finished Apr 25 04:13:39 PM PDT 24
Peak memory 242680 kb
Host smart-d8798cc7-5bc9-415e-9d67-0c9c9630fb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302814232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1302814232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.3531933871
Short name T344
Test name
Test status
Simulation time 1855690320 ps
CPU time 4.33 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 04:12:59 PM PDT 24
Peak memory 218108 kb
Host smart-6b5d45b1-813a-4a83-a89f-19374af4a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531933871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3531933871 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.192964725
Short name T38
Test name
Test status
Simulation time 1843527041 ps
CPU time 13.16 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 04:13:08 PM PDT 24
Peak memory 234432 kb
Host smart-c5ea043d-f579-45e8-9ee2-00872fc605ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192964725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.192964725 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.4214933685
Short name T718
Test name
Test status
Simulation time 42412489667 ps
CPU time 1524.97 seconds
Started Apr 25 04:12:48 PM PDT 24
Finished Apr 25 04:38:14 PM PDT 24
Peak memory 338568 kb
Host smart-f4e1b689-4460-458d-86c9-577b57f8257c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214933685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.4214933685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.771635352
Short name T664
Test name
Test status
Simulation time 60225155213 ps
CPU time 380.44 seconds
Started Apr 25 04:12:49 PM PDT 24
Finished Apr 25 04:19:10 PM PDT 24
Peak memory 247704 kb
Host smart-2474b51e-d56f-4955-b044-2fedeecfe9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771635352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.771635352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.2174421765
Short name T749
Test name
Test status
Simulation time 2785919815 ps
CPU time 72.48 seconds
Started Apr 25 04:12:43 PM PDT 24
Finished Apr 25 04:13:57 PM PDT 24
Peak memory 223108 kb
Host smart-7b9bef43-a9e7-48fe-8eb8-49bd9f464f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174421765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.2174421765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2416467370
Short name T973
Test name
Test status
Simulation time 26160944613 ps
CPU time 795.51 seconds
Started Apr 25 04:13:00 PM PDT 24
Finished Apr 25 04:26:16 PM PDT 24
Peak memory 318820 kb
Host smart-34677934-75a4-4f3e-a821-47601c63c1e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2416467370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2416467370 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.3421391113
Short name T401
Test name
Test status
Simulation time 673144711 ps
CPU time 6.02 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 04:13:01 PM PDT 24
Peak memory 218252 kb
Host smart-7d5fe8af-8e90-4d72-b112-440492d20a76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421391113 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.3421391113 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.496550775
Short name T777
Test name
Test status
Simulation time 1069897108 ps
CPU time 6.96 seconds
Started Apr 25 04:12:53 PM PDT 24
Finished Apr 25 04:13:00 PM PDT 24
Peak memory 218224 kb
Host smart-a93267fa-6e56-4d55-a11b-b4dd727145af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496550775 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.kmac_test_vectors_kmac_xof.496550775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1472162251
Short name T203
Test name
Test status
Simulation time 25145129744 ps
CPU time 1959.35 seconds
Started Apr 25 04:12:48 PM PDT 24
Finished Apr 25 04:45:28 PM PDT 24
Peak memory 387084 kb
Host smart-49094570-9d85-4f9d-9f12-175e88572caa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1472162251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1472162251 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.1287159386
Short name T901
Test name
Test status
Simulation time 33989985818 ps
CPU time 1711.7 seconds
Started Apr 25 04:12:48 PM PDT 24
Finished Apr 25 04:41:21 PM PDT 24
Peak memory 388440 kb
Host smart-0810ad8d-a878-4122-8b9a-bb4064546cc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1287159386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.1287159386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.254547346
Short name T754
Test name
Test status
Simulation time 73514924930 ps
CPU time 1821.35 seconds
Started Apr 25 04:12:48 PM PDT 24
Finished Apr 25 04:43:10 PM PDT 24
Peak memory 340308 kb
Host smart-94cabc28-1282-45c8-93ed-1be152a9a942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=254547346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.254547346 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.2506301472
Short name T263
Test name
Test status
Simulation time 33537786519 ps
CPU time 1172.03 seconds
Started Apr 25 04:12:55 PM PDT 24
Finished Apr 25 04:32:28 PM PDT 24
Peak memory 298688 kb
Host smart-8d79a5e6-faac-4e63-803b-9883adf13ca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2506301472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2506301472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.4020610368
Short name T183
Test name
Test status
Simulation time 724766651232 ps
CPU time 5059.74 seconds
Started Apr 25 04:12:54 PM PDT 24
Finished Apr 25 05:37:15 PM PDT 24
Peak memory 672372 kb
Host smart-10971791-ecc9-47bf-ad7d-cedebf024c54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4020610368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.4020610368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.3855174535
Short name T481
Test name
Test status
Simulation time 108440318577 ps
CPU time 4347.02 seconds
Started Apr 25 04:12:53 PM PDT 24
Finished Apr 25 05:25:21 PM PDT 24
Peak memory 565616 kb
Host smart-9e9e720d-b114-404c-9395-1eeb22579148
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3855174535 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.3855174535 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.2151685496
Short name T566
Test name
Test status
Simulation time 35664681 ps
CPU time 0.87 seconds
Started Apr 25 03:57:38 PM PDT 24
Finished Apr 25 03:57:40 PM PDT 24
Peak memory 217896 kb
Host smart-29b48294-e77c-42a2-bde1-3781f37eaa43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151685496 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2151685496 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.292130784
Short name T798
Test name
Test status
Simulation time 2921979434 ps
CPU time 23.01 seconds
Started Apr 25 03:57:26 PM PDT 24
Finished Apr 25 03:57:50 PM PDT 24
Peak memory 221476 kb
Host smart-ba4065f2-ddd4-456d-9d7e-4a59118d1822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292130784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.292130784 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.4130746243
Short name T254
Test name
Test status
Simulation time 6080166356 ps
CPU time 195.58 seconds
Started Apr 25 03:57:28 PM PDT 24
Finished Apr 25 04:00:44 PM PDT 24
Peak memory 241672 kb
Host smart-9c3cac76-b3ed-4ea0-97ac-9a93deca407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130746243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.4130746243 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.3085802890
Short name T762
Test name
Test status
Simulation time 448942469 ps
CPU time 32.11 seconds
Started Apr 25 03:57:12 PM PDT 24
Finished Apr 25 03:57:45 PM PDT 24
Peak memory 223748 kb
Host smart-d3c337a6-b2d1-4078-897f-d1f351aae278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085802890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3085802890 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1951186751
Short name T897
Test name
Test status
Simulation time 75974538 ps
CPU time 3.91 seconds
Started Apr 25 03:57:34 PM PDT 24
Finished Apr 25 03:57:39 PM PDT 24
Peak memory 226148 kb
Host smart-28f6065b-9df9-46d5-9015-94c435823793
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1951186751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1951186751 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1148898617
Short name T979
Test name
Test status
Simulation time 525077445 ps
CPU time 1.38 seconds
Started Apr 25 03:57:33 PM PDT 24
Finished Apr 25 03:57:35 PM PDT 24
Peak memory 221544 kb
Host smart-1c8516f5-7e8b-47ca-ad9e-cc648911c3d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1148898617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1148898617 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.2051673045
Short name T725
Test name
Test status
Simulation time 2111731844 ps
CPU time 20.86 seconds
Started Apr 25 03:57:32 PM PDT 24
Finished Apr 25 03:57:54 PM PDT 24
Peak memory 218308 kb
Host smart-9bf782ec-73e1-4b43-a7b4-6b67abd7a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051673045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.2051673045 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2304654577
Short name T268
Test name
Test status
Simulation time 633721800 ps
CPU time 32.67 seconds
Started Apr 25 03:57:29 PM PDT 24
Finished Apr 25 03:58:03 PM PDT 24
Peak memory 233428 kb
Host smart-3a66abed-d87f-4b2b-b4e9-c6545e506aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304654577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2304654577 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.2085927566
Short name T826
Test name
Test status
Simulation time 13379171379 ps
CPU time 102.33 seconds
Started Apr 25 03:57:32 PM PDT 24
Finished Apr 25 03:59:16 PM PDT 24
Peak memory 242756 kb
Host smart-abfde8db-4749-4dfe-8ddd-4ff53f52e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085927566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2085927566 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.2827339234
Short name T292
Test name
Test status
Simulation time 128177602 ps
CPU time 1.4 seconds
Started Apr 25 03:57:30 PM PDT 24
Finished Apr 25 03:57:32 PM PDT 24
Peak memory 218084 kb
Host smart-b907634a-9a4b-4206-9900-5b8979e5fc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827339234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2827339234 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.2341266421
Short name T24
Test name
Test status
Simulation time 146571990 ps
CPU time 1.51 seconds
Started Apr 25 03:57:35 PM PDT 24
Finished Apr 25 03:57:37 PM PDT 24
Peak memory 218200 kb
Host smart-f9d2cda4-5ee8-429b-8beb-2d99901ca33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341266421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2341266421 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.4292383403
Short name T708
Test name
Test status
Simulation time 10182754283 ps
CPU time 1051.69 seconds
Started Apr 25 03:57:07 PM PDT 24
Finished Apr 25 04:14:40 PM PDT 24
Peak memory 319836 kb
Host smart-6f336367-f763-40ff-8cf6-6580dbe40fc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292383403 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.4292383403 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.3265647515
Short name T778
Test name
Test status
Simulation time 4116161496 ps
CPU time 21.74 seconds
Started Apr 25 03:57:27 PM PDT 24
Finished Apr 25 03:57:50 PM PDT 24
Peak memory 226620 kb
Host smart-2822e1c1-8900-4175-b45c-16c528e7f5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265647515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.3265647515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.2577175720
Short name T606
Test name
Test status
Simulation time 31146142833 ps
CPU time 486.82 seconds
Started Apr 25 03:57:06 PM PDT 24
Finished Apr 25 04:05:14 PM PDT 24
Peak memory 258320 kb
Host smart-34756454-02a4-412c-826e-070da7fff681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577175720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2577175720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.312965272
Short name T431
Test name
Test status
Simulation time 7646677483 ps
CPU time 77.12 seconds
Started Apr 25 03:57:10 PM PDT 24
Finished Apr 25 03:58:28 PM PDT 24
Peak memory 222832 kb
Host smart-16171c20-6095-4ceb-a7d3-f81e1466f3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312965272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.312965272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.2037736825
Short name T1021
Test name
Test status
Simulation time 244432884195 ps
CPU time 1889.22 seconds
Started Apr 25 03:57:33 PM PDT 24
Finished Apr 25 04:29:04 PM PDT 24
Peak memory 356672 kb
Host smart-933bbf6f-e313-4558-aadc-c79881cd9376
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2037736825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2037736825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.611197951
Short name T131
Test name
Test status
Simulation time 40833962703 ps
CPU time 1744.45 seconds
Started Apr 25 03:57:35 PM PDT 24
Finished Apr 25 04:26:41 PM PDT 24
Peak memory 353056 kb
Host smart-c5c8ae90-9d89-415e-9965-7169fd77a0e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611197951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.611197951 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.2357693329
Short name T993
Test name
Test status
Simulation time 387156203 ps
CPU time 6.22 seconds
Started Apr 25 03:57:17 PM PDT 24
Finished Apr 25 03:57:24 PM PDT 24
Peak memory 218124 kb
Host smart-64dbdea6-a679-4da0-b264-e13e70ccfbb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357693329 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.kmac_test_vectors_kmac.2357693329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.3522784151
Short name T786
Test name
Test status
Simulation time 91113481 ps
CPU time 5.89 seconds
Started Apr 25 03:57:21 PM PDT 24
Finished Apr 25 03:57:28 PM PDT 24
Peak memory 218152 kb
Host smart-988fdacd-fd95-444e-9287-e7294e671c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522784151 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.3522784151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.2179112205
Short name T244
Test name
Test status
Simulation time 265667975496 ps
CPU time 2356.13 seconds
Started Apr 25 03:57:14 PM PDT 24
Finished Apr 25 04:36:31 PM PDT 24
Peak memory 387788 kb
Host smart-01c40d3b-0f16-4775-85a6-fea69e9d1ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2179112205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2179112205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.1998873532
Short name T330
Test name
Test status
Simulation time 80954451597 ps
CPU time 1884.66 seconds
Started Apr 25 03:57:14 PM PDT 24
Finished Apr 25 04:28:40 PM PDT 24
Peak memory 392896 kb
Host smart-2a6f3243-fbc5-4d67-80b1-f7654ae0b4a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1998873532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.1998873532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.1350060255
Short name T898
Test name
Test status
Simulation time 64928972514 ps
CPU time 1799.53 seconds
Started Apr 25 03:57:12 PM PDT 24
Finished Apr 25 04:27:13 PM PDT 24
Peak memory 343624 kb
Host smart-137261fa-12f2-42a7-805e-70afd59433f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1350060255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.1350060255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.2154308515
Short name T571
Test name
Test status
Simulation time 136184082112 ps
CPU time 1434.82 seconds
Started Apr 25 03:57:19 PM PDT 24
Finished Apr 25 04:21:15 PM PDT 24
Peak memory 296792 kb
Host smart-a2b3c67f-2cce-44e5-bff6-ea94fa6d72ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2154308515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2154308515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.655676976
Short name T193
Test name
Test status
Simulation time 63173106155 ps
CPU time 4802.29 seconds
Started Apr 25 03:57:20 PM PDT 24
Finished Apr 25 05:17:24 PM PDT 24
Peak memory 645964 kb
Host smart-d3f32ea1-868f-416c-9e49-e2fff215caef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=655676976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.655676976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.897857843
Short name T420
Test name
Test status
Simulation time 90771320927 ps
CPU time 4125.11 seconds
Started Apr 25 03:57:17 PM PDT 24
Finished Apr 25 05:06:04 PM PDT 24
Peak memory 571184 kb
Host smart-14ee4e73-523c-431d-a468-3258fcebe7cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=897857843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.897857843 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.492196836
Short name T981
Test name
Test status
Simulation time 13707272 ps
CPU time 0.88 seconds
Started Apr 25 03:58:08 PM PDT 24
Finished Apr 25 03:58:11 PM PDT 24
Peak memory 217880 kb
Host smart-c4592c8d-89fa-4278-a83c-a8e83ee818d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492196836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.492196836 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.1835547686
Short name T747
Test name
Test status
Simulation time 21074167696 ps
CPU time 45.56 seconds
Started Apr 25 03:57:54 PM PDT 24
Finished Apr 25 03:58:41 PM PDT 24
Peak memory 226472 kb
Host smart-777d7b32-6ee4-4bc9-8b12-1f3505b6bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835547686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.1835547686 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.487547261
Short name T102
Test name
Test status
Simulation time 10141855205 ps
CPU time 257.57 seconds
Started Apr 25 03:57:53 PM PDT 24
Finished Apr 25 04:02:13 PM PDT 24
Peak memory 242732 kb
Host smart-0ea1bc7c-9986-48ef-bc6b-93e5eda259b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487547261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.487547261 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_burst_write.471751411
Short name T639
Test name
Test status
Simulation time 35473467852 ps
CPU time 1416.12 seconds
Started Apr 25 03:57:37 PM PDT 24
Finished Apr 25 04:21:14 PM PDT 24
Peak memory 238380 kb
Host smart-7e67be97-2c83-43d5-a142-91431860947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471751411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.471751411 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_burst_write/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.3274862714
Short name T892
Test name
Test status
Simulation time 37957465 ps
CPU time 1.24 seconds
Started Apr 25 03:58:01 PM PDT 24
Finished Apr 25 03:58:04 PM PDT 24
Peak memory 222580 kb
Host smart-d361dde0-8b49-473e-8263-5b4daaaa6628
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3274862714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.3274862714 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.1766729578
Short name T191
Test name
Test status
Simulation time 2771358756 ps
CPU time 36.62 seconds
Started Apr 25 03:58:03 PM PDT 24
Finished Apr 25 03:58:41 PM PDT 24
Peak memory 226172 kb
Host smart-eae0c258-8f6a-423a-b78a-8332f6f39aa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766729578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1766729578 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.686765707
Short name T54
Test name
Test status
Simulation time 924521951 ps
CPU time 48.09 seconds
Started Apr 25 03:58:05 PM PDT 24
Finished Apr 25 03:58:54 PM PDT 24
Peak memory 219280 kb
Host smart-93b93b4d-e1a9-42b5-94e7-1830daa63588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686765707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.686765707 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.4257511667
Short name T243
Test name
Test status
Simulation time 13286403270 ps
CPU time 66.5 seconds
Started Apr 25 03:57:57 PM PDT 24
Finished Apr 25 03:59:05 PM PDT 24
Peak memory 227980 kb
Host smart-55d85ce7-bff0-43c1-8bf1-d772e3d3e67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257511667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.4257511667 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.3869228167
Short name T911
Test name
Test status
Simulation time 1558704517 ps
CPU time 112.04 seconds
Started Apr 25 03:57:56 PM PDT 24
Finished Apr 25 03:59:50 PM PDT 24
Peak memory 242656 kb
Host smart-c1611515-7e69-4f2b-bf96-01cfbe16e67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869228167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3869228167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.4211377167
Short name T882
Test name
Test status
Simulation time 164634830 ps
CPU time 1.39 seconds
Started Apr 25 03:58:02 PM PDT 24
Finished Apr 25 03:58:05 PM PDT 24
Peak memory 218044 kb
Host smart-3e78165b-0237-4d38-9e8e-2028631eecbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211377167 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.4211377167 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.3450849782
Short name T461
Test name
Test status
Simulation time 36004034 ps
CPU time 1.36 seconds
Started Apr 25 03:58:06 PM PDT 24
Finished Apr 25 03:58:09 PM PDT 24
Peak memory 218128 kb
Host smart-1a7cf12d-3cd4-4c78-ae73-89692e0a78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450849782 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3450849782 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2279898359
Short name T776
Test name
Test status
Simulation time 3825039196 ps
CPU time 433.45 seconds
Started Apr 25 03:57:37 PM PDT 24
Finished Apr 25 04:04:51 PM PDT 24
Peak memory 258088 kb
Host smart-9a8fd390-fa61-45e1-b07b-d0279b1fc2ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279898359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2279898359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1737935135
Short name T1013
Test name
Test status
Simulation time 12864201773 ps
CPU time 224.74 seconds
Started Apr 25 03:57:58 PM PDT 24
Finished Apr 25 04:01:44 PM PDT 24
Peak memory 243240 kb
Host smart-f8efb7ac-bbda-44d1-a324-ffe986cfb9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737935135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1737935135 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.2423552642
Short name T840
Test name
Test status
Simulation time 37619360118 ps
CPU time 262.79 seconds
Started Apr 25 03:57:38 PM PDT 24
Finished Apr 25 04:02:01 PM PDT 24
Peak memory 240280 kb
Host smart-b3340f88-7c6a-48af-9f2c-0cd841b0aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423552642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.2423552642 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1072259110
Short name T272
Test name
Test status
Simulation time 8041866218 ps
CPU time 96.62 seconds
Started Apr 25 03:57:35 PM PDT 24
Finished Apr 25 03:59:13 PM PDT 24
Peak memory 222488 kb
Host smart-ca613171-30b5-4d81-9697-5b5d519cd234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072259110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1072259110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.2089107538
Short name T617
Test name
Test status
Simulation time 99552419678 ps
CPU time 2496.04 seconds
Started Apr 25 03:58:08 PM PDT 24
Finished Apr 25 04:39:46 PM PDT 24
Peak memory 418856 kb
Host smart-7b4b5399-95b0-409f-a723-fa446c2bd157
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2089107538 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.2089107538 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.1047723154
Short name T352
Test name
Test status
Simulation time 1516061732 ps
CPU time 6.33 seconds
Started Apr 25 03:57:46 PM PDT 24
Finished Apr 25 03:57:54 PM PDT 24
Peak memory 218164 kb
Host smart-9f2ec9be-14aa-499f-84b3-4c216f15d011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047723154 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.1047723154 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.1696569198
Short name T931
Test name
Test status
Simulation time 2763878069 ps
CPU time 6.24 seconds
Started Apr 25 03:57:51 PM PDT 24
Finished Apr 25 03:57:59 PM PDT 24
Peak memory 218284 kb
Host smart-98b2a4dc-61ac-43cc-b5b2-fa5532629c78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696569198 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.kmac_test_vectors_kmac_xof.1696569198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.418721123
Short name T794
Test name
Test status
Simulation time 84549000449 ps
CPU time 2078.59 seconds
Started Apr 25 03:57:41 PM PDT 24
Finished Apr 25 04:32:20 PM PDT 24
Peak memory 394928 kb
Host smart-d269c18c-1fd3-4d27-beb7-52e7837ee8a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=418721123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.418721123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2992788663
Short name T436
Test name
Test status
Simulation time 83767803024 ps
CPU time 2105.43 seconds
Started Apr 25 03:57:42 PM PDT 24
Finished Apr 25 04:32:48 PM PDT 24
Peak memory 385728 kb
Host smart-ae976eb5-c7d0-44a6-b273-264482b6f78e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2992788663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2992788663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.1709798260
Short name T261
Test name
Test status
Simulation time 49586608204 ps
CPU time 1677.02 seconds
Started Apr 25 03:57:43 PM PDT 24
Finished Apr 25 04:25:41 PM PDT 24
Peak memory 340532 kb
Host smart-ee33ec8a-baa0-4bf7-b041-e7bf9dba2718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1709798260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1709798260 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.2069192693
Short name T869
Test name
Test status
Simulation time 50303187388 ps
CPU time 1354.85 seconds
Started Apr 25 03:57:43 PM PDT 24
Finished Apr 25 04:20:19 PM PDT 24
Peak memory 298384 kb
Host smart-f8183a8d-d8b0-4e87-a4bc-67b43bf242a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2069192693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.2069192693 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.1031592504
Short name T976
Test name
Test status
Simulation time 584765937275 ps
CPU time 6490.22 seconds
Started Apr 25 03:57:48 PM PDT 24
Finished Apr 25 05:46:01 PM PDT 24
Peak memory 657792 kb
Host smart-a216e237-4de0-4f44-ab09-2cd5e58aa1f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1031592504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.1031592504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.1400010247
Short name T112
Test name
Test status
Simulation time 55781179179 ps
CPU time 4091.79 seconds
Started Apr 25 03:57:47 PM PDT 24
Finished Apr 25 05:06:01 PM PDT 24
Peak memory 584488 kb
Host smart-3660beff-b94e-45c4-951b-7b6ccc5de620
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1400010247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.1400010247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.3676622119
Short name T560
Test name
Test status
Simulation time 14749898 ps
CPU time 0.83 seconds
Started Apr 25 03:58:40 PM PDT 24
Finished Apr 25 03:58:41 PM PDT 24
Peak memory 217872 kb
Host smart-d34f0d77-9a05-4a30-a8e1-7bff5a23da0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676622119 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.3676622119 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.4053377689
Short name T200
Test name
Test status
Simulation time 15557695175 ps
CPU time 198.71 seconds
Started Apr 25 03:58:22 PM PDT 24
Finished Apr 25 04:01:41 PM PDT 24
Peak memory 239676 kb
Host smart-12233bad-5961-43e1-876d-b4eac95b40f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053377689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.4053377689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_app_with_partial_data.1496562529
Short name T101
Test name
Test status
Simulation time 5616755637 ps
CPU time 125.98 seconds
Started Apr 25 03:58:18 PM PDT 24
Finished Apr 25 04:00:25 PM PDT 24
Peak memory 234528 kb
Host smart-8db016f0-eaed-4228-999b-93c4cdfb245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496562529 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.1496562529 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/7.kmac_burst_write.20094162
Short name T582
Test name
Test status
Simulation time 111638704489 ps
CPU time 731.04 seconds
Started Apr 25 03:58:06 PM PDT 24
Finished Apr 25 04:10:19 PM PDT 24
Peak memory 232976 kb
Host smart-0296e18b-6dd2-4715-83a0-454512673c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20094162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.20094162 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.1674735477
Short name T350
Test name
Test status
Simulation time 131861102 ps
CPU time 1.3 seconds
Started Apr 25 03:58:39 PM PDT 24
Finished Apr 25 03:58:41 PM PDT 24
Peak memory 221840 kb
Host smart-5c5f9b3e-8bca-4a72-85c8-6b8ca356eea8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1674735477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1674735477 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3641116339
Short name T387
Test name
Test status
Simulation time 9932742161 ps
CPU time 56.77 seconds
Started Apr 25 03:58:33 PM PDT 24
Finished Apr 25 03:59:31 PM PDT 24
Peak memory 219972 kb
Host smart-ec8411f9-c732-4266-8f68-c41d1950a95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641116339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3641116339 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.4008360361
Short name T645
Test name
Test status
Simulation time 28079922703 ps
CPU time 139.31 seconds
Started Apr 25 03:58:21 PM PDT 24
Finished Apr 25 04:00:41 PM PDT 24
Peak memory 233476 kb
Host smart-33c1adaf-c23b-4933-8f91-aec5d90a9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008360361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.4008360361 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.902953623
Short name T470
Test name
Test status
Simulation time 19011744638 ps
CPU time 352.2 seconds
Started Apr 25 03:58:26 PM PDT 24
Finished Apr 25 04:04:19 PM PDT 24
Peak memory 259112 kb
Host smart-2da557f5-4715-46b9-8826-e85ce91d3e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902953623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.902953623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.1908356545
Short name T740
Test name
Test status
Simulation time 896279206 ps
CPU time 4.17 seconds
Started Apr 25 03:58:27 PM PDT 24
Finished Apr 25 03:58:32 PM PDT 24
Peak memory 218108 kb
Host smart-81d2752d-b877-4864-abcd-cc2e476cf06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908356545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1908356545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.1344615812
Short name T66
Test name
Test status
Simulation time 55661123 ps
CPU time 1.3 seconds
Started Apr 25 03:58:30 PM PDT 24
Finished Apr 25 03:58:32 PM PDT 24
Peak memory 218200 kb
Host smart-26da0691-c04c-4635-9503-d43c371951d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344615812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1344615812 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.1132719859
Short name T426
Test name
Test status
Simulation time 51385257963 ps
CPU time 1369.26 seconds
Started Apr 25 03:58:08 PM PDT 24
Finished Apr 25 04:20:59 PM PDT 24
Peak memory 324444 kb
Host smart-c7f69006-9bf7-4aac-82d2-9caee28d474b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132719859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.1132719859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.2450307593
Short name T954
Test name
Test status
Simulation time 175308375472 ps
CPU time 355.58 seconds
Started Apr 25 03:58:28 PM PDT 24
Finished Apr 25 04:04:24 PM PDT 24
Peak memory 247920 kb
Host smart-ab027999-25e6-4f32-b4f4-5d45666d11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450307593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.2450307593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.3969233575
Short name T604
Test name
Test status
Simulation time 15127164864 ps
CPU time 220.25 seconds
Started Apr 25 03:58:06 PM PDT 24
Finished Apr 25 04:01:47 PM PDT 24
Peak memory 238784 kb
Host smart-5574ee8b-6c0a-43f9-adc1-2c0f704d6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969233575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3969233575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.2982639941
Short name T920
Test name
Test status
Simulation time 1904586254 ps
CPU time 75.91 seconds
Started Apr 25 03:58:06 PM PDT 24
Finished Apr 25 03:59:24 PM PDT 24
Peak memory 226356 kb
Host smart-a2a9c857-ce44-44a0-b0ee-8516c48ecab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982639941 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.2982639941 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.2189173781
Short name T454
Test name
Test status
Simulation time 201072246279 ps
CPU time 1461.46 seconds
Started Apr 25 03:58:34 PM PDT 24
Finished Apr 25 04:22:56 PM PDT 24
Peak memory 353960 kb
Host smart-7add505d-51a6-4eed-b697-e5a9bd580cdd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2189173781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.2189173781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.2444781877
Short name T133
Test name
Test status
Simulation time 139976021446 ps
CPU time 1249.81 seconds
Started Apr 25 03:58:40 PM PDT 24
Finished Apr 25 04:19:31 PM PDT 24
Peak memory 307732 kb
Host smart-66d9fb79-3f3d-4623-ad67-6ee9aea010ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444781877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.2444781877 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.1216657274
Short name T217
Test name
Test status
Simulation time 1084096949 ps
CPU time 7.16 seconds
Started Apr 25 03:58:15 PM PDT 24
Finished Apr 25 03:58:23 PM PDT 24
Peak memory 218256 kb
Host smart-b8793a41-3990-472d-9067-d6a43802760b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216657274 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.1216657274 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.2326936899
Short name T638
Test name
Test status
Simulation time 252068301 ps
CPU time 7.07 seconds
Started Apr 25 03:58:15 PM PDT 24
Finished Apr 25 03:58:23 PM PDT 24
Peak memory 218184 kb
Host smart-a2a6cc44-8a99-478a-9275-dfb51aea37f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326936899 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.2326936899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.368336153
Short name T648
Test name
Test status
Simulation time 221749260749 ps
CPU time 2141.65 seconds
Started Apr 25 03:58:13 PM PDT 24
Finished Apr 25 04:33:56 PM PDT 24
Peak memory 389696 kb
Host smart-0ef977ab-a1de-4d33-b12b-73da74f975b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=368336153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.368336153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.3314340744
Short name T378
Test name
Test status
Simulation time 114599841567 ps
CPU time 1959.77 seconds
Started Apr 25 03:58:13 PM PDT 24
Finished Apr 25 04:30:55 PM PDT 24
Peak memory 383256 kb
Host smart-ab4364bc-8cd3-428e-9681-09f9fb09eda2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3314340744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.3314340744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.863629383
Short name T925
Test name
Test status
Simulation time 83370796317 ps
CPU time 1544.71 seconds
Started Apr 25 03:58:11 PM PDT 24
Finished Apr 25 04:23:58 PM PDT 24
Peak memory 339548 kb
Host smart-fb26eb3a-073e-4c5b-8464-d1b60fd59784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=863629383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.863629383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.1171018005
Short name T341
Test name
Test status
Simulation time 22115912191 ps
CPU time 1292.09 seconds
Started Apr 25 03:58:11 PM PDT 24
Finished Apr 25 04:19:44 PM PDT 24
Peak memory 300244 kb
Host smart-db513a4d-cc46-440b-907e-3e20bb3f6492
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1171018005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.1171018005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.65869144
Short name T374
Test name
Test status
Simulation time 246978774950 ps
CPU time 4865.33 seconds
Started Apr 25 03:58:16 PM PDT 24
Finished Apr 25 05:19:23 PM PDT 24
Peak memory 651560 kb
Host smart-f0eae373-fbb5-4530-a55e-bf6a366f740c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=65869144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.65869144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.3692973729
Short name T216
Test name
Test status
Simulation time 385181496901 ps
CPU time 4629.99 seconds
Started Apr 25 03:58:15 PM PDT 24
Finished Apr 25 05:15:27 PM PDT 24
Peak memory 569592 kb
Host smart-3bb91016-884e-4581-9a0c-f1d3e4005689
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3692973729 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.3692973729 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.2381685245
Short name T550
Test name
Test status
Simulation time 14649801 ps
CPU time 0.86 seconds
Started Apr 25 03:59:00 PM PDT 24
Finished Apr 25 03:59:02 PM PDT 24
Peak memory 217900 kb
Host smart-fc877f80-e596-4c10-b5be-72e7edc6ccd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381685245 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2381685245 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.4006213035
Short name T768
Test name
Test status
Simulation time 2639900500 ps
CPU time 57.37 seconds
Started Apr 25 03:58:51 PM PDT 24
Finished Apr 25 03:59:49 PM PDT 24
Peak memory 227964 kb
Host smart-3bbf8f61-d6e0-493a-9120-3e24390c2a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006213035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.4006213035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.1082626025
Short name T438
Test name
Test status
Simulation time 31406704378 ps
CPU time 170.33 seconds
Started Apr 25 03:58:53 PM PDT 24
Finished Apr 25 04:01:45 PM PDT 24
Peak memory 242680 kb
Host smart-90c0d276-3695-48d0-b495-f6d88ff07b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082626025 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1082626025 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.4165422324
Short name T50
Test name
Test status
Simulation time 40963858496 ps
CPU time 343.79 seconds
Started Apr 25 03:58:46 PM PDT 24
Finished Apr 25 04:04:31 PM PDT 24
Peak memory 229104 kb
Host smart-03997421-d0b2-4849-adaa-e1e2ac34e789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165422324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.4165422324 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2163896946
Short name T285
Test name
Test status
Simulation time 1419404121 ps
CPU time 43.81 seconds
Started Apr 25 03:58:56 PM PDT 24
Finished Apr 25 03:59:40 PM PDT 24
Peak memory 227228 kb
Host smart-3449ba92-089f-4d80-bd4a-041cac35c3ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2163896946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2163896946 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.2632463869
Short name T705
Test name
Test status
Simulation time 341035231 ps
CPU time 27.39 seconds
Started Apr 25 03:58:55 PM PDT 24
Finished Apr 25 03:59:23 PM PDT 24
Peak memory 223684 kb
Host smart-8d7b7c7a-e0a5-45fe-9522-1848ca19b989
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2632463869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2632463869 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.2367250804
Short name T1016
Test name
Test status
Simulation time 40192479887 ps
CPU time 225.85 seconds
Started Apr 25 03:58:52 PM PDT 24
Finished Apr 25 04:02:39 PM PDT 24
Peak memory 240392 kb
Host smart-38b5cb44-d6ea-4402-b8f3-8e6c652a05c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367250804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2367250804 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.272009341
Short name T839
Test name
Test status
Simulation time 18826274984 ps
CPU time 444.95 seconds
Started Apr 25 03:58:55 PM PDT 24
Finished Apr 25 04:06:21 PM PDT 24
Peak memory 267348 kb
Host smart-3ee6a24b-f285-4bcb-b571-aa2486bc8df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272009341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.272009341 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.1344028832
Short name T1042
Test name
Test status
Simulation time 325688282 ps
CPU time 2.46 seconds
Started Apr 25 03:58:56 PM PDT 24
Finished Apr 25 03:58:59 PM PDT 24
Peak memory 218084 kb
Host smart-3f65cc02-0886-4b26-8b87-52cd350280fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344028832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.1344028832 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1523037775
Short name T35
Test name
Test status
Simulation time 43522710 ps
CPU time 1.43 seconds
Started Apr 25 03:59:01 PM PDT 24
Finished Apr 25 03:59:03 PM PDT 24
Peak memory 218216 kb
Host smart-a5b9dcfa-15c2-4714-a719-2dcf830ff033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523037775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1523037775 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.2238275101
Short name T625
Test name
Test status
Simulation time 94955645465 ps
CPU time 2477.58 seconds
Started Apr 25 03:58:40 PM PDT 24
Finished Apr 25 04:39:59 PM PDT 24
Peak memory 432428 kb
Host smart-97723213-f38d-44ac-b364-2d32b3815122
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238275101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.2238275101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.2008689456
Short name T982
Test name
Test status
Simulation time 13114124726 ps
CPU time 316.25 seconds
Started Apr 25 03:58:53 PM PDT 24
Finished Apr 25 04:04:10 PM PDT 24
Peak memory 247804 kb
Host smart-4868a047-5392-40f4-9734-dedd848b65c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008689456 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.2008689456 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3279048003
Short name T887
Test name
Test status
Simulation time 18598239522 ps
CPU time 125.6 seconds
Started Apr 25 03:58:41 PM PDT 24
Finished Apr 25 04:00:48 PM PDT 24
Peak memory 231828 kb
Host smart-161a8e79-fb81-4b9f-9967-73e311a71094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279048003 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3279048003 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.1329903717
Short name T874
Test name
Test status
Simulation time 9061741695 ps
CPU time 25.41 seconds
Started Apr 25 03:58:41 PM PDT 24
Finished Apr 25 03:59:07 PM PDT 24
Peak memory 225976 kb
Host smart-8b437823-f072-4e58-a97b-5bf3bb7dfa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329903717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.1329903717 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.1702369916
Short name T990
Test name
Test status
Simulation time 406103732283 ps
CPU time 1887.97 seconds
Started Apr 25 03:59:02 PM PDT 24
Finished Apr 25 04:30:31 PM PDT 24
Peak memory 401432 kb
Host smart-a5dcc0c8-6994-43b1-947a-dd329ceedb2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1702369916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1702369916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.3778903388
Short name T396
Test name
Test status
Simulation time 874707377 ps
CPU time 6.73 seconds
Started Apr 25 03:58:51 PM PDT 24
Finished Apr 25 03:58:58 PM PDT 24
Peak memory 218212 kb
Host smart-cd30e1a2-ae6c-4864-b2a9-fc2027bbfb12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778903388 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.kmac_test_vectors_kmac.3778903388 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1434282004
Short name T863
Test name
Test status
Simulation time 184236155 ps
CPU time 5.55 seconds
Started Apr 25 03:58:53 PM PDT 24
Finished Apr 25 03:58:59 PM PDT 24
Peak memory 218184 kb
Host smart-72e35f35-b5db-435b-b928-f610e99519ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434282004 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1434282004 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.1169290771
Short name T549
Test name
Test status
Simulation time 24298820212 ps
CPU time 1916.76 seconds
Started Apr 25 03:58:46 PM PDT 24
Finished Apr 25 04:30:44 PM PDT 24
Peak memory 398832 kb
Host smart-c7ad0b7f-704f-437f-89d0-9c11a1abbc61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1169290771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.1169290771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.900933039
Short name T515
Test name
Test status
Simulation time 106588254531 ps
CPU time 2269.67 seconds
Started Apr 25 03:58:50 PM PDT 24
Finished Apr 25 04:36:41 PM PDT 24
Peak memory 386184 kb
Host smart-2f1d546f-0cc8-4d20-b99a-29a74d6953b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=900933039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.900933039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.2266317485
Short name T693
Test name
Test status
Simulation time 192869372455 ps
CPU time 1848.05 seconds
Started Apr 25 03:58:46 PM PDT 24
Finished Apr 25 04:29:35 PM PDT 24
Peak memory 343328 kb
Host smart-5642e326-d894-4c30-8cbd-07f58319ac61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2266317485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.2266317485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.695951294
Short name T984
Test name
Test status
Simulation time 106532633135 ps
CPU time 1288.74 seconds
Started Apr 25 03:58:45 PM PDT 24
Finished Apr 25 04:20:14 PM PDT 24
Peak memory 301580 kb
Host smart-860451cc-1613-4d67-9497-9752e59d15e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=695951294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.695951294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.313158582
Short name T818
Test name
Test status
Simulation time 73103415024 ps
CPU time 4836.33 seconds
Started Apr 25 03:58:51 PM PDT 24
Finished Apr 25 05:19:29 PM PDT 24
Peak memory 655804 kb
Host smart-4b92f5b7-e9b4-4b8f-8a00-4e70fd16457f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=313158582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.313158582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.379735581
Short name T554
Test name
Test status
Simulation time 199268755818 ps
CPU time 4943.69 seconds
Started Apr 25 03:58:54 PM PDT 24
Finished Apr 25 05:21:19 PM PDT 24
Peak memory 574796 kb
Host smart-68f533e5-3e5e-4759-affb-b7a7ad9721e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=379735581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.379735581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.3839141238
Short name T799
Test name
Test status
Simulation time 15165390 ps
CPU time 0.88 seconds
Started Apr 25 03:59:32 PM PDT 24
Finished Apr 25 03:59:34 PM PDT 24
Peak memory 217876 kb
Host smart-59fb0736-3b77-4503-8ad1-8edc7cc4a380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839141238 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3839141238 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.803496866
Short name T875
Test name
Test status
Simulation time 6489751569 ps
CPU time 148.92 seconds
Started Apr 25 03:59:11 PM PDT 24
Finished Apr 25 04:01:40 PM PDT 24
Peak memory 236828 kb
Host smart-aef07932-af61-4ff5-a07f-ee71537c34a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803496866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.803496866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_burst_write.897989834
Short name T368
Test name
Test status
Simulation time 4868347702 ps
CPU time 494.49 seconds
Started Apr 25 03:59:10 PM PDT 24
Finished Apr 25 04:07:25 PM PDT 24
Peak memory 232340 kb
Host smart-c16d3ed3-fd50-40f2-8527-aed82cb53e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897989834 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.897989834 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.4024423673
Short name T922
Test name
Test status
Simulation time 748666432 ps
CPU time 45.24 seconds
Started Apr 25 03:59:57 PM PDT 24
Finished Apr 25 04:00:44 PM PDT 24
Peak memory 226152 kb
Host smart-3c106bd2-bfb7-4514-8b17-be7eaff87722
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4024423673 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.4024423673 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.3819194249
Short name T8
Test name
Test status
Simulation time 2125486173 ps
CPU time 42.46 seconds
Started Apr 25 03:59:19 PM PDT 24
Finished Apr 25 04:00:03 PM PDT 24
Peak memory 227684 kb
Host smart-24aeefe8-a1f0-45c4-b6be-c924063bba62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3819194249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.3819194249 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.4059836483
Short name T167
Test name
Test status
Simulation time 2545020410 ps
CPU time 18.2 seconds
Started Apr 25 03:59:29 PM PDT 24
Finished Apr 25 03:59:48 PM PDT 24
Peak memory 218376 kb
Host smart-454865df-5fae-48f2-b18a-b3958ddf2abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059836483 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.4059836483 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.3141697106
Short name T842
Test name
Test status
Simulation time 22187658882 ps
CPU time 412.09 seconds
Started Apr 25 03:59:16 PM PDT 24
Finished Apr 25 04:06:09 PM PDT 24
Peak memory 251064 kb
Host smart-00ee09ee-3728-4b64-ac23-144f4ca71752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141697106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.3141697106 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.3911892242
Short name T711
Test name
Test status
Simulation time 12386562834 ps
CPU time 242.9 seconds
Started Apr 25 03:59:19 PM PDT 24
Finished Apr 25 04:03:22 PM PDT 24
Peak memory 259112 kb
Host smart-3ffee01c-0043-45d3-905c-c70b6ec881c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911892242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3911892242 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.3809749461
Short name T825
Test name
Test status
Simulation time 1767652510 ps
CPU time 3.09 seconds
Started Apr 25 03:59:17 PM PDT 24
Finished Apr 25 03:59:20 PM PDT 24
Peak memory 218096 kb
Host smart-5f98d3ec-a887-496c-9c49-83ba0424410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809749461 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.3809749461 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.3227929872
Short name T84
Test name
Test status
Simulation time 59374310 ps
CPU time 1.29 seconds
Started Apr 25 03:59:29 PM PDT 24
Finished Apr 25 03:59:31 PM PDT 24
Peak memory 218188 kb
Host smart-2d1cfe2f-f72e-4981-9062-3caeee57cba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227929872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.3227929872 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.2945980818
Short name T143
Test name
Test status
Simulation time 43357573055 ps
CPU time 1459.14 seconds
Started Apr 25 03:59:05 PM PDT 24
Finished Apr 25 04:23:26 PM PDT 24
Peak memory 338636 kb
Host smart-66852735-8f22-40e1-bca3-8514ffc1b335
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945980818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an
d_output.2945980818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.3298448689
Short name T377
Test name
Test status
Simulation time 34678208677 ps
CPU time 321.84 seconds
Started Apr 25 03:59:19 PM PDT 24
Finished Apr 25 04:04:42 PM PDT 24
Peak memory 251432 kb
Host smart-1fe456f2-f3f2-4c22-951d-3e9193ef24b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298448689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.3298448689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.3354173410
Short name T696
Test name
Test status
Simulation time 1720669266 ps
CPU time 135.78 seconds
Started Apr 25 03:59:09 PM PDT 24
Finished Apr 25 04:01:26 PM PDT 24
Peak memory 234200 kb
Host smart-f8ee66e3-c567-4ec1-a743-53877455f67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354173410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.3354173410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.2966074674
Short name T985
Test name
Test status
Simulation time 3742831221 ps
CPU time 82.67 seconds
Started Apr 25 03:59:06 PM PDT 24
Finished Apr 25 04:00:29 PM PDT 24
Peak memory 223816 kb
Host smart-0b1cc519-c0ab-44a7-84a4-fc1b888c5149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966074674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2966074674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3101367875
Short name T80
Test name
Test status
Simulation time 4862127240 ps
CPU time 109.06 seconds
Started Apr 25 03:59:32 PM PDT 24
Finished Apr 25 04:01:22 PM PDT 24
Peak memory 250900 kb
Host smart-040cd078-d123-4d41-8e87-a76b96811962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3101367875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3101367875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.3157081724
Short name T601
Test name
Test status
Simulation time 179966097 ps
CPU time 6.25 seconds
Started Apr 25 03:59:13 PM PDT 24
Finished Apr 25 03:59:20 PM PDT 24
Peak memory 218196 kb
Host smart-b1aad772-c917-4f32-a4a7-360ff2356ff3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157081724 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.3157081724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3989389330
Short name T590
Test name
Test status
Simulation time 4463004135 ps
CPU time 6.44 seconds
Started Apr 25 03:59:11 PM PDT 24
Finished Apr 25 03:59:18 PM PDT 24
Peak memory 218272 kb
Host smart-4f7a9524-4861-456c-a871-6065fb683db3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989389330 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3989389330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.2935604685
Short name T991
Test name
Test status
Simulation time 133408318924 ps
CPU time 2339.04 seconds
Started Apr 25 03:59:05 PM PDT 24
Finished Apr 25 04:38:06 PM PDT 24
Peak memory 403228 kb
Host smart-6af470f6-54c9-40e0-9afa-c9346afdd799
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2935604685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.2935604685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.2896305352
Short name T656
Test name
Test status
Simulation time 22118708219 ps
CPU time 1892.26 seconds
Started Apr 25 03:59:10 PM PDT 24
Finished Apr 25 04:30:43 PM PDT 24
Peak memory 398160 kb
Host smart-e09ba2d0-69ef-4ec3-b155-e4b028ca224f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2896305352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.2896305352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.2537840730
Short name T866
Test name
Test status
Simulation time 293666431770 ps
CPU time 1802.85 seconds
Started Apr 25 03:59:09 PM PDT 24
Finished Apr 25 04:29:13 PM PDT 24
Peak memory 338904 kb
Host smart-1e7ec1a2-0cc4-4981-9f26-0d8169e4fcc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2537840730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2537840730 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.2203155445
Short name T500
Test name
Test status
Simulation time 197990597027 ps
CPU time 1360.09 seconds
Started Apr 25 03:59:07 PM PDT 24
Finished Apr 25 04:21:49 PM PDT 24
Peak memory 301752 kb
Host smart-8733017c-dac4-4cfb-96cd-89aefbdfeef8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2203155445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2203155445 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.3193268713
Short name T782
Test name
Test status
Simulation time 226195058114 ps
CPU time 4348.52 seconds
Started Apr 25 03:59:13 PM PDT 24
Finished Apr 25 05:11:43 PM PDT 24
Peak memory 573396 kb
Host smart-a6802fe4-2a99-4e18-ac56-336ec3eeb8ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3193268713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.3193268713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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