Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100491949	1			T3	161748		T4	309		T5	1180
all_values[1]	100491949	1			T3	161748		T4	309		T5	1180
all_values[2]	100491949	1			T3	161748		T4	309		T5	1180

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601824

1

T4

180

T5

42

T14

3

auto[1]

300874023

1

T3

485244

T4

747

T5

3498

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299940615

1

T3

483885

T4

882

T5

3030

auto[1]

1535232

1

T3

1359

T4

45

T5

510

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	217833	1			T4	4		T5	23		T6	40
all_values[0]	auto[0]	auto[1]	2249	1			T4	2		T5	4		T6	2
all_values[0]	auto[1]	auto[0]	99762372	1			T3	161295		T4	290		T5	987
all_values[0]	auto[1]	auto[1]	509495	1			T3	453		T4	13		T5	166
all_values[1]	auto[0]	auto[0]	180397	1			T5	13		T14	2		T6	39
all_values[1]	auto[0]	auto[1]	1656	1			T5	2		T14	1		T6	2
all_values[1]	auto[1]	auto[0]	99799808	1			T3	161295		T4	294		T5	997
all_values[1]	auto[1]	auto[1]	510088	1			T3	453		T4	15		T5	168
all_values[2]	auto[0]	auto[0]	198018	1			T4	165		T6	39		T7	739
all_values[2]	auto[0]	auto[1]	1671	1			T4	9		T6	2		T7	10
all_values[2]	auto[1]	auto[0]	99782187	1			T3	161295		T4	129		T5	1010
all_values[2]	auto[1]	auto[1]	510073	1			T3	453		T4	6		T5	170