Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
366216 |
1 |
|
|
T3 |
620 |
|
T4 |
2 |
|
T5 |
2 |
auto[1] |
329394 |
1 |
|
|
T4 |
16 |
|
T5 |
224 |
|
T12 |
272 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174710 |
1 |
|
|
T3 |
166 |
|
T4 |
2 |
|
T5 |
53 |
lower_val |
171814 |
1 |
|
|
T3 |
158 |
|
T4 |
4 |
|
T5 |
70 |
zero_val |
1905 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
265220 |
1 |
|
|
T3 |
272 |
|
T4 |
4 |
|
T5 |
50 |
lower_val |
265436 |
1 |
|
|
T3 |
348 |
|
T4 |
2 |
|
T5 |
72 |
zero_val |
164954 |
1 |
|
|
T4 |
12 |
|
T5 |
104 |
|
T12 |
134 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45591 |
1 |
|
|
T3 |
71 |
|
T6 |
22 |
|
T7 |
75 |
higher_val |
higher_val |
auto[1] |
20860 |
1 |
|
|
T5 |
19 |
|
T12 |
10 |
|
T13 |
12 |
higher_val |
lower_val |
auto[0] |
45674 |
1 |
|
|
T3 |
95 |
|
T6 |
22 |
|
T7 |
51 |
higher_val |
lower_val |
auto[1] |
20787 |
1 |
|
|
T4 |
1 |
|
T5 |
14 |
|
T12 |
12 |
higher_val |
zero_val |
auto[0] |
71 |
1 |
|
|
T7 |
1 |
|
T9 |
1 |
|
T152 |
1 |
higher_val |
zero_val |
auto[1] |
41727 |
1 |
|
|
T4 |
1 |
|
T5 |
20 |
|
T12 |
27 |
lower_val |
higher_val |
auto[0] |
45336 |
1 |
|
|
T3 |
59 |
|
T6 |
12 |
|
T7 |
64 |
lower_val |
higher_val |
auto[1] |
20316 |
1 |
|
|
T5 |
12 |
|
T12 |
18 |
|
T13 |
15 |
lower_val |
lower_val |
auto[0] |
45107 |
1 |
|
|
T3 |
99 |
|
T6 |
15 |
|
T7 |
54 |
lower_val |
lower_val |
auto[1] |
20419 |
1 |
|
|
T4 |
1 |
|
T5 |
19 |
|
T12 |
23 |
lower_val |
zero_val |
auto[0] |
98 |
1 |
|
|
T8 |
2 |
|
T30 |
1 |
|
T109 |
1 |
lower_val |
zero_val |
auto[1] |
40538 |
1 |
|
|
T4 |
3 |
|
T5 |
39 |
|
T12 |
33 |
zero_val |
higher_val |
auto[0] |
584 |
1 |
|
|
T5 |
1 |
|
T12 |
1 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
152 |
1 |
|
|
T7 |
3 |
|
T53 |
1 |
|
T29 |
2 |
zero_val |
lower_val |
auto[0] |
544 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
lower_val |
auto[1] |
157 |
1 |
|
|
T5 |
4 |
|
T8 |
2 |
|
T193 |
2 |
zero_val |
zero_val |
auto[0] |
264 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
zero_val |
auto[1] |
204 |
1 |
|
|
T7 |
2 |
|
T8 |
2 |
|
T29 |
1 |