Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10346	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9208	1			T3	24		T14	17		T7	18
len_5001_7500	14762	1			T3	24		T14	17		T7	31
len_2501_5000	9329	1			T3	24		T14	17		T7	7
len_1025_2500	5408	1			T3	14		T14	10		T7	5
len_769_1024	6227	1			T3	2		T12	17		T13	21
len_513_768	6588	1			T3	3		T12	32		T13	28
len_257_512	21096	1			T3	2		T12	18		T13	25
len_0_256	258360	1			T3	211		T4	9		T5	113
len_keccak_block_sizes[72]	722	1			T3	2		T12	1		T14	2
len_keccak_block_sizes[104]	618	1			T3	2		T14	2		T67	2
len_keccak_block_sizes[136]	516	1			T14	2		T67	2		T19	3
len_keccak_block_sizes[144]	421	1			T13	1		T14	2		T19	3
len_keccak_block_sizes[168]	335	1			T7	1		T19	3		T194	3
len_1	754	1			T3	2		T5	1		T13	1
len_0	1210	1			T3	2		T5	6		T14	2