Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100491949	1			T3	161748		T4	309		T5	1180
all_pins[1]	100491949	1			T3	161748		T4	309		T5	1180
all_pins[2]	100491949	1			T3	161748		T4	309		T5	1180

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300692393	1			T3	484791		T4	914		T5	3374
values[0x1]	783454	1			T3	453		T4	13		T5	166
transitions[0x0=>0x1]	781721	1			T3	453		T4	13		T5	166
transitions[0x1=>0x0]	781741	1			T3	453		T4	13		T5	166

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99982454	1			T3	161295		T4	296		T5	1014
all_pins[0]	values[0x1]	509495	1			T3	453		T4	13		T5	166
all_pins[0]	transitions[0x0=>0x1]	509482	1			T3	453		T4	13		T5	166
all_pins[0]	transitions[0x1=>0x0]	6730	1			T6	12		T7	116		T8	61
all_pins[1]	values[0x0]	100485206	1			T3	161748		T4	309		T5	1180
all_pins[1]	values[0x1]	6743	1			T6	12		T7	116		T8	61
all_pins[1]	transitions[0x0=>0x1]	6630	1			T6	12		T7	98		T8	56
all_pins[1]	transitions[0x1=>0x0]	267103	1			T7	9427		T8	2806		T33	593
all_pins[2]	values[0x0]	100224733	1			T3	161748		T4	309		T5	1180
all_pins[2]	values[0x1]	267216	1			T7	9445		T8	2811		T33	593
all_pins[2]	transitions[0x0=>0x1]	265609	1			T7	9381		T8	2790		T33	593
all_pins[2]	transitions[0x1=>0x0]	507908	1			T3	453		T4	13		T5	166