Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100696428	1			T1	22963		T2	3179		T3	159621
all_values[1]	100696428	1			T1	22963		T2	3179		T3	159621
all_values[2]	100696428	1			T1	22963		T2	3179		T3	159621

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

508285

1

T1

966

T3

3

T6

2500

auto[1]

301580999

1

T1

67923

T2

9537

T3

478860

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300561315

1

T1

68226

T2

9456

T3

477492

auto[1]

1527969

1

T1

663

T2

81

T3

1371

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	167098	1			T3	1		T6	1		T5	1
all_values[0]	auto[0]	auto[1]	2104	1			T3	2		T5	2		T8	2
all_values[0]	auto[1]	auto[0]	100020007	1			T1	22742		T2	3152		T3	159163
all_values[0]	auto[1]	auto[1]	507219	1			T1	221		T2	27		T3	455
all_values[1]	auto[0]	auto[0]	186197	1			T1	330		T6	1726		T10	67
all_values[1]	auto[0]	auto[1]	1645	1			T1	1		T6	10		T10	6
all_values[1]	auto[1]	auto[0]	100000908	1			T1	22412		T2	3152		T3	159164
all_values[1]	auto[1]	auto[1]	507678	1			T1	220		T2	27		T3	457
all_values[2]	auto[0]	auto[0]	149803	1			T1	631		T6	752		T5	9
all_values[2]	auto[0]	auto[1]	1438	1			T1	4		T6	11		T5	6
all_values[2]	auto[1]	auto[0]	100037302	1			T1	22111		T2	3152		T3	159164
all_values[2]	auto[1]	auto[1]	507885	1			T1	217		T2	27		T3	457