Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339024 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
353076 |
1 |
|
|
T1 |
282 |
|
T2 |
52 |
|
T3 |
618 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173214 |
1 |
|
|
T1 |
74 |
|
T2 |
10 |
|
T3 |
170 |
lower_val |
171422 |
1 |
|
|
T1 |
65 |
|
T2 |
20 |
|
T3 |
143 |
zero_val |
1855 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
258648 |
1 |
|
|
T1 |
66 |
|
T2 |
16 |
|
T3 |
158 |
lower_val |
256826 |
1 |
|
|
T1 |
88 |
|
T2 |
12 |
|
T3 |
162 |
zero_val |
176626 |
1 |
|
|
T1 |
130 |
|
T2 |
26 |
|
T3 |
300 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42517 |
1 |
|
|
T6 |
18 |
|
T10 |
4 |
|
T54 |
1 |
higher_val |
higher_val |
auto[1] |
22572 |
1 |
|
|
T1 |
17 |
|
T2 |
2 |
|
T3 |
47 |
higher_val |
lower_val |
auto[0] |
41993 |
1 |
|
|
T2 |
1 |
|
T6 |
20 |
|
T10 |
3 |
higher_val |
lower_val |
auto[1] |
22046 |
1 |
|
|
T1 |
22 |
|
T2 |
3 |
|
T3 |
39 |
higher_val |
zero_val |
auto[0] |
100 |
1 |
|
|
T6 |
1 |
|
T7 |
1 |
|
T42 |
1 |
higher_val |
zero_val |
auto[1] |
43986 |
1 |
|
|
T1 |
35 |
|
T2 |
4 |
|
T3 |
84 |
lower_val |
higher_val |
auto[0] |
41976 |
1 |
|
|
T6 |
20 |
|
T10 |
1 |
|
T54 |
7 |
lower_val |
higher_val |
auto[1] |
21873 |
1 |
|
|
T1 |
14 |
|
T2 |
3 |
|
T3 |
41 |
lower_val |
lower_val |
auto[0] |
41828 |
1 |
|
|
T6 |
24 |
|
T10 |
3 |
|
T54 |
2 |
lower_val |
lower_val |
auto[1] |
21909 |
1 |
|
|
T1 |
24 |
|
T2 |
6 |
|
T3 |
44 |
lower_val |
zero_val |
auto[0] |
108 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
lower_val |
zero_val |
auto[1] |
43728 |
1 |
|
|
T1 |
26 |
|
T2 |
11 |
|
T3 |
57 |
zero_val |
higher_val |
auto[0] |
540 |
1 |
|
|
T6 |
2 |
|
T186 |
4 |
|
T187 |
3 |
zero_val |
higher_val |
auto[1] |
144 |
1 |
|
|
T84 |
2 |
|
T29 |
4 |
|
T188 |
1 |
zero_val |
lower_val |
auto[0] |
539 |
1 |
|
|
T2 |
1 |
|
T6 |
2 |
|
T10 |
1 |
zero_val |
lower_val |
auto[1] |
130 |
1 |
|
|
T189 |
1 |
|
T29 |
2 |
|
T188 |
2 |
zero_val |
zero_val |
auto[0] |
288 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T6 |
1 |
zero_val |
zero_val |
auto[1] |
214 |
1 |
|
|
T40 |
2 |
|
T189 |
1 |
|
T29 |
2 |