Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9059	1			T3	24		T6	9		T5	17
len_5001_7500	14610	1			T3	24		T6	20		T5	17
len_2501_5000	9255	1			T3	24		T6	4		T5	17
len_1025_2500	5449	1			T3	14		T6	2		T5	10
len_769_1024	6014	1			T1	36		T2	6		T3	2
len_513_768	6352	1			T1	42		T2	6		T3	3
len_257_512	20811	1			T1	34		T2	4		T3	2
len_0_256	257183	1			T1	30		T2	1		T3	211
len_keccak_block_sizes[72]	728	1			T3	2		T5	2		T8	1
len_keccak_block_sizes[104]	625	1			T3	2		T5	2		T42	2
len_keccak_block_sizes[136]	518	1			T1	1		T5	2		T186	3
len_keccak_block_sizes[144]	422	1			T5	2		T186	3		T190	2
len_keccak_block_sizes[168]	319	1			T186	3		T128	1		T189	3
len_1	757	1			T3	2		T5	2		T40	2
len_0	1226	1			T2	1		T3	2		T6	1