Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100696428	1			T1	22963		T2	3179		T3	159621
all_pins[1]	100696428	1			T1	22963		T2	3179		T3	159621
all_pins[2]	100696428	1			T1	22963		T2	3179		T3	159621

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301311738	1			T1	68606		T2	6349		T3	478408
values[0x1]	777546	1			T1	283		T2	3188		T3	455
transitions[0x0=>0x1]	775736	1			T1	283		T2	3170		T3	455
transitions[0x1=>0x0]	775762	1			T1	283		T2	3171		T3	455

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100189209	1			T1	22742		T2	3152		T3	159166
all_pins[0]	values[0x1]	507219	1			T1	221		T2	27		T3	455
all_pins[0]	transitions[0x0=>0x1]	507204	1			T1	221		T2	27		T3	455
all_pins[0]	transitions[0x1=>0x0]	5408	1			T1	62		T6	24		T7	1
all_pins[1]	values[0x0]	100691005	1			T1	22901		T2	3179		T3	159621
all_pins[1]	values[0x1]	5423	1			T1	62		T6	24		T7	1
all_pins[1]	transitions[0x0=>0x1]	5224	1			T1	62		T6	24		T7	1
all_pins[1]	transitions[0x1=>0x0]	264705	1			T2	3161		T8	176		T33	770
all_pins[2]	values[0x0]	100431524	1			T1	22963		T2	18		T3	159621
all_pins[2]	values[0x1]	264904	1			T2	3161		T8	176		T33	770
all_pins[2]	transitions[0x0=>0x1]	263308	1			T2	3143		T8	176		T33	769
all_pins[2]	transitions[0x1=>0x0]	505649	1			T1	221		T2	10		T3	455