Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339803 |
1 |
|
|
T1 |
140 |
|
T2 |
32 |
|
T3 |
295 |
auto[1] |
3336 |
1 |
|
|
T2 |
5 |
|
T6 |
8 |
|
T8 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306456 |
1 |
|
|
T1 |
49 |
|
T2 |
23 |
|
T3 |
295 |
auto[1] |
36683 |
1 |
|
|
T1 |
91 |
|
T2 |
14 |
|
T6 |
77 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329931 |
1 |
|
|
T2 |
26 |
|
T3 |
295 |
|
T6 |
86 |
auto[1] |
13208 |
1 |
|
|
T1 |
140 |
|
T2 |
11 |
|
T6 |
17 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13208 |
1 |
|
|
T1 |
140 |
|
T2 |
11 |
|
T6 |
17 |
sw_kmac_invalid_sideload |
329931 |
1 |
|
|
T2 |
26 |
|
T3 |
295 |
|
T6 |
86 |
app_valid_sideload |
13208 |
1 |
|
|
T1 |
140 |
|
T2 |
11 |
|
T6 |
17 |
app_invalid_sideload |
329931 |
1 |
|
|
T2 |
26 |
|
T3 |
295 |
|
T6 |
86 |