Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10573456 |
1 |
|
|
T1 |
23717 |
|
T2 |
3093 |
|
T3 |
3720 |
auto[1] |
10573417 |
1 |
|
|
T1 |
23717 |
|
T2 |
3093 |
|
T3 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20910327 |
1 |
|
|
T1 |
47242 |
|
T2 |
6166 |
|
T3 |
7440 |
triple_byte_access |
78550 |
1 |
|
|
T1 |
50 |
|
T2 |
6 |
|
T6 |
24 |
halfword_access |
79350 |
1 |
|
|
T1 |
78 |
|
T2 |
10 |
|
T6 |
26 |
byte_access |
78646 |
1 |
|
|
T1 |
64 |
|
T2 |
4 |
|
T6 |
48 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10455183 |
1 |
|
|
T1 |
23621 |
|
T2 |
3083 |
|
T3 |
3720 |
auto[0] |
triple_byte_access |
39275 |
1 |
|
|
T1 |
25 |
|
T2 |
3 |
|
T6 |
12 |
auto[0] |
halfword_access |
39675 |
1 |
|
|
T1 |
39 |
|
T2 |
5 |
|
T6 |
13 |
auto[0] |
byte_access |
39323 |
1 |
|
|
T1 |
32 |
|
T2 |
2 |
|
T6 |
24 |
auto[1] |
word_access |
10455144 |
1 |
|
|
T1 |
23621 |
|
T2 |
3083 |
|
T3 |
3720 |
auto[1] |
triple_byte_access |
39275 |
1 |
|
|
T1 |
25 |
|
T2 |
3 |
|
T6 |
12 |
auto[1] |
halfword_access |
39675 |
1 |
|
|
T1 |
39 |
|
T2 |
5 |
|
T6 |
13 |
auto[1] |
byte_access |
39323 |
1 |
|
|
T1 |
32 |
|
T2 |
2 |
|
T6 |
24 |