Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100833076	1			T1	450379		T2	1243		T3	251
all_values[1]	100833076	1			T1	450379		T2	1243		T3	251
all_values[2]	100833076	1			T1	450379		T2	1243		T3	251

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

556873

1

T1

6

T2

24

T3

6

auto[1]

301942355

1

T1

135113

T2

3705

T3

747

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300961365

1

T1

134088

T2

3180

T3

708

auto[1]

1537863

1

T1

10251

T2

549

T3

45

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197799	1			T1	1		T4	1		T5	1614
all_values[0]	auto[0]	auto[1]	2268	1			T1	2		T5	12		T15	2
all_values[0]	auto[1]	auto[0]	100122656	1			T1	446961		T2	1060		T3	236
all_values[0]	auto[1]	auto[1]	510353	1			T1	3415		T2	183		T3	15
all_values[1]	auto[0]	auto[0]	171420	1			T1	1		T2	7		T3	5
all_values[1]	auto[0]	auto[1]	1675	1			T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[0]	100149035	1			T1	446961		T2	1053		T3	231
all_values[1]	auto[1]	auto[1]	510946	1			T1	3415		T2	182		T3	14
all_values[2]	auto[0]	auto[0]	182041	1			T2	13		T12	2		T4	487
all_values[2]	auto[0]	auto[1]	1670	1			T2	3		T4	6		T14	1
all_values[2]	auto[1]	auto[0]	100138414	1			T1	446962		T2	1047		T3	236
all_values[2]	auto[1]	auto[1]	510951	1			T1	3417		T2	180		T3	15