Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347860 |
1 |
|
|
T1 |
4530 |
|
T2 |
242 |
|
T3 |
2 |
auto[1] |
350322 |
1 |
|
|
T3 |
16 |
|
T11 |
392 |
|
T4 |
356 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175224 |
1 |
|
|
T1 |
1116 |
|
T2 |
42 |
|
T3 |
4 |
lower_val |
172591 |
1 |
|
|
T1 |
1049 |
|
T2 |
80 |
|
T3 |
4 |
zero_val |
1875 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261386 |
1 |
|
|
T1 |
2240 |
|
T2 |
104 |
|
T3 |
6 |
lower_val |
261200 |
1 |
|
|
T1 |
2290 |
|
T2 |
138 |
|
T3 |
2 |
zero_val |
175596 |
1 |
|
|
T3 |
10 |
|
T11 |
178 |
|
T4 |
184 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43164 |
1 |
|
|
T1 |
549 |
|
T2 |
23 |
|
T12 |
41 |
higher_val |
higher_val |
auto[1] |
22145 |
1 |
|
|
T3 |
2 |
|
T11 |
29 |
|
T4 |
20 |
higher_val |
lower_val |
auto[0] |
43576 |
1 |
|
|
T1 |
567 |
|
T2 |
19 |
|
T12 |
48 |
higher_val |
lower_val |
auto[1] |
22064 |
1 |
|
|
T3 |
1 |
|
T11 |
35 |
|
T4 |
24 |
higher_val |
zero_val |
auto[0] |
87 |
1 |
|
|
T99 |
1 |
|
T31 |
1 |
|
T27 |
1 |
higher_val |
zero_val |
auto[1] |
44188 |
1 |
|
|
T3 |
1 |
|
T11 |
54 |
|
T4 |
54 |
lower_val |
higher_val |
auto[0] |
42834 |
1 |
|
|
T1 |
531 |
|
T2 |
28 |
|
T12 |
34 |
lower_val |
higher_val |
auto[1] |
21689 |
1 |
|
|
T3 |
1 |
|
T11 |
20 |
|
T4 |
19 |
lower_val |
lower_val |
auto[0] |
42788 |
1 |
|
|
T1 |
518 |
|
T2 |
52 |
|
T12 |
32 |
lower_val |
lower_val |
auto[1] |
21528 |
1 |
|
|
T11 |
18 |
|
T4 |
25 |
|
T5 |
8 |
lower_val |
zero_val |
auto[0] |
94 |
1 |
|
|
T3 |
1 |
|
T15 |
1 |
|
T39 |
1 |
lower_val |
zero_val |
auto[1] |
43658 |
1 |
|
|
T3 |
2 |
|
T11 |
26 |
|
T4 |
37 |
zero_val |
higher_val |
auto[0] |
550 |
1 |
|
|
T2 |
2 |
|
T4 |
1 |
|
T6 |
1 |
zero_val |
higher_val |
auto[1] |
145 |
1 |
|
|
T15 |
1 |
|
T190 |
3 |
|
T65 |
1 |
zero_val |
lower_val |
auto[0] |
586 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
137 |
1 |
|
|
T4 |
1 |
|
T190 |
3 |
|
T191 |
2 |
zero_val |
zero_val |
auto[0] |
251 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T5 |
1 |
zero_val |
zero_val |
auto[1] |
206 |
1 |
|
|
T4 |
1 |
|
T15 |
3 |
|
T190 |
2 |