Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100833076	1			T1	450379		T2	1243		T3	251
all_pins[1]	100833076	1			T1	450379		T2	1243		T3	251
all_pins[2]	100833076	1			T1	450379		T2	1243		T3	251

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301616015	1			T1	134772		T2	3546		T3	738
values[0x1]	883213	1			T1	3415		T2	183		T3	15
transitions[0x0=>0x1]	880722	1			T1	3415		T2	183		T3	15
transitions[0x1=>0x0]	880744	1			T1	3415		T2	183		T3	15

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100322723	1			T1	446964		T2	1060		T3	236
all_pins[0]	values[0x1]	510353	1			T1	3415		T2	183		T3	15
all_pins[0]	transitions[0x0=>0x1]	510345	1			T1	3415		T2	183		T3	15
all_pins[0]	transitions[0x1=>0x0]	6511	1			T6	13		T7	32		T8	32
all_pins[1]	values[0x0]	100826557	1			T1	450379		T2	1243		T3	251
all_pins[1]	values[0x1]	6519	1			T6	13		T7	32		T8	32
all_pins[1]	transitions[0x0=>0x1]	6301	1			T6	13		T7	32		T30	77
all_pins[1]	transitions[0x1=>0x0]	366123	1			T4	8221		T8	14156		T30	962
all_pins[2]	values[0x0]	100466735	1			T1	450379		T2	1243		T3	251
all_pins[2]	values[0x1]	366341	1			T4	8221		T8	14188		T30	962
all_pins[2]	transitions[0x0=>0x1]	364076	1			T4	8167		T8	14091		T30	962
all_pins[2]	transitions[0x1=>0x0]	508110	1			T1	3415		T2	183		T3	15