Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	730	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5820	1			T11	22		T4	17		T5	8
len_601_800	13368	1			T11	55		T4	36		T5	11
len_401_600	8670	1			T11	38		T4	24		T5	13
len_201_400	16489	1			T1	251		T11	19		T4	14
len_65_200	74094	1			T1	680		T2	62		T11	5
len_min_for_xof_require_squeeze	1011	1			T1	10		T2	2		T15	10
len_keccak_block_sizes[72]	755	1			T1	5		T4	1		T15	5
len_keccak_block_sizes[104]	758	1			T1	5		T4	1		T5	1
len_keccak_block_sizes[136]	752	1			T1	5		T15	5		T192	9
len_keccak_block_sizes[144]	286	1			T1	5		T15	5		T30	1
len_keccak_block_sizes[168]	292	1			T1	5		T15	5		T6	1
len_datapath_width	14136	1			T1	5		T2	1		T3	3
len_2_63	214160	1			T1	1329		T2	58		T3	6
len_1	46	1			T10	1		T73	1		T159	1