Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11064542 |
1 |
|
|
T1 |
47900 |
|
T2 |
4769 |
|
T3 |
96 |
auto[1] |
11064435 |
1 |
|
|
T1 |
47900 |
|
T2 |
4769 |
|
T3 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21887585 |
1 |
|
|
T1 |
93928 |
|
T2 |
9364 |
|
T3 |
192 |
triple_byte_access |
80292 |
1 |
|
|
T1 |
620 |
|
T2 |
56 |
|
T11 |
66 |
halfword_access |
81194 |
1 |
|
|
T1 |
632 |
|
T2 |
62 |
|
T11 |
74 |
byte_access |
79906 |
1 |
|
|
T1 |
620 |
|
T2 |
56 |
|
T11 |
56 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10943846 |
1 |
|
|
T1 |
46964 |
|
T2 |
4682 |
|
T3 |
96 |
auto[0] |
triple_byte_access |
40146 |
1 |
|
|
T1 |
310 |
|
T2 |
28 |
|
T11 |
33 |
auto[0] |
halfword_access |
40597 |
1 |
|
|
T1 |
316 |
|
T2 |
31 |
|
T11 |
37 |
auto[0] |
byte_access |
39953 |
1 |
|
|
T1 |
310 |
|
T2 |
28 |
|
T11 |
28 |
auto[1] |
word_access |
10943739 |
1 |
|
|
T1 |
46964 |
|
T2 |
4682 |
|
T3 |
96 |
auto[1] |
triple_byte_access |
40146 |
1 |
|
|
T1 |
310 |
|
T2 |
28 |
|
T11 |
33 |
auto[1] |
halfword_access |
40597 |
1 |
|
|
T1 |
316 |
|
T2 |
31 |
|
T11 |
37 |
auto[1] |
byte_access |
39953 |
1 |
|
|
T1 |
310 |
|
T2 |
28 |
|
T11 |
28 |