Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100439771	1			T1	162707		T2	216457		T3	14623
all_values[1]	100439771	1			T1	162707		T2	216457		T3	14623
all_values[2]	100439771	1			T1	162707		T2	216457		T3	14623

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497183

1

T1

3

T2

3

T3

461

auto[1]

300822130

1

T1

488118

T2

649368

T3

43408

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299788209

1

T1

486744

T2

647697

T3

43428

auto[1]

1531104

1

T1

1377

T2

1674

T3

441

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	149403	1			T1	1		T3	375		T7	617
all_values[0]	auto[0]	auto[1]	2146	1			T1	2		T3	6		T7	6
all_values[0]	auto[1]	auto[0]	99780000	1			T1	162247		T2	215899		T3	14101
all_values[0]	auto[1]	auto[1]	508222	1			T1	457		T2	558		T3	141
all_values[1]	auto[0]	auto[0]	197399	1			T3	38		T7	378		T34	1
all_values[1]	auto[0]	auto[1]	1643	1			T3	2		T7	3		T34	2
all_values[1]	auto[1]	auto[0]	99732004	1			T1	162248		T2	215899		T3	14438
all_values[1]	auto[1]	auto[1]	508725	1			T1	459		T2	558		T3	145
all_values[2]	auto[0]	auto[0]	145040	1			T2	2		T3	38		T7	377
all_values[2]	auto[0]	auto[1]	1552	1			T2	1		T3	2		T7	3
all_values[2]	auto[1]	auto[0]	99784363	1			T1	162248		T2	215897		T3	14438
all_values[2]	auto[1]	auto[1]	508816	1			T1	459		T2	557		T3	145