Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323858 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
371408 |
1 |
|
|
T1 |
618 |
|
T2 |
746 |
|
T3 |
204 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173588 |
1 |
|
|
T1 |
128 |
|
T2 |
188 |
|
T3 |
67 |
lower_val |
173218 |
1 |
|
|
T1 |
185 |
|
T2 |
195 |
|
T3 |
52 |
zero_val |
1869 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254810 |
1 |
|
|
T1 |
124 |
|
T2 |
192 |
|
T3 |
52 |
lower_val |
254292 |
1 |
|
|
T1 |
174 |
|
T2 |
196 |
|
T3 |
48 |
zero_val |
186164 |
1 |
|
|
T1 |
322 |
|
T2 |
360 |
|
T3 |
106 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
39954 |
1 |
|
|
T2 |
1 |
|
T7 |
39 |
|
T32 |
37 |
higher_val |
higher_val |
auto[1] |
23419 |
1 |
|
|
T1 |
30 |
|
T2 |
49 |
|
T3 |
15 |
higher_val |
lower_val |
auto[0] |
40576 |
1 |
|
|
T7 |
31 |
|
T32 |
53 |
|
T33 |
558 |
higher_val |
lower_val |
auto[1] |
23005 |
1 |
|
|
T1 |
33 |
|
T2 |
59 |
|
T3 |
19 |
higher_val |
zero_val |
auto[0] |
84 |
1 |
|
|
T17 |
2 |
|
T92 |
1 |
|
T189 |
1 |
higher_val |
zero_val |
auto[1] |
46550 |
1 |
|
|
T1 |
65 |
|
T2 |
79 |
|
T3 |
33 |
lower_val |
higher_val |
auto[0] |
40470 |
1 |
|
|
T7 |
45 |
|
T32 |
42 |
|
T33 |
600 |
lower_val |
higher_val |
auto[1] |
23290 |
1 |
|
|
T1 |
38 |
|
T2 |
41 |
|
T3 |
14 |
lower_val |
lower_val |
auto[0] |
40089 |
1 |
|
|
T7 |
37 |
|
T32 |
38 |
|
T33 |
530 |
lower_val |
lower_val |
auto[1] |
23098 |
1 |
|
|
T1 |
41 |
|
T2 |
54 |
|
T3 |
6 |
lower_val |
zero_val |
auto[0] |
87 |
1 |
|
|
T16 |
1 |
|
T17 |
1 |
|
T190 |
1 |
lower_val |
zero_val |
auto[1] |
46184 |
1 |
|
|
T1 |
106 |
|
T2 |
100 |
|
T3 |
32 |
zero_val |
higher_val |
auto[0] |
551 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
153 |
1 |
|
|
T9 |
4 |
|
T16 |
1 |
|
T17 |
2 |
zero_val |
lower_val |
auto[0] |
537 |
1 |
|
|
T7 |
2 |
|
T32 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[1] |
148 |
1 |
|
|
T9 |
2 |
|
T16 |
3 |
|
T38 |
3 |
zero_val |
zero_val |
auto[0] |
250 |
1 |
|
|
T8 |
1 |
|
T9 |
2 |
|
T38 |
1 |
zero_val |
zero_val |
auto[1] |
230 |
1 |
|
|
T16 |
4 |
|
T38 |
1 |
|
T17 |
1 |