Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10346	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	9054	1			T1	24		T2	19		T33	30
len_5001_7500	14323	1			T1	24		T2	18		T33	30
len_2501_5000	9261	1			T1	24		T2	18		T33	30
len_1025_2500	5391	1			T1	14		T2	11		T33	16
len_769_1024	6448	1			T1	2		T2	2		T3	21
len_513_768	6961	1			T1	3		T2	2		T3	26
len_257_512	21258	1			T1	2		T2	2		T3	24
len_0_256	257496	1			T1	211		T2	274		T3	32
len_keccak_block_sizes[72]	718	1			T1	2		T2	2		T32	1
len_keccak_block_sizes[104]	628	1			T1	2		T2	2		T33	3
len_keccak_block_sizes[136]	526	1			T2	2		T32	1		T33	3
len_keccak_block_sizes[144]	428	1			T32	1		T33	3		T74	3
len_keccak_block_sizes[168]	331	1			T33	3		T74	3		T138	3
len_1	755	1			T1	2		T2	2		T33	3
len_0	1207	1			T1	2		T2	2		T7	2