Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100439771	1			T1	162707		T2	216457		T3	14623
all_pins[1]	100439771	1			T1	162707		T2	216457		T3	14623
all_pins[2]	100439771	1			T1	162707		T2	216457		T3	14623

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300506054	1			T1	487664		T2	648813		T3	43728
values[0x1]	813259	1			T1	457		T2	558		T3	141
transitions[0x0=>0x1]	811204	1			T1	457		T2	558		T3	141
transitions[0x1=>0x0]	811235	1			T1	457		T2	558		T3	141

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99931549	1			T1	162250		T2	215899		T3	14482
all_pins[0]	values[0x1]	508222	1			T1	457		T2	558		T3	141
all_pins[0]	transitions[0x0=>0x1]	508216	1			T1	457		T2	558		T3	141
all_pins[0]	transitions[0x1=>0x0]	6023	1			T32	79		T9	28		T36	2
all_pins[1]	values[0x0]	100433742	1			T1	162707		T2	216457		T3	14623
all_pins[1]	values[0x1]	6029	1			T32	79		T9	28		T36	2
all_pins[1]	transitions[0x0=>0x1]	5771	1			T32	79		T9	24		T36	2
all_pins[1]	transitions[0x1=>0x0]	298750	1			T7	6828		T9	3427		T16	1752
all_pins[2]	values[0x0]	100140763	1			T1	162707		T2	216457		T3	14623
all_pins[2]	values[0x1]	299008	1			T7	6828		T9	3431		T16	1752
all_pins[2]	transitions[0x0=>0x1]	297217	1			T7	6784		T9	3403		T16	1743
all_pins[2]	transitions[0x1=>0x0]	506462	1			T1	457		T2	558		T3	141