Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	676	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5534	1			T3	13		T7	15		T32	34
len_601_800	12730	1			T3	37		T7	60		T32	62
len_401_600	8388	1			T3	21		T7	34		T32	38
len_201_400	16551	1			T3	14		T7	18		T32	18
len_65_200	73617	1			T3	12		T7	31		T32	12
len_min_for_xof_require_squeeze	992	1			T33	9		T8	1		T74	10
len_keccak_block_sizes[72]	750	1			T3	1		T7	1		T32	1
len_keccak_block_sizes[104]	746	1			T7	1		T33	9		T74	5
len_keccak_block_sizes[136]	744	1			T33	9		T74	5		T39	1
len_keccak_block_sizes[144]	278	1			T74	5		T191	1		T65	1
len_keccak_block_sizes[168]	290	1			T9	2		T74	5		T192	5
len_datapath_width	14190	1			T3	1		T7	1		T33	9
len_2_63	214119	1			T1	310		T2	374		T3	4
len_1	61	1			T32	1		T193	1		T194	1