Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98345322	1			T1	17950		T2	273		T3	290
all_values[1]	98345322	1			T1	17950		T2	273		T3	290
all_values[2]	98345322	1			T1	17950		T2	273		T3	290

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

549168

1

T1

3

T2

36

T3

84

auto[1]

294486798

1

T1

53847

T2

783

T3

786

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

293519796

1

T1

53358

T2

780

T3

822

auto[1]

1516170

1

T1

492

T2

39

T3

48

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179937	1			T1	1		T2	4		T3	74
all_values[0]	auto[0]	auto[1]	2155	1			T2	2		T3	10		T7	2
all_values[0]	auto[1]	auto[0]	97659995	1			T1	17785		T2	256		T3	200
all_values[0]	auto[1]	auto[1]	503235	1			T1	164		T2	11		T3	6
all_values[1]	auto[0]	auto[0]	209261	1			T1	1		T2	12		T30	2
all_values[1]	auto[0]	auto[1]	1769	1			T2	3		T30	1		T7	2
all_values[1]	auto[1]	auto[0]	97630671	1			T1	17785		T2	248		T3	274
all_values[1]	auto[1]	auto[1]	503621	1			T1	164		T2	10		T3	16
all_values[2]	auto[0]	auto[0]	154441	1			T1	1		T2	12		T7	92
all_values[2]	auto[0]	auto[1]	1605	1			T2	3		T7	2		T31	2
all_values[2]	auto[1]	auto[0]	97685491	1			T1	17785		T2	248		T3	274
all_values[2]	auto[1]	auto[1]	503785	1			T1	164		T2	10		T3	16