Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356296 |
1 |
|
|
T1 |
354 |
|
T2 |
18 |
|
T3 |
18 |
auto[1] |
331390 |
1 |
|
|
T29 |
60 |
|
T8 |
194 |
|
T28 |
128 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171322 |
1 |
|
|
T1 |
92 |
|
T2 |
4 |
|
T3 |
2 |
lower_val |
170894 |
1 |
|
|
T1 |
99 |
|
T2 |
8 |
|
T3 |
5 |
zero_val |
1816 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261078 |
1 |
|
|
T1 |
180 |
|
T2 |
8 |
|
T3 |
4 |
lower_val |
260234 |
1 |
|
|
T1 |
174 |
|
T2 |
10 |
|
T3 |
14 |
zero_val |
166374 |
1 |
|
|
T29 |
28 |
|
T8 |
100 |
|
T28 |
64 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44180 |
1 |
|
|
T1 |
47 |
|
T2 |
2 |
|
T3 |
1 |
higher_val |
higher_val |
auto[1] |
20874 |
1 |
|
|
T29 |
6 |
|
T8 |
13 |
|
T28 |
16 |
higher_val |
lower_val |
auto[0] |
44256 |
1 |
|
|
T1 |
45 |
|
T2 |
2 |
|
T3 |
1 |
higher_val |
lower_val |
auto[1] |
20587 |
1 |
|
|
T29 |
1 |
|
T8 |
17 |
|
T28 |
7 |
higher_val |
zero_val |
auto[0] |
102 |
1 |
|
|
T8 |
2 |
|
T35 |
2 |
|
T20 |
2 |
higher_val |
zero_val |
auto[1] |
41323 |
1 |
|
|
T29 |
6 |
|
T8 |
19 |
|
T28 |
22 |
lower_val |
higher_val |
auto[0] |
44191 |
1 |
|
|
T1 |
48 |
|
T2 |
3 |
|
T3 |
2 |
lower_val |
higher_val |
auto[1] |
20614 |
1 |
|
|
T29 |
3 |
|
T8 |
9 |
|
T28 |
5 |
lower_val |
lower_val |
auto[0] |
44047 |
1 |
|
|
T1 |
51 |
|
T2 |
5 |
|
T3 |
3 |
lower_val |
lower_val |
auto[1] |
20751 |
1 |
|
|
T29 |
3 |
|
T8 |
10 |
|
T28 |
7 |
lower_val |
zero_val |
auto[0] |
96 |
1 |
|
|
T28 |
1 |
|
T35 |
1 |
|
T15 |
1 |
lower_val |
zero_val |
auto[1] |
41195 |
1 |
|
|
T29 |
10 |
|
T8 |
24 |
|
T28 |
13 |
zero_val |
higher_val |
auto[0] |
554 |
1 |
|
|
T30 |
1 |
|
T8 |
2 |
|
T33 |
1 |
zero_val |
higher_val |
auto[1] |
138 |
1 |
|
|
T8 |
1 |
|
T38 |
2 |
|
T15 |
2 |
zero_val |
lower_val |
auto[0] |
529 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
129 |
1 |
|
|
T8 |
2 |
|
T38 |
2 |
|
T16 |
2 |
zero_val |
zero_val |
auto[0] |
282 |
1 |
|
|
T8 |
1 |
|
T28 |
1 |
|
T54 |
1 |
zero_val |
zero_val |
auto[1] |
184 |
1 |
|
|
T8 |
1 |
|
T38 |
4 |
|
T16 |
1 |