Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98345322	1			T1	17950		T2	273		T3	290
all_pins[1]	98345322	1			T1	17950		T2	273		T3	290
all_pins[2]	98345322	1			T1	17950		T2	273		T3	290

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	294218704	1			T1	53636		T2	808		T3	863
values[0x1]	817262	1			T1	214		T2	11		T3	7
transitions[0x0=>0x1]	815209	1			T1	214		T2	11		T3	7
transitions[0x1=>0x0]	815226	1			T1	214		T2	11		T3	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97842087	1			T1	17786		T2	262		T3	284
all_pins[0]	values[0x1]	503235	1			T1	164		T2	11		T3	6
all_pins[0]	transitions[0x0=>0x1]	503221	1			T1	164		T2	11		T3	6
all_pins[0]	transitions[0x1=>0x0]	5124	1			T1	50		T3	1		T29	17
all_pins[1]	values[0x0]	98340184	1			T1	17900		T2	273		T3	289
all_pins[1]	values[0x1]	5138	1			T1	50		T3	1		T29	17
all_pins[1]	transitions[0x0=>0x1]	4987	1			T1	50		T3	1		T29	17
all_pins[1]	transitions[0x1=>0x0]	308738	1			T8	7396		T17	273		T15	1545
all_pins[2]	values[0x0]	98036433	1			T1	17950		T2	273		T3	290
all_pins[2]	values[0x1]	308889	1			T8	7396		T17	273		T15	1547
all_pins[2]	transitions[0x0=>0x1]	307001	1			T8	7346		T17	273		T15	1537
all_pins[2]	transitions[0x1=>0x0]	501364	1			T1	164		T2	11		T3	6