Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10502121 |
1 |
|
|
T1 |
21561 |
|
T2 |
96 |
|
T3 |
96 |
auto[1] |
10502065 |
1 |
|
|
T1 |
21561 |
|
T2 |
96 |
|
T3 |
96 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20768576 |
1 |
|
|
T1 |
42946 |
|
T2 |
192 |
|
T3 |
192 |
triple_byte_access |
78390 |
1 |
|
|
T1 |
68 |
|
T29 |
16 |
|
T7 |
8 |
halfword_access |
78842 |
1 |
|
|
T1 |
52 |
|
T29 |
14 |
|
T7 |
12 |
byte_access |
78378 |
1 |
|
|
T1 |
56 |
|
T29 |
16 |
|
T7 |
8 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10384316 |
1 |
|
|
T1 |
21473 |
|
T2 |
96 |
|
T3 |
96 |
auto[0] |
triple_byte_access |
39195 |
1 |
|
|
T1 |
34 |
|
T29 |
8 |
|
T7 |
4 |
auto[0] |
halfword_access |
39421 |
1 |
|
|
T1 |
26 |
|
T29 |
7 |
|
T7 |
6 |
auto[0] |
byte_access |
39189 |
1 |
|
|
T1 |
28 |
|
T29 |
8 |
|
T7 |
4 |
auto[1] |
word_access |
10384260 |
1 |
|
|
T1 |
21473 |
|
T2 |
96 |
|
T3 |
96 |
auto[1] |
triple_byte_access |
39195 |
1 |
|
|
T1 |
34 |
|
T29 |
8 |
|
T7 |
4 |
auto[1] |
halfword_access |
39421 |
1 |
|
|
T1 |
26 |
|
T29 |
7 |
|
T7 |
6 |
auto[1] |
byte_access |
39189 |
1 |
|
|
T1 |
28 |
|
T29 |
8 |
|
T7 |
4 |