Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99392951	1			T1	221		T2	9276		T7	806
all_values[1]	99392951	1			T1	221		T2	9276		T7	806
all_values[2]	99392951	1			T1	221		T2	9276		T7	806

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

472718

1

T1

663

T7

3

T21

1200

auto[1]

297706135

1

T2

27828

T7

2415

T21

89367

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296664183

1

T1

657

T2

27516

T7

2394

auto[1]

1514670

1

T1

6

T2

312

T7

24

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	158698	1			T1	219		T7	1		T21	596
all_values[0]	auto[0]	auto[1]	2119	1			T1	2		T21	4		T34	2
all_values[0]	auto[1]	auto[0]	98729363	1			T2	9172		T7	797		T21	29300
all_values[0]	auto[1]	auto[1]	502771	1			T2	104		T7	8		T21	289
all_values[1]	auto[0]	auto[0]	160641	1			T1	219		T7	1		T21	596
all_values[1]	auto[0]	auto[1]	1578	1			T1	2		T21	4		T22	1
all_values[1]	auto[1]	auto[0]	98727420	1			T2	9172		T7	797		T21	29300
all_values[1]	auto[1]	auto[1]	503312	1			T2	104		T7	8		T21	289
all_values[2]	auto[0]	auto[0]	148211	1			T1	219		T7	1		T34	11
all_values[2]	auto[0]	auto[1]	1471	1			T1	2		T34	3		T22	5
all_values[2]	auto[1]	auto[0]	98739850	1			T2	9172		T7	797		T21	29896
all_values[2]	auto[1]	auto[1]	503419	1			T2	104		T7	8		T21	293