Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
331426 |
1 |
|
|
T1 |
2 |
|
T2 |
138 |
|
T7 |
2 |
auto[1] |
355436 |
1 |
|
|
T7 |
14 |
|
T21 |
378 |
|
T22 |
52 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172357 |
1 |
|
|
T2 |
38 |
|
T7 |
3 |
|
T21 |
93 |
lower_val |
169385 |
1 |
|
|
T2 |
29 |
|
T7 |
2 |
|
T21 |
96 |
zero_val |
1823 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T7 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254432 |
1 |
|
|
T2 |
74 |
|
T7 |
6 |
|
T21 |
118 |
lower_val |
253534 |
1 |
|
|
T1 |
2 |
|
T2 |
64 |
|
T7 |
2 |
zero_val |
178896 |
1 |
|
|
T7 |
8 |
|
T21 |
184 |
|
T22 |
26 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41513 |
1 |
|
|
T2 |
25 |
|
T34 |
2 |
|
T36 |
6 |
higher_val |
higher_val |
auto[1] |
22378 |
1 |
|
|
T7 |
1 |
|
T21 |
23 |
|
T22 |
3 |
higher_val |
lower_val |
auto[0] |
41479 |
1 |
|
|
T2 |
13 |
|
T36 |
16 |
|
T37 |
32 |
higher_val |
lower_val |
auto[1] |
22110 |
1 |
|
|
T21 |
21 |
|
T22 |
2 |
|
T35 |
284 |
higher_val |
zero_val |
auto[0] |
77 |
1 |
|
|
T9 |
1 |
|
T64 |
1 |
|
T16 |
2 |
higher_val |
zero_val |
auto[1] |
44800 |
1 |
|
|
T7 |
2 |
|
T21 |
49 |
|
T22 |
3 |
lower_val |
higher_val |
auto[0] |
41101 |
1 |
|
|
T2 |
10 |
|
T34 |
2 |
|
T36 |
19 |
lower_val |
higher_val |
auto[1] |
21801 |
1 |
|
|
T21 |
30 |
|
T22 |
7 |
|
T35 |
253 |
lower_val |
lower_val |
auto[0] |
40709 |
1 |
|
|
T2 |
19 |
|
T34 |
2 |
|
T36 |
6 |
lower_val |
lower_val |
auto[1] |
21752 |
1 |
|
|
T21 |
22 |
|
T22 |
2 |
|
T35 |
285 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T21 |
1 |
|
T35 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
43944 |
1 |
|
|
T7 |
2 |
|
T21 |
43 |
|
T22 |
8 |
zero_val |
higher_val |
auto[0] |
552 |
1 |
|
|
T7 |
1 |
|
T8 |
1 |
|
T38 |
1 |
zero_val |
higher_val |
auto[1] |
137 |
1 |
|
|
T35 |
1 |
|
T38 |
1 |
|
T41 |
1 |
zero_val |
lower_val |
auto[0] |
532 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T34 |
1 |
zero_val |
lower_val |
auto[1] |
127 |
1 |
|
|
T38 |
2 |
|
T9 |
3 |
|
T63 |
2 |
zero_val |
zero_val |
auto[0] |
255 |
1 |
|
|
T21 |
1 |
|
T22 |
1 |
|
T35 |
1 |
zero_val |
zero_val |
auto[1] |
220 |
1 |
|
|
T35 |
3 |
|
T38 |
3 |
|
T9 |
3 |