Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.66	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	3	18	85.71
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	3	6	66.67	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	0	7	100.00	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	541	1			T18	28		T67	9		T68	6
auto[CmdProcess]	76	1			T22	3		T18	5		T67	2
auto[CmdManualRun]	251	1			T22	14		T18	18		T67	10
auto[CmdDone]	1174	1			T22	4		T23	3		T18	59

---

Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	3	6	66.67

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T4	1		T5	1		T6	1
auto[ErrSwPushedMsgFifo]	30	1			T18	2		T67	1		T24	2
auto[ErrSwIssuedCmdInAppActive]	56	1			T18	4		T24	2		T25	3
auto[ErrUnexpectedModeStrength]	496	1			T22	2		T23	1		T18	23
auto[ErrIncorrectFunctionName]	449	1			T18	26		T67	8		T68	6
auto[ErrSwCmdSequence]	1014	1			T22	19		T23	2		T18	55

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	335	1			T22	1		T18	21		T67	8
auto[Shake]	343	1			T22	12		T18	22		T67	1
auto[CShake]	1367	1			T22	8		T23	3		T18	67

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	690	1			T22	13		T18	39		T67	11
auto[L224]	237	1			T18	15		T67	5		T68	10
auto[L256]	683	1			T4	1		T22	5		T5	1
auto[L384]	253	1			T22	3		T18	9		T67	5
auto[L512]	232	1			T23	3		T18	12		T67	1

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

56

1

T18

4

T24

2

T25

3

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	0	7	100.00

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	141	1			T22	1		T18	7		T67	3
shake_224_invalid_cfg	36	1			T18	2		T68	2		T24	1
shake_384_invalid_cfg	28	1			T67	1		T68	1		T25	2
shake_512_invalid_cfg	33	1			T18	1		T172	1		T177	2
cshake_224_invalid_cfg	88	1			T18	5		T67	3		T68	2
cshake_384_invalid_cfg	95	1			T22	1		T18	5		T67	2
cshake_512_invalid_cfg	75	1			T23	1		T18	3		T67	1