Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99392951	1			T1	221		T2	9276		T7	806
all_pins[1]	99392951	1			T1	221		T2	9276		T7	806
all_pins[2]	99392951	1			T1	221		T2	9276		T7	806

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297350248	1			T1	663		T2	27724		T7	2410
values[0x1]	828605	1			T2	104		T7	8		T21	289
transitions[0x0=>0x1]	826305	1			T2	104		T7	8		T21	289
transitions[0x1=>0x0]	826333	1			T2	104		T7	8		T21	289

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98890180	1			T1	221		T2	9172		T7	798
all_pins[0]	values[0x1]	502771	1			T2	104		T7	8		T21	289
all_pins[0]	transitions[0x0=>0x1]	502763	1			T2	104		T7	8		T21	289
all_pins[0]	transitions[0x1=>0x0]	6214	1			T22	7		T66	66		T40	2
all_pins[1]	values[0x0]	99386729	1			T1	221		T2	9276		T7	806
all_pins[1]	values[0x1]	6222	1			T22	7		T66	66		T40	2
all_pins[1]	transitions[0x0=>0x1]	5869	1			T22	7		T66	66		T40	2
all_pins[1]	transitions[0x1=>0x0]	319259	1			T22	217		T9	2019		T23	48
all_pins[2]	values[0x0]	99073339	1			T1	221		T2	9276		T7	806
all_pins[2]	values[0x1]	319612	1			T22	217		T9	2019		T23	48
all_pins[2]	transitions[0x0=>0x1]	317673	1			T22	217		T9	2004		T23	48
all_pins[2]	transitions[0x1=>0x0]	500860	1			T2	104		T7	8		T21	289