Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337044 |
1 |
|
|
T1 |
1 |
|
T2 |
68 |
|
T7 |
9 |
auto[1] |
3130 |
1 |
|
|
T7 |
2 |
|
T4 |
1 |
|
T8 |
12 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
304031 |
1 |
|
|
T2 |
14 |
|
T7 |
4 |
|
T21 |
50 |
auto[1] |
36143 |
1 |
|
|
T1 |
1 |
|
T2 |
54 |
|
T7 |
7 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
327379 |
1 |
|
|
T1 |
1 |
|
T7 |
9 |
|
T34 |
9 |
auto[1] |
12795 |
1 |
|
|
T2 |
68 |
|
T7 |
2 |
|
T21 |
185 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
12795 |
1 |
|
|
T2 |
68 |
|
T7 |
2 |
|
T21 |
185 |
sw_kmac_invalid_sideload |
327379 |
1 |
|
|
T1 |
1 |
|
T7 |
9 |
|
T34 |
9 |
app_valid_sideload |
12795 |
1 |
|
|
T2 |
68 |
|
T7 |
2 |
|
T21 |
185 |
app_invalid_sideload |
327379 |
1 |
|
|
T1 |
1 |
|
T7 |
9 |
|
T34 |
9 |