Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10561480 |
1 |
|
|
T1 |
210 |
|
T2 |
10877 |
|
T7 |
772 |
auto[1] |
10561412 |
1 |
|
|
T1 |
210 |
|
T2 |
10877 |
|
T7 |
772 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20887613 |
1 |
|
|
T1 |
418 |
|
T2 |
21656 |
|
T7 |
1536 |
triple_byte_access |
78272 |
1 |
|
|
T2 |
26 |
|
T7 |
4 |
|
T21 |
102 |
halfword_access |
78990 |
1 |
|
|
T2 |
24 |
|
T21 |
90 |
|
T22 |
12 |
byte_access |
78017 |
1 |
|
|
T1 |
2 |
|
T2 |
48 |
|
T7 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10443840 |
1 |
|
|
T1 |
209 |
|
T2 |
10828 |
|
T7 |
768 |
auto[0] |
triple_byte_access |
39136 |
1 |
|
|
T2 |
13 |
|
T7 |
2 |
|
T21 |
51 |
auto[0] |
halfword_access |
39495 |
1 |
|
|
T2 |
12 |
|
T21 |
45 |
|
T22 |
6 |
auto[0] |
byte_access |
39009 |
1 |
|
|
T1 |
1 |
|
T2 |
24 |
|
T7 |
2 |
auto[1] |
word_access |
10443773 |
1 |
|
|
T1 |
209 |
|
T2 |
10828 |
|
T7 |
768 |
auto[1] |
triple_byte_access |
39136 |
1 |
|
|
T2 |
13 |
|
T7 |
2 |
|
T21 |
51 |
auto[1] |
halfword_access |
39495 |
1 |
|
|
T2 |
12 |
|
T21 |
45 |
|
T22 |
6 |
auto[1] |
byte_access |
39008 |
1 |
|
|
T1 |
1 |
|
T2 |
24 |
|
T7 |
2 |